Move all fecs methods related code to gr falcon unit and handle it
through generic gr.falocn.ctrl_ctxsw hal.
Following methods are moved from gr_gk20a.c to gr falcon unit.
fecs method and corresponding new fecs method def in gr_falcon.h:
gr_fecs_method_push_adr_discover_image_size_v ->
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_IMAGE_SIZE
gr_fecs_method_push_adr_discover_pm_image_size_v ->
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_PM_IMAGE_SIZE
gr_fecs_method_push_adr_discover_reglist_image_size_v ->
NVGPU_GR_FALCON_METHOD_REGLIST_DISCOVER_IMAGE_SIZE
gr_fecs_method_push_adr_set_reglist_bind_instance_v ->
NVGPU_GR_FALCON_METHOD_REGLIST_BIND_INSTANCE
gr_fecs_method_push_adr_set_reglist_virtual_address_v ->
NVGPU_GR_FALCON_METHOD_REGLIST_SET_VIRTUAL_ADDRESS
Following fecs methods are moved from obj_ctx.c to gr falcon unit.
gr_fecs_method_push_adr_bind_pointer_v ->
NVGPU_GR_FALCON_METHOD_ADDRESS_BIND_PTR
gr_fecs_method_push_adr_wfi_golden_save_v ->
NVGPU_GR_FALCON_METHOD_GOLDEN_IMAGE_SAVE
Following fecs methods are moved from gr_gp10b.c to gr falcon unit.
gr_fecs_method_push_adr_discover_preemption_image_size_v ->
NVGPU_GR_FALCON_METHOD_PREEMPT_IMAGE_SIZE
gr_fecs_method_push_adr_configure_interrupt_completion_option_v ->
NVGPU_GR_FALCON_METHOD_CONFIGURE_CTXSW_INTR
Following fecs method is moved from zcull_gm20b.c:
gr_fecs_method_push_adr_discover_zcull_image_size_v ->
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE
Following fecs method is moved from fecs_trace_gp10b.c:
gr_fecs_method_push_adr_write_timestamp_record_v
-> NVGPU_GR_FALCON_METHOD_FECS_TRACE_FLUSH
Added new HAL in gr falcon for moving fecs_current_ctx_data from
gr_gk20a.c to gr_falcon_gm20b.c.
u32 (*get_fecs_current_ctx_data)(struct gk20a *g,
struct nvgpu_mem *inst_block);
Added overlay for gm20b_gr_falcon_ctrl_ctxsw in newly added in
gr_falcon_gp10b.c for handling gp10b+ specific fecs methods:
gp10b_gr_falcon_ctrl_ctxsw
JIRA NVGPU-1881
Change-Id: I662d06f5176b29e6837d63c25e42de67505d48f5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087148
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Move handle_semaphore_pending to hal.gr.intr
gr_gk20a_handle_semaphore_pending function is moved from
gr_gk20a.c to common.gr.intr as nvgpu_gr_handle_semaphore_pending
JIRA NVGPU-3016
JIRA NVGPU-1891
Change-Id: Id731bb4169de9dcfff012e401165ad5a7f43bffa
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089173
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Move handle_notify_pending hal to hal.gr.intr
Move gk20a_gr_handle_notify_pending code from gr_gk20a.c to
common.gr.intr as nvgpu_gr_intr_handle_notify_pending function.
JIRA NVGPU-1891
JIRA NVGPU-3016
Change-Id: Ib3284a83253b03e5708674fce683331ee20b8213
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089172
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nvgpu_gr_obj_ctx_alloc_golden_ctx_image() right now uses global variable
g->gr.ctx_vars.golden_image_size to get size of golden image which is
then used to initialize local golden image
Use nvgpu_gr_obj_ctx_get_golden_image_size() API to get the size instead
of using global variable
Jira NVGPU-1887
Change-Id: I39b0cfe8f051c828e2b279c1836a259962c3d3bd
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089581
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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These HALs are used to initialize and set preeemption modes
g->ops.gr.init_ctxsw_preemption_mode()
g->ops.gr.set_ctxsw_preemption_mode()
g->ops.gr.update_ctxsw_preemption_mode()
They are all h/w independent except for the functional support for
GFXP/CILP preemption support which is only present on gp10b+ chips
Add a characteristics flag NVGPU_SUPPORT_PREEMPTION_GFXP for these
preemption modes and set this flag for gp10b+ chips
Use this flag and unify all above HALs into below common functions
nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode()
nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode()
nvgpu_gr_obj_ctx_update_ctxsw_preemption_mode()
vGPU specific code also directly calls below vGPU specific APIs
vgpu_gr_init_ctxsw_preemption_mode()
vgpu_gr_set_ctxsw_preemption_mode()
g->ops.gr.update_ctxsw_preemption_mode() is not needed for vGPU since
it is handled by vserver
Above g->ops.gr.*_ctxsw_preemption_mode() HALs are no more required
hence delete them
Jira NVGPU-1887
Change-Id: I9b3164bcf01e5e3c27e52369c9364e0ee23a9662
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088507
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gr_gk20a_commit_global_ctx_buffers() is h/w independent, hence move it
to common unit common.gr.obj_ctx and rename it as
nvgpu_gr_obj_ctx_commit_global_ctx_buffers()
Delete g->ops.gr.commit_global_ctx_buffers hal
Jira NVGPU-1887
Change-Id: If1c840237b8ba2c13bed40a4315810073756aeb9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088506
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Following functions are moved from gr_gk20a.c to common gr_falcon.c
gr_gk20a_disable_ctxsw -> nvgpu_gr_falcon_disable_ctxsw
gr_gk20a_enable_ctxsw -> nvgpu_gr_falcon_enable_ctxsw
gr_gk20a_halt_pipe -> nvgpu_gr_falcon_halt_pipe
Added new gr falcon hal to control ctxsw:
int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
u32 data, u32 *ret_val)
Parameters:
fecs_method: will be specified by a generic define provided in gr_falcon.h
header.
data: input data parameter (if any), set it to zero, if method did not
require any data input.
ret_val: pointer to expected output.
Added following ops for gr falcon:
int (*halt_pipe)(struct gk20a *g); -> this is moved from gr
int (*disable_ctxsw)(struct gk20a *g);
int (*enable_ctxsw)(struct gk20a *g);
JIRA NVGPU-1881
Change-Id: Idb3b7355b5a0bd3b9bb01f9f424c5d607616f540
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081308
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Add a new unit common.gr.obj_ctx which allocates and initializes GR
context. This unit also takes care of creating global golden image
used to initialize every context.
Add private header obj_ctx_priv.h that defines struct
nvgpu_gr_obj_ctx_golden_image
Add public header obj_ctx.h that exposes functions supported by new unit
This unit now exposes below API to allocate and initialize context
nvgpu_gr_obj_ctx_alloc()
Remove below functions from gk20a/gr_gk20a.c and move them to new unit
with below renames
gr_gk20a_fecs_ctx_bind_channel() -> nvgpu_gr_obj_ctx_bind_channel()
gr_gk20a_fecs_ctx_image_save() -> nvgpu_gr_obj_ctx_image_save()
gk20a_init_sw_bundle() -> nvgpu_gr_obj_ctx_alloc_sw_bundle()
gr_gk20a_alloc_gr_ctx() -> nvgpu_gr_obj_ctx_gr_ctx_alloc()
gr_gk20a_init_golden_ctx_image() ->
nvgpu_gr_obj_ctx_alloc_golden_ctx_image()
Use new APIs in gk20a_alloc_obj_ctx() to allocate context
For now this unit includes <nvgpu/gr/gr.h> and some h/w headers.
But they will be removed in follow up patches
Jira NVGPU-1887
Change-Id: Ib95ec1c19c5b74810f85c2feed8fdd63889d3d22
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087662
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Add new unit common.gr.setup that provides runtime setup interfaces to
other units outside of GR unit or to OS-specific code
Move zcull setup call to this unit.
New unit now exposes nvgpu_gr_setup_bind_ctxsw_zcull() to setup zcull
This API internally calls common.gr.zcull API nvgpu_gr_zcull_ctx_setup()
Add new hal g->ops.gr.setup.bind_ctxsw_zcull() and remove
g->ops.gr.zcull.bind_ctxsw_zcull()
Remove nvgpu_channel_gr_zcull_setup() from channel unit
Also remove ctx/subctx header includes sicne channel code need not
configure zcull
Remove gm20b_gr_bind_ctxsw_zcull() since binding is done from common
code
Jira NVGPU-1886
Change-Id: I6f04d19a8b8c003734702c5f6780a03ffc89b717
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2086602
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Remove locally defined timeout call in gr and use common timeout
call.
Replace nvgpu_gr_get_idle_timeout with nvgpu_get_poll_timeout function
Replace following defines to
NVGPU_GR_IDLE_CHECK_DEFAULT_US ---> POLL_DELAY_MIN_US
NVGPU_GR_IDLE_CHECK_MAX_US ---> POLL_DELAY_MIN_US
JIRA NVGPU-1885
Change-Id: I4514a9763fe0687680d50704bc9f22677a1a3df9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085031
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Code for secure/non-secure ctxsw booting spread across gr_gk20a.c
and gr_gm20b.c. With this change this code is move to gr falcon unit.
Ctxsw loading is now supported with 2 supported common functions:
1.Non secure boot:
int nvgpu_gr_falcon_load_ctxsw_ucode(struct gk20a *g);
2.Secure boot:
int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g);
Now gr ops function "int (*load_ctxsw_ucode)(struct gk20a *g);" is moved to
gr falcon ops and in chip hals it is set with secure/non-secure booting.
Non-secure booting: nvgpu_gr_falcon_load_ctxsw_ucode support ctxsw loading
in 2 methods: bit-banging uode or booting with bootloader
A. Common and hal functions for non-secure bit-banging ctxsw loading:
Common: static void nvgpu_gr_falcon_load_dmem(struct gk20a *g) ->
Hals: void (*load_gpccs_dmem)(struct gk20a *g,i
const u32 *ucode_u32_data, u32 size);
void (*load_fecs_dmem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
Common: static void nvgpu_gr_falcon_load_imem(struct gk20a *g) ->
Hals: void (*load_gpccs_imem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
void (*load_fecs_imem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
Other basic HALs:
void (*configure_fmodel)(struct gk20a *g); -> configure fmodel for ctxsw loading
void (*start_ucode)(struct gk20a *g); -> start running ctxcw ucode
B.Common and hal functions for non-secure ctxsw loading with bootloader
First get the ctxsw ucode using: nvgpu_gr_falcon_init_ctxsw_ucode, then
Common: static void nvgpu_gr_falcon_load_with_bootloader(struct gk20a *g)
void nvgpu_gr_falcon_bind_instblk((struct gk20a *g) ->
Hal: void (*bind_instblk)(struct gk20a *g, struct nvgpu_mem *mem, u64 inst_ptr);
Common: nvgpu_gr_falcon_load_ctxsw_ucode_segments ->
nvgpu_gr_falcon_load_ctxsw_ucode_header ->
nvgpu_gr_falcon_load_ctxsw_ucode_boot for both fecs and gpccs ->
Hals: void (*load_ctxsw_ucode_header)(struct gk20a *g, u32 reg_offset,
u32 boot_signature, u32 addr_code32, u32 addr_data32,
u32 code_size, u32 data_size);
void (*load_ctxsw_ucode_boot)(struct gk20a *g, u64 reg_offset, u32 boot_entry,
u32 addr_load32, u32 blocks, u32 dst);
Other basic HAL to get gpccs start offset:
u32 (*get_gpccs_start_reg_offset)(void);
C.Secure booting is support with gpmu and acr and with following additional
common function in gr falcon.
static void nvgpu_gr_falcon_load_gpccs_with_bootloader(struct gk20a *g) ->
nvgpu_gr_falcon_bind_instblk and nvgpu_gr_falcon_load_ctxsw_ucode_segments
Additional basic hals:
void (*start_gpccs)(struct gk20a *g);
void (*start_fecs)(struct gk20a *g);
Following ops from gr is removed, since it is not required to set by chip hals:
void (*falcon_load_ucode)(struct gk20a *g, u64 addr_base,
struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset);
Now this is handled by static common function:
static int nvgpu_gr_falcon_copy_ctxsw_ucode_segments( struct gk20a *g,
struct nvgpu_mem *dst, struct gk20a_ctxsw_ucode_segments *segments,
u32 *bootimage, u32 *code, u32 *data)
JIRA NVGPU-1881
Change-Id: I895a03faaf1a21286316befde24765c8b55075cf
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083388
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Move functions related to init_ctxsw_ucode to common
falcon from gr_gk20a.c. Modified code to call this new
function and modified function names in common falcon
to reflect new re-org.
JIRA NVGPU-1881
Change-Id: I389f5c902bfbec17cdb4b16840a5ba66f6b1e331
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081331
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Remove use of struct gk20a and struct gr_gk20a from common.gr.config
hal functions.
This requires a reference to struct gk20a *g for many nvgpu_* ops. Also,
nvgpu_gr_config is updated to include sm_count_per_tpc.
JIRA NVGPU-1884
Change-Id: I874c2b3970d97ef3940b74d8ef121a7261061670
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075681
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Change the global_ctx_buffer_index member in the nvgpu_gr_ctx struct
to be an enum nvgpu_gr_global_ctx_index. global_ctx_buffer_index is
used as an array of these indicies, but had been declared as an int.
This change resolves a number of MISRA Rule 10.3 violations for implicit
assignment of objects of different essential or narrower type.
In order to use this enum, it is moved out of global_ctx.h into a new
header file ctx_common.h that can be used by both ctx.h and global_ctx.h.
JIRA NVGPU-2955
Change-Id: I5e399ba3b0821d696aa0b9909d3bc6bbe99d274c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075753
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Move load_smid_config and program_sm_id_numbering hal functions to
corresponding hal files in hal.gr.init.
Add new hal for get_sm_id_size and new static function in common.gr
init code for gr_load_sm_id_config.
JIRA NVGPU-2951
Change-Id: I27755306d278db9fcd5ab60169a64057b2989ea8
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075875
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Move load_tpc_mask and setup_rop_mapping hal functions to hal.gr.init.
Existing load_tpc_mask hal code is split to two parts, one as a common
code in gr_load_tpc_mask and register write to init.tpc_mask hal
functions.
Modify pd_tpc_per_gpc and pd_skip_table_gpc hals in the
hal.gr.init to pass struct nvgpu_gr_config as a parameter.
JIRA NVGPU-2951
Change-Id: I52e26d0f023afa511a8cf8c3e4c54f45350be4ae
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2074892
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nvgpu_gr_ctx_load_golden_ctx_image() in common.gr.ctx unit programs
initial pm_mode in context. gk20a_alloc_obj_ctx() then disables pm_mode
ctxsw by default.
Fix this by disabling pm_mode ctxsw by default in
nvgpu_gr_ctx_load_golden_ctx_image() itself. Remove corresponding code
from gk20a_alloc_obj_ctx()
Jira NVGPU-1887
Change-Id: I6e1f83cefcb6229394da353e4cd87f1f5a0b10d4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076273
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Add below two new APIs to set preemption buffer in graphics context or
subcontext respectively
nvgpu_gr_ctx_set_preemption_buffer_va()
nvgpu_gr_subctx_set_preemption_buffer_va()
Remove g->ops.gr.set_preemption_buffer_va() hal and use above APIs to
set preemption buffer VA.
Jira NVGPU-1887
Change-Id: I38fb76eaf01d3fc73fd8104f30bcd89be9fa45b6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076272
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To avoid the other hal calls from gr_gv11b_init_fs_state
and gr_gm20b_init_fs_state hal, move the load_tpc_mask and
load_smid_config hal to nvgpu_gr_init_fs_state common gr function.
bes_zrop_setting and bes_crop_setting for active_ltcs is moved before
the nvgpu_gr_init_fs_state call from those hals.
replace gk20a_writel and gk20a_readl in modified hal function with
nvgpu_writel and nvgpu_readl.
JIRA NVGPU-1885
Change-Id: Ic0bf4a4bfa4da032f33bbe4af89031bbbdd9cd94
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072414
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Move g->ops.fecs_trace.*() HAL operations under gr operations as
g->ops.gr.fecs_trace.*()
Also rename gk20a_ctxsw_*() functions used in common code to the
format nvgpu_gr_fecs_trace_*()
Jira NVGPU-1880
Change-Id: Idf2f8fb3d7ba2832bf1837fd97b70b3cee412123
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070767
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We have 3 header files for FECS tracing support
include/nvgpu/gr/fecs_trace.h : common header
include/nvgpu/ctxsw_trace.h : header that includes both common and
os-specific functions
os/linux/ctxsw_trace.h : linux specific header
Remove the second header since it is not needed.
Move all structures that are needed in common code to
include/nvgpu/gr/fecs_trace.h
Move all function declarations that are needed in common code to
include/nvgpu/gr/fecs_trace.h
Move all linux specific declarations in os/linux/ctxsw_trace.h and
rename this file as os/linux/fecs_trace_linux.h
Also rename os/linux/ctxsw_trace.c to os/linux/fecs_trace_linux.c
Jira NVGPU-1880
Change-Id: I05cc4489c4b6a64880b7d59c02b22cd2244d5e22
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070766
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In case of FBPA we need to consider mask of active FBPAs on dGPUs.
For that we have GR unit HAL g->ops.gr.add_ctxsw_reg_pm_fbpa()
Generic support to consider active mask of unit need not be in a HAL,
move it to common code in add_ctxsw_buffer_map_entries_subunits() itself
This API now supports providing active_unit_mask as its parameter
In case we don't need to consider unit mask caller will simply pass
~U32(0U) to indicate all units are active
In case of FBPA, add a new HAL g->ops.gr.hwpm_pm.get_active_fbpa_mask()
which gets mask of active FBPAs, and pass this value to common API
add_ctxsw_buffer_map_entries_subunits()
Jira NVGPU-2895
Change-Id: I0d208ce53abcd36929c25a4d248868d6eaa5c70d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069472
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Create a new HAL unit hal.gr.hwpm_map that provides chip specific
support to common.gr.hwpm_map unit
We currently have common.gr HAL g->ops.gr.add_ctxsw_reg_perf_pma()
to handle chip specific alignment of perf_pma list
We only adjust the offset of list and remaining code is same
Hence delete above HAL, and add new HAL under hal.gr.hwpm_map
g->ops.gr.hwpm_map.align_regs_perf_pma() which returns correct
alignment if HAL is defined
Remove gr_gv100_add_ctxsw_reg_perf_pma() and
gr_gk20a_add_ctxsw_reg_perf_pma() APIs since they are no longer used
Simplify perf_pma parsing by fixing alignment with new HAL and then
directly calling add_ctxsw_buffer_map_entries()
Jira NVGPU-2895
Change-Id: I1852db846e1f5441e482028c79a3f39c5142b0c2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069471
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
