Commit Graph

7378 Commits

Author SHA1 Message Date
Seema Khowala
c0e725a576 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add nvgpu_assert.
nvgpu_assert is warning on linux but a system halt on safety
builds.
nvgpu_preempt_channel

JIRA NVGPU-3388

Change-Id: Id60d10c0d1593a6b798a037b9ec0efe6c4d20dd5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115762
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:46:56 -07:00
Seema Khowala
7ebb9d85d9 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below functions and print error messages
g->ops.tsg.force_reset
nvgpu_channel_wdt_stop

JIRA NVGPU-3388

Change-Id: Ia02b0fe040d2181a2b2dc24ec56e443f59505e99
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:46:46 -07:00
Seema Khowala
c986b60c6f gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value and nvgpu_assert for
g->ops.mm.cache.fb_flush(g)

JIRA NVGPU-3388

Change-Id: I24ccc4ae57a2827423db4eb96726a0fe5a7f04df
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115754
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:46:36 -07:00
Seema Khowala
c2b3da8e47 gpu: nvgpu: channel MISRA fix for Rule 17.7
Change gk20a_free_priv_cmdbuf from int to void type

Rename
gk20a_free_priv_cmdbuf -> nvgpu_channel_update_priv_cmd_q_and_free_entry
channel_gk20a_free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_q
free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_entry

JIRA NVGPU-3388
JIRA NVGPU-3248

Change-Id: I32bc5686a280f72c7bba4ab2d37782e29117f596
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114971
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:46:27 -07:00
Philip Elcan
13b94dd3fe gpu: nvgpu: xve: fix MISRA violations
Fix several 17.7 violations where the return values were ignored.

Fix 8.6 violation by removing unused declaration of
gp106_init_xve_ops().

Fix a 21.2 violation by renaming function __do_xve_set_speed_gp106().

JIRA NVGPU-3308

Change-Id: I480950aa42478329df33fd8c9c8c63a10dc11434
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116841
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 15:57:01 -07:00
Philip Elcan
e0fa45135a gpu: nvgpu: timers: fix MISRA 5.5 violation
MISRA Rule 5.5 requires identifiers be unique from macro names. The
struct timeout member max is renamed to max_attempts to fix the
violation.

JIRA NVGPU-3374

Change-Id: I701899e38a25b654d5f78feabbb273e21601f313
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118815
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 12:15:16 -07:00
Philip Elcan
bb1ca4fef5 gpu: nvgpu: mm: fix MISRA 17.2 violation in nvgpu_allocator
MISRA Rule 17.2 prohibits indirect recursion. nvgpu_allocator_initi()
was calling nvgpu_page_allocator_init(), which in turn was calling back
to nvgpu_allocator_init() to init a buddy allocator.  Rather than
calling back to nvgpu_allocator_init(), have nvgpu_page_allocator_init()
call nvgpu_buddy_allocator_init() directly.

JIRA NVGPU-3332

Change-Id: I1102450ae26dda355d5f5dcc3ddb195871c26c32
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114028
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 09:56:17 -07:00
Philip Elcan
bceac52f0b gpu: nvgpu: mm: fix MISRA 4.7 violations in vm.c
This fixes MISRA rule 4.7 violations in the function nvgpu_vm_map(). The
violations were caused by trying to use ERR_PTR() to return error
information. Rather than try to return errors in a pointer, just change
the API to return an int and pass the pointer the arguments.

JIRA NVGPU-3332

Change-Id: I2852a6de808d9203b8c7826e2b8211bab97ccd16
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114027
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 09:56:08 -07:00
Philip Elcan
43c6e208fd gpu: nvgpu: mm: fix MISRA violations in vm.c
Fix Rule 4.7 violation for failing to check return value.

Fix Rule 14.2 violation when using the nvgpu_list_for_each_entry_safe
macro by refactoring to use a while loop.

Fix Rule 13.5 violation for using a nvgpu_timeout_expired_msg() in a
logical expression because it can have side effects. This was fixed by
refactoring the while loop.

JIRA NVGPU-3332

Change-Id: I1454db82f766a06d3ffd549de43aad6e1b632928
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114026
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 09:55:59 -07:00
Thomas Fleury
62aa562cfb gpu: nvgpu: fix MISRA 16.x violations in nvgpu.hal.mm.mm
MISRA mandates switch clauses to end with an unconditional break
statement. Refactor switch/case in gv100_mm_get_flush_retries
function to set retries in each clause, then return result
at the end of the function.

Refactoring of the switch/case solves MISRA 16.1, 16.3 and 16.6
violations.

Jira NVGPU-3314

Change-Id: Ie051a8f2df805b63a7bef6a55fea3ae011603a0e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118887
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 18:40:52 -07:00
Thomas Fleury
93bfdd3207 gpu: nvgpu: remove unused ch->gpfifo.wrap
ch->gpfifo.wrap was set when updating ch->gpfifo.get,
but never used afterwards. Removed.

Jira NVGPU-3388

Change-Id: I198e9ba0c3716a200a8937c2488cf35e04c0166f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118184
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 18:40:21 -07:00
Vinod G
c8899a3f24 gpu: nvgpu: Fix CERT INT32-C C error in common.gr
Fix cert c violations in common.gr

CERT INT31-C: unsigned long to unsigned int without checking, it value
may result in lose or misintepreted data.
Casting the U64 data type define to U32 is causing certc violation.
To avoid this error, add define BITS_PER_BYTE_U32 as a U32 data type.

CERT EXP34-C: dereferencing null pointer "g".

Jira NVGPU-3411

Change-Id: I9eaf76bde967ee075244723c51239a7c85d09e96
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118146
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 17:47:59 -07:00
Thomas Fleury
b1dff583c8 gpu: nvgpu: fix MISRA 10.4 violation in nvgpu.common.mm.vm_area
Below MISRA 10.4 violation is reported in nvgpu.common.mm.vm_area

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/vm_area.c:234:
misra_violation: The condition clause expression of the for loop has
persistent side-effects.

Fix this by replacing with a while loop.

Jira NVGPU-3330

Change-Id: Ica6882d6c73dc0d74159f34279d8f91b7494c65c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117059
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 17:47:41 -07:00
Thomas Fleury
1fd2e43a3f gpu: nvgpu: fix MISRA 21.6 violation in nvgpu.common.mm.as
Below MISRA 21.6 violation is reported in nvgpu.common.mm.as

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/as.c:79:
misra_violation: Using function "snprintf".

Fix this by replacing snprintf with strncpy.
Add nvgpu_strnadd_u32 function to convert u32 to string
The function supports radix from 2 to 16.

Jira NVGPU-3333

Change-Id: Idee739dfdedeabb74d0d9f7d4cddd798445f0ee1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117019
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 10:50:12 -07:00
Thomas Fleury
9b2f6925ca gpu: nvgpu: fix MISRA 10.1 violation in nvgpu.common.mm.as
Below MISRA 10.1 violation is reported in nvgpu.common.mm.as

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/as.c:69:
misra_violation: The expression "({...})" of non-boolean essential
type is being interpreted as a boolean value for the operator "!".

Fix this by adding an explicit cast to bool in is_power_of_2
macro.

Jira NVGPU-3333

Change-Id: I81e0110a6cd66088a5a39c63521efa41cbd90f48
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117018
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 10:50:02 -07:00
Prateek Sethi
340cb4fcc7 gpu: nvgpu: fix barrier MISRA violations
- MISRA C-2012 Rule 21.1
Defining or undefining a reserved name.

- MISRA C-2012 Rule 21.2
"__" shall not be declared.

Jira NVGPU-3175

Change-Id: I434a35ee6cf5b06434a361e89ae092230f01055b
Signed-off-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117760
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 04:58:05 -07:00
Mahantesh Kumbar
25364895fd gpu: nvgpu: PMU RTOS fw init update
Allocate space at runtime for PMU RTOS fw struct, this helps
to reduce the size of nvgpu_pmu struct when LS_PMU support
is not required.

Allocation happens at pmu early init stage & will deinit at
remove_support stage.

JIRA NVGPU-1972

Change-Id: I1452b085f8d3a76e12186f788c2d999a8b4b202d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111072
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 04:56:34 -07:00
Mahantesh Kumbar
118381411a gpu: nvgpu: replace gk20a_from_pmu() with pmu->g
removed gk20a_from_pmu() & used pmu->g to remove
circular dependency within PMU units.

JIRA NVGPU-1972

Change-Id: I5fd1eae30a81cea5a50dd04c1fdfdb7fd4d0e1b8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111071
GVS: Gerrit_Virtual_Submit
Reviewed-by: Abdul Salam <absalam@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 04:56:18 -07:00
Sagar Kamble
6c22dc7ea4 gpu: nvgpu: use make flag NV_BUILD_CONFIGURATION_IS_SAFETY
Update the shared config file to use the safety build flag NV_BUILD_
CONFIGURATION_IS_SAFETY instead of NVGPU_REDUCED. With these changes
posix userspace and tests will be built in two configs based on this
flag.

JIRA NVGPU-3062

Change-Id: Iaf34dd1a8f66f2dd3f351365c369ed46a484a257
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116402
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 01:18:38 -07:00
Shashank Singh
e0a98ff45a gpu: nvgpu: fix cert-c violation for irq var
irq number read from dt is unsigned type and it is stored in signed
variable(CERT-INIT31-C). So, make irq number as unsigned.

Jira NVGPU-3438

Change-Id: I2afd8686bf2f5405caec62cf94418e4bd009be07
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115393
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 01:18:04 -07:00
Sagar Kamble
24759e41e8 gpu: nvgpu: update the safety build config options setup
Due to dependency on nvrm ioctl whitelisting, switch to user mode
submit and rmserver, we can't disable virt support, USERD, LS PMU
and debugger functionalities yet. Update the config options setup
accordingly. With these changes safety build will have same code
compiled as normal build.

JIRA NVGPU-3062

Change-Id: I99d1bb1c7bb8c244cab9d04304aa760c09e7dd1e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113483
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 01:17:14 -07:00
Sagar Kamble
94a8f3ce28 gpu: nvgpu: consolidate the makefile config setup
Since the safety build config options for qnx build are to be adhered
by posix userspace build as well, let us create shared configs file.
Add these config options to unit tests makefile as we would need to
control the tests based on these options and tests also access the
common nvgpu functions.

JIRA NVGPU-3062

Change-Id: I292eca9ac3160eed93485afddf7c30e993e0461c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116401
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 01:17:04 -07:00
ajesh
84393def8b gpu: nvgpu: fix MISRA violations in types unit
MISRA rule 10.1 requires that the operands shall not be of an
inappropriate essential type.
MISRA rule 10.3 requires that the values of an expression shall not be
assigned to an object with narrower essential type or of a different
essential type category.
MISRA rule 10.4 requires both the operands of an operator in which the
usual arithmetic conversions are performed to have the same essential
type category.
MISRA rule 10.8 requires that the value of a composite expression shall
not be cast to a different essential type category or a wider essential
type.
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore.
Fix violations of rules 10.1, 10.3, 10.4, 10.8 and 21.2 in types unit.

Jira NVGPU-3300

Change-Id: I3be4218ec8785aa9a116765233273097993baf0d
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117921
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 23:09:31 -07:00
Thomas Fleury
c7b6a7d235 gpu: nvgpu: fix MISRA 10.4 violation in nvgpu.common.mm.nvgpu_sgt
Below MISRA 10.4 violation is reported in nvgpu.common.mm.nvgpu_sgt

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/nvgpu_sgt.c:131:
misra_violation: Essential type of the left hand operand
"mem->mem_flags & 8ULL" (unsigned) is not the same as that of the
right operand "0ULL"(signed).

Fix this by changing right hand operand to 0U.

Jira NVGPU-3334

Change-Id: Ib28bfce363a807ba9f8fa9df9cbb02c636a74898
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117034
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 23:08:49 -07:00
Shih-hsin Li
6f9ef25c12 gpu: nvgpu: fix synchronization in nvgpu_vm_map
The mapping early returned from nvgpu_vm_map might already
be unmapped during channel clean up. Increase refcount of
an already mapped buffer inside the scope of update_gmmu_lock
mutex to avoid this race.

Bug 200494150

Change-Id: I66d9272e42c40cd3aae7ba3bb8106ec37691bf8e
Signed-off-by: Shih-hsin Li <seasonl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114163
(cherry picked from commit af95d14bb0)
Reviewed-on: https://git-master.nvidia.com/r/2116749
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 21:56:07 -07:00
Thomas Fleury
6e9fdd57eb gpu: nvgpu: fix MISRA 21.x violations in utils
Below MISRA 21.1 violation is reported in nvgpu.common.utils

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/utils.h:56:
misra_violation: The NVGPU_GET_IP shall not be defined or undefined.

Below MISRA 21.2 violation is reported in nvgpu.common.utils

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/utils.h:56:
misra_violation: The NVGPU_GET_IP shall not be declared.

Fix this by renaming _NVGPU_GET_IP_ to NVGPU_GET_IP

Jira NVGPU-3327

Change-Id: Ied94d8c8d80c2b26df8e742c18255c3dc657d59a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116696
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 17:16:23 -07:00
Thomas Fleury
076555efb8 gpu: nvgpu: fix MISRA 8.6 violation in nvgpu.common.mm.mm
Below MISRA 8.6 violation is reported in nvgpu.common.mm.mm

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/mm.h:184:
declaration_with_no_definition: "nvgpu_init_mm_setup_hw" is
declared but never defined.

Fix this by removing nvgpu_init_mm_setup_hw declaration.

Jira NVGPU-3331

Change-Id: I78352c13e6c85cc67a261f62fe33eff64b5f6f5f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116707
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:12:29 -07:00
Thomas Fleury
310471bf77 gpu: nvgpu: fix MISRA 17.7 violation in nvgpu.common.mm.mm
Below MISRA 17.7 violation is reported in nvgpu.common.mm.mm

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/mm.c:645:
misra_c_2012_rule_17_7: The return value of a non-void function
"*g->ops.bus.bar1_bind" is unused.

Fix this by checking return value and returning an error in
case of failure.

Jira NVGPU-3331

Change-Id: Iab43d630163af782d3cc87989a64062516a4cd92
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116706
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:12:19 -07:00
Thomas Fleury
4cd0e88065 gpu: nvgpu: fix MISRA 10.1 violation in nvgpu.common.mm.mm
Below MISRA 10.1 violation is reported in nvgpu.common.mm.mm

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/mm.c:378:
misra_violation: The expression "g->mm.vidmem.size" of non-boolean
essential type is being interpreted as a boolean value for the
operator "&&".

Fix this by explicitly checking g->mm.vidmem.size > 0U.

Jira NVGPU-3331

Change-Id: I1bb54736593801c7cb684973f411459dae6f008d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116705
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:12:09 -07:00
Thomas Fleury
89155d0ed1 gpu: nvgpu: fix MISRA 21.2 violation in rbtree
Below MISRA 21.2 violation is reported in nvgpu.common.rbtree

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/rbtree.c:188:
misra_violation: _delete_fixup shall not be declared.

Fix this by renaming to delete_fixup.

Jira NVGPU-3305

Change-Id: I09d8da721cc87d3bb9e4a23d00a31a82a8759365
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116681
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:11:59 -07:00
Thomas Fleury
d38723d618 gpu: nvgpu: fix MISRA 15.7 violation in rbtree
Below MISRA 15.7 violation is reported in nvgpu.common.rbtree

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/rbtree.c:200:
misra_violation: No non-empty terminating "else" statement.

Fix this by re-factoring for loop.
Also re-arranged code to avoid lines over 80 chars.

Jira NVGPU-3305

Change-Id: If7586f1ac9bc411751c92b94969123788a273cf8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116680
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:11:49 -07:00
Seema Khowala
f453f66fc4 gpu: nvgpu: fifo MISRA fix for Rule 15.7
Add terminating else statement

JIRA NVGPU-3383

Change-Id: I3ceb15de502d3927452713765a83076837904624
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115899
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:11:13 -07:00
Seema Khowala
50d4421dc2 gpu: nvgpu: fifo MISRA fix for Rule 10.3
JIRA NVGPU-3383

Change-Id: Ic1b30cd4b8c5dba0ea75ff0de316d0d5dcc99ae4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116730
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:10:57 -07:00
Seema Khowala
7054643749 gpu: nvgpu: fifo MISRA fix for Rule 10.3
JIRA NVGPU-3383

Change-Id: Ice279ee436b1f54c3aa2279f1129aa6de11f1315
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115860
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:10:47 -07:00
Seema Khowala
42c2ea552d gpu: nvgpu: fifo MISRA fix for Rule 10.1
JIRA NVGPU-3383

Change-Id: I18ab3ebd4728ff798c0cc47f6cb84d1dda225b53
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116729
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:10:37 -07:00
Seema Khowala
8d34edfee0 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add err message
ch_data->unbind_single_channel

JIRA NVGPU-3388

Change-Id: Iac979c464600507b3fcfa907d9babc8bdc232338
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115832
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:10:27 -07:00
Alex Waterman
6efe02f776 gpu: nvgpu: Add YAML arch to linux-nvgpu
Add the YAML arch to the linux-nvgpu repo so that the arch and source
code can be kept entirely in sync.

When the YAML was in a separate repo it was too difficult to keep things
in sync. Based on this work the next steps are:

  1. Gate compilation on no sources issues (missing or orphan source
     files.
  2. Perhaps use the arch to generate the Makefile.sources files.

JIRA NVGPU-3074
JIRA NVGPU-3075
Bug 2587555

Change-Id: Ic62be3e5e7ea1fb61ea50a2d611f905fa574988f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113154
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 10:47:44 -07:00
ajesh
6d83f6bca8 gpu: nvgpu: fix MISRA violation in posix cond unit
MISRA 20.7 rule requires macro paramaters to be wrapped in
parantheses when the parameter expands into an expression.
Fix the violation of MISRA rule 20.7 in posix cond unit.

Jira NVGPU-3139

Change-Id: If1833677b5c6e3d9f3f20ff81fdc4c6dd52451b9
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112615
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-12 22:55:24 -07:00
Rajesh Devaraj
8090e2d5eb gpu: nvgpu: report PFIFO CTXSW timeout error
During code review, it has been found that PFIFO CTXSW timeout error related
callback has been removed while restructuring PFIFO unit. Hence, we are
introducing the callback to report PFIFO CTXSW timeout error to 3LSS.

Jira NVGPU-3439

Change-Id: I3c4b9a25215fb7692470ac43f0ea8fc21720c376
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115186
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-12 21:45:20 -07:00
Vinod G
5c60645cfa gpu: nvgpu: gr_priv header include cleanup
Add more apis in gr_utils for accessing variables within gr struct.
This helps to avoid including gr_priv.h outside gr files and
derefencing gr struct.

Jira NVGPU-3218

Change-Id: I6f24cc302f10aa1da14a981d80c400a027c9a115
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115930
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 20:15:36 -07:00
Vinod G
e615e8f0ff gpu: nvgpu: gr/init MISRA fixes for Rule 10.3
Fix MISRA violations for Rule 10.3 in gr.init unit
Implicit conversion from essential type "unsigned 64-bit int"
to different or narrower essential type "unsigned 32-bit int"

Jira NVGPU-3389

Change-Id: I00bc876f271242a513371477c781e78b2ee42b6a
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116733
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 19:05:25 -07:00
Philip Elcan
e332b6023c gpu: nvgpu: vbios: fix MISRA 11.3 violations
MISRA Rule 11.3 prohibits casting between pointer types. This patch
eliminates the 11.3 violations by doing the pointer arithmetic before
the cast.

JIRA NVGPU-3317

Change-Id: I624301041f3b91ddc71b30ba19f04ab492f40794
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114880
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 16:46:20 -07:00
Philip Elcan
4d104a432c gpu: nvgpu: vbios: fix MISRA 5.7 violations
MISRA 5.7 requires that all tag names be unique. Rename local variables
in functions where the local variable was named the same as the struct
type.

JIRA NVGPU-3317

Change-Id: I6604e386ac043ff33369a3ab676a6f59bfcc30c4
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114879
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 16:46:11 -07:00
Philip Elcan
173f23754d gpu:nvgpu: vbios: fix MISRA 21.2 violations
MISRA Rule 21.2 prohibits naming identifiers beginning with double
underscore. Rename __nvgpu_bios_readdbyte to nvgpu_bios_readbyte_impl to
comply.

JIRA NVGPU-3317

Change-Id: Ic5eaf0a629db8669c52cc6c8a2218499ceb0d8e4
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114878
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 16:46:01 -07:00
Nicolas Benech
8f1e12f4bb gpu: nvgpu: unit: add required_tests for rbtree
rbtree related tests were missing from required_tests.json.
This patch adds them.

JIRA NVGPU-3247

Change-Id: I5452785fcc31b9b2c32780b1cf70bdb94d185421
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114023
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 14:24:57 -07:00
Seshendra Gadagottu
76aac6b183 gpu: nvgpu: MISRA 21.6 fixes in hal netlist
Use strcpy/strcat instead of sprintf to fix MISRA 21.6
violations.

JIRA NVGPU-3420

Change-Id: I70314bc9b407370961bd46434bb355ebb8d1df7d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115925
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 13:21:25 -07:00
Seshendra Gadagottu
62a7fde536 gpu: nvgpu: MISRA 16.x fixes for hal netlist
Fixes issues with switch formatting and missing break statements
in hal netlist driver.

JIRA NVGPU-3420

Change-Id: Iae59ac80d6f780cfc6144977f14e85e15dc53ace
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114896
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 13:20:31 -07:00
ajesh
de9e914670 gpu: nvgpu: fix MISRA violations in atomic unit
MISRA rule 20.7 requires macro paramaters to be wrapped in parantheses
when the parameter expands into an expression.  Fix violations of rule
20.7 in atomic unit.
MISRA rule 10.3 prohibits the assignment of the value of an expression
to an object with narrower essential type or of a different essential
type category.  Fix violations of rule 10.3 in atomic unit.

Jira NVGPU-3296

Change-Id: I087a6d15c5d03885aea29f22853e5bbde7880014
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116306
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 11:43:02 -07:00
Seema Khowala
defc27ac9b gpu: nvgpu: cg fix MISRA violations
Fix Rule 10.1

Rename gk20a_readl and gk20a_writel
Moved ELCG_* and BLCG_* defines from gk20a.h to cg.h
Cleaned up checkpatch errors

JIRA NVGPU-3424

Change-Id: I8d7de11dd7beb22c0fe44ff770af3b2609434385
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115908
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 11:42:52 -07:00
Seshendra Gadagottu
9651138633 gpu: nvgpu: Fix MISRA 5.5 error in common netlist
Avoid use of local variable "max" by renaming it to "max_netlist_num"

JIRA NVGPU-3420

Change-Id: Ie0a49aa6c24617d22efe401ae883d0a9c8b1dff0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116066
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
2019-05-10 10:54:04 -07:00