As a part of safety check, golden context is created twice
(back to back) and two golden context images are compared.
These two images should be identical for safety check.
Currently there is one hw deviation happening because of stats
counter idle clock increments. To avoid this, stats counter
clocks enable is disabled. To have a valid golden context(
avoid mismatch between fe and mpc), original stats counter
bundle is programmed through mme shadow register.
Before first golden context save, golden image is saved in
a local copy. Same copy is restored back after first golden
save. Second golden context save is done with this local copy
and two golden contexts are compared.
JIRA NVGPU-3558
Change-Id: I5b5a1c5ff177e866a91cfc23618b118c157c8e95
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2167213
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Added following gr init related gv11b hal for safety golden context
creation:
void gv11b_gr_init_restore_stats_counter_bundle_data(struct gk20a *g,
struct netlist_av_list *sw_bundle_init);
int gv11b_gr_init_load_sw_bundle_init(struct gk20a *g,
struct netlist_av_list *sw_bundle_init);
gv11b_gr_init_restore_stats_counter_bundle_data implements functionality
required to re-store stats bundle data, to avoid fe and mme mismatch.
gv11b_gr_init_load_sw_bundle_init implements functionality required for
disable stats idle clock counter to avoid mismatches
with two golden context saves.
JIRA NVGPU-3558
Change-Id: I73886770dac30934cbd3989b19ba87553286453d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2167211
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Added helper function to compare two golden context images:
bool nvgpu_gr_global_ctx_compare_golden_images(struct gk20a *g,
bool is_sysmem,
struct nvgpu_gr_global_ctx_local_golden_image *local_golden_image1,
struct nvgpu_gr_global_ctx_local_golden_image *local_golden_image2,
size_t size);
In case of sysmmem, direct mem comparison can be used and for vidmem.
only word by word comparison can be done.
Since this code is used only for safety, all implementation is under
NV_BUILD_CONFIGURATION_IS_SAFETY flag.
JIRA NVGPU-3558
Change-Id: Ie3d0ac19e561b19d44e90a9d6188eaade0cdec44
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2167209
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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INT31-C requires that integer conversions do not result in lost or
misinterpreted data.
Fix violations of INT31-C in utils unit. Add safe sub function for
u8 variables to fix the violation.
Jira NVGPU-3609
Change-Id: Ife51f5cc00c7127dd87d5d7b1b3c19ecf7bbfa4d
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2169974
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Rule 11.3 forbids pointer cast between two different object types.
Rule 13.5 doesn't allow right hand operand of a logical operator to have
persistent side effects.
This patch fixes mentioned rules in nvgpu.common.mm.
Jira NVGPU-3864
Change-Id: I08b7fb4d3fb623f14f8760a50648b39b3e53b233
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168522
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Add CONFIG_NVGPU_RECOVERY in order to conditionally compile
recovery code. This code will be removed from safety build
when sw quiesce state is implemented, and negative tests are
disabled or modified such that they do not expect recovery
to happen.
Added static inline functions for recovery handlers, when
CONFIG_NVGPU_RECOVERY is not defined. These inline functions
can later be wired to the sw quiesce functions.
Also moved gv11b recovery code to non-fusa, as it will ultimately
be removed from safety build.
Jira NVGPU-3871
Change-Id: Ia705b059fab6120899c7e15082f2a0f51ff51dc9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2166074
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Add nvgpu_utf_falcon_set_dmactl() function in falcon UTF
to set the falcon dmactl register with desired value
required for pmu reset test
Also, update the register size for falcon from 0x300 to 0x400
for including pmu reset register.
Rename userspace/units/facon/falcon folder to
userspace/units/facon/falcon_tests
JIRA NVGPU-2159
Change-Id: I0b22cff4699af6947e87019751aa85508dfdb185
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155124
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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There was a header file circular dependency that was preventing
including some files. For example, for utils.h to include safe_ops.h
would include bug.h which included log.h which included bitops.h which
included utils.h. To break this loop, the macro nvgpu_do_assert_print()
into a function in a new file assert.c. With this change, log.h is no
longer required in bug.h.
This change also required adding a few includes in C files that were
picking up definitions through the chain above.
JIRA NVGPU-3868
Change-Id: Icf95677bb36e4aa034cba25594cf71f2d028c289
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168528
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nvgpu_rc_pbdma_fault just checks for the id and id_type from struct
nvgpu_pbdma_status_info. These contain invalid values during chsw_load
and chsw_switch. This patch corrects the above bug by checking for the
chsw status and then loading the values for id and type.
The current code reads the pbdma_status info after clearing the
interrupt. Other interrupts can cause enough delay between clearing the
interrupt and pbdma switching the channel leading to invalid channel/tsg
ID. Correct that by reading the pbdma_status info register before
clearing of the pbdma interrupt to correctly read the context
information before the pbdma can switch out the context.
Bug 2648298
Change-Id: Ic2f0682526e00d14ad58f0411472f34388183f2b
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165047
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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INT30-C requires that unsigned integer operations do not wrap.
INT31-C requires checking that data isn't misinterpreted after casting.
INT32-C requires that signed operations do not overflow.
Jira NVGPU-3882
Change-Id: I6b4c1769ec85919f8ec2aa183cba3b7c0ffa1e97
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2166124
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If CONFIG_NVGPU_CE is disabled, nvgpu right now does not even reset
the CE engines or initialize prod values.
This ultimately needs to be fixed by adding appropriate initialization
for CE engines even if CONFIG_NVGPU_CE is disabled.
For now, add the code to at least reset CE engines if CONFIG_NVGPU_CE
is disabled
Bug 2526212
Change-Id: Id0a6fbfe44ef7af62715bcee65bef056359f1c19
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165861
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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INT30-C requires that unsigned integer operations do not wrap.
INT32-C requires that operations on signed integers do not result in
overflow.
FIO47-C requires use of valid format strings.
Fix CERT-C violations of these types in nvgpu.common.ecc.
JIRA NVGPU-3868
Change-Id: I72e15ae2e6d6a4db4e7e9971e13e143cf58b6dc4
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2164602
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Rule 2.2 doesn't allow unused variable assignments. The reason is
presence of unused variable assignments may indicate error in program's
logic.
Rule 21.x doesn't allow reserved identifier or macro names starting with
'_' to be reused or defined.
Jira NVGPU-3864
Change-Id: I8ee31c0ee522cd4de00b317b0b4463868ac958ef
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2163723
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Reduce code complexity of following functions in gr.falcon unit
nvgpu_gr_falcon_load_secure_ctxsw_ucode(complexity : 14 to 5)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create three sub functions from nvgpu_gr_falcon_load_secure_ctxsw_ucode function
Sub functions to do bootstrap during recovery and cold boot
Generalize sec2 and ls_pmu bootstrap to a single function.
gr_falcon_sec2_or_ls_pmu_bootstrap(with complexity : 4)
gr_falcon_recovery_bootstrap(with complexity : 4)
gr_falcon_coldboot_bootstrap(with complexity : 5)
and reduce nvgpu_gr_falcon_load_secure_ctxsw_ucode complexity to 5
Jira NVGPU-3662
Change-Id: I290580572d6c6dac6aa9bbd93b06c84ec3b93637
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165255
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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With hal units sources now separated out largely, let us update the
yaml to create fusa/non-fusa units for various hals. This is prer-
equisite to gating safety sources compilation based on YAML.
JIRA NVGPU-3860
Change-Id: Ifcdb0a1484279fe4abbe03b4de1b45e9b8ef6239
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2164333
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
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Reduce code complexity of following functions in gr.falcon unit
gm20b_gr_falcon_ctx_wait_ucode(complexity : 21 to 9)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create two sub functions from gm20b_gr_falcon_ctx_wait_ucode function
Sub functions to check the opcode failure and opcode success.
gm20b_gr_falcon_check_ctx_opcode_success(with complexity : 7)
gm20b_gr_falcon_check_ctx_opcode_failure(with complexity : 7)
and reduce gm20b_gr_falcon_ctx_wait_ucode complexity to 9
Jira NVGPU-3662
Change-Id: I445dab4e4149af2cc88d19a5b18b105077dece5f
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165217
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Reduce code complexity of following functions in gr.falcon unit
gv11b_gr_falcon_handle_fecs_ecc_error(complexity : 12 to 8)
Create sub functions by moving the control statement codes from
the function which has high complexity above 10.
Create one sub functions from gv11b_gr_falcon_handle_fecs_ecc_error function
One sub function to set the fecs_ecc_error status locally.
gr_falcon_set_fecs_ecc_error_status(with complexity : 5) and
reduce gv11b_gr_falcon_handle_fecs_ecc_error complexity to 8
Jira NVGPU-3662
Change-Id: I9ce3cd7b6b4fb453445457ba5f19faf7086b5fc6
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165190
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Rule 8.6 requires each identifier with external linkage to have exactly
one external definitions.
Rule 10.x necessitates operands to have essential type; left and right
operands should be of same width and type.
Rule 17.7 requires function return value to be checked for error
information.
This patch fixes above mentioned errors in nvgpu.hal.mc.
Jira NVGPU-3855
Change-Id: I5440392de5d55dc98ed2002273af8a44a596cd3a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2162145
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Moved non-secure gr falcon boot related code to non-functional safety file.
Also added HAL initialization related to these functions under
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT flag.
JIRA NVGPU-3741
Change-Id: I72fb92c04dc6e76c338e9a0e0cd86b12109ce284
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158936
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Compile-out non-secure gr falcon boot related code for safety build by
adding non-secure gr falcon related code under following flag:
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
Added nvgpu_gr_falcon_load_ctxsw_ucode and related functions under
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT flag and enabled this flag only
for non-safety builds.
JIRA NVGPU-3741
Change-Id: I817d8a7be6a675eee514faf7bb93f1382c6da5ce
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158935
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Eliminate Advisory Rule 8.11 violations in gmmu_gk20a.h by
removing extern declarations of gk20a_mm_levels_64k[] and
gk20a_mm_levels_128k[].
Advisory Rule 8.11 states when an array with external linkage
is declared, its size should be explicitly specified.
Jira NVGPU-3178
Change-Id: I452a571e0561edbd9f8cd856775563587c201d40
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2162273
GVS: Gerrit_Virtual_Submit
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Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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