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2907 Commits

Author SHA1 Message Date
ajesh
9846573d64 gpu: nvgpu: handle the return values from OS APIs 
Handle the return values from standard OS library calls.

Jira NVGPU-4987

Change-Id: I41bf0113097d6bfa344ed58f68448abc9cc7f367
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299985
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 2020-12-15 14:13:28 -06:00
Terje Bergstrom
6d4e4f633f gpu: nvgpu: posix: Use non-atomic types when appropriate 
Atomic functions return non-atomic types. Change the type definitions
and casts to follow that.

Change-Id: If6fbfa5f75810151fe4765874f3dd610b85a39d1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318384
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
da8ee8d615 gpu: nvgpu: add therm_max_fpdiv_factor gops.therm 
Use therm_max_fpdiv_factor gops.therm for nvgpu-next to get the maximum
fp_div_factor.

Jira NVGPU-4860

Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Change-Id: If0e9b82f5b61289e226ceeff386fc88763af66e2
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313336
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 2020-12-15 14:13:28 -06:00
Abdul Salam
4f5bd9e633 gpu: nvgpu: Implement clk_good and pll_lock check 
Add clk_good and pll_lock check as a part of fmon polling.
This will poll for any clock related faults at FTTI interval.
Add new function to poll for vbios init completion.

NVGPU-4967
Bug 2849506
Bug 200564937

Change-Id: I5bc885329981e07376824e148edabe9be4120e1c
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2305782
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 2020-12-15 14:13:28 -06:00
Seema Khowala
21e2214c3d gpu: nvgpu: support nvgpu-next intr config 
JIRA NVGPU-4864

Change-Id: I2fb5be3270c73ea891021161f539a7f731e05f63
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2314372
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 2020-12-15 14:13:28 -06:00
rmylavarapu
a5b3170c6f gpu: nvgpu: Refactor allocator lite unit 
- Changed the names of structs as per private/public
  naming convention.
- Renamed allocator.c file

NVGPU-4487

Change-Id: I42ec5730f1cb0029a6bb6e6ddff151bd08d6bbd8
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316945
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
f43d5df83a gpu: nvgpu: build dGPU in safety 
Enable build flags for dGPU in safety, when
NVGPU_FORCE_DGPU_SAFETY_PROFILE is set.

Use libnvgpu-dgpu_safe.exports for dGPU safety build.

Add build flags for tu104 HAL initialization (to solve
undefined symbols in safety build).

Temporarily add non-fusa files needed to build dGPU in safety.
related functions will have to move to fusa files.

Jira NVGPU-4611

Change-Id: I41db0c039c7f15d9191cdb811b4906e779d5cc88
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310276
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
872b3946dd gpu: nvgpu: add nvgpu-next fb gops 
JIRA NVGPU-5222

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I3004fcfd9cf17b81c6d218954da140982a76c6fd
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316212
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 2020-12-15 14:13:28 -06:00
rmylavarapu
f5acc98db3 gpu: nvgpu: Refactor Super surface lite unit 
- Changed the names of structs as per private/public
  naming convention.
- Removed unwanted code in struct super_surface.

NVGPU-4486

Change-Id: I5834c2296ccbe1545bca6a608ad88817a9104fb8
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313989
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
682966ef4c gpu: nvgpu: posix: add some nvhost primitives 
Add the following primitives to resolve build issues
when enabling dGPU in safety build:
- nvgpu_nvhost_syncpt_is_expired_ext
- nvgpu_nvhost_syncpt_is_valid_pt_ext
- nvgpu_nvhost_syncpt_incr_max_ext
- nvgpu_nvhost_intr_register_notifier
- nvgpu_nvhost_get_syncpt_host_managed
- nvgpu_nvhost_syncpt_wait_timeout_ext
- nvgpu_nvhost_syncpt_read_ext_check

Jira NVGPU-4661

Change-Id: Iabd7b2a9addc96ed48f42aedb5640a17c6dce62c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2314207
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
8ec4395e82 gpu: nvgpu: build flag for deterministic channel 
Add CONFIG_NVGPU_DETERMINISTIC_CHANNELS and fix
preprocessor #ifdefs to allow compiling kernel mode
submit without deterministic feature enabled.

Jira NVGPU-4661

Change-Id: I4aa678715824e8981d39bd8db0c5ae61ef3a675c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310325
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 2020-12-15 14:13:28 -06:00
Seeta Rama Raju
5ce7d5acff gpu: nvgpu: Add fault injection variable for clock UT 
Bug 2861451

Change-Id: Ie51c1524c47934e44cde06515f5daccd8e1e7dd9
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
(cherry picked from commit d57a51ba6db7b6c2df28d1770727506214b85e08)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310971
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
7aa9e90bfc gpu: nvgpu: update gops.cg 
Update gops.cg to include following runlist level cg ops:
- blcg_runlist_load_gating_prod
- slcg_runlist_load_gating_prod

Jira NVGPU-5048

Change-Id: Ia2a3f887d5c2fd6f1dd35d606afd19d117468c2c
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300448
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
59c6947fc6 gpu: nvgpu: add CONFIG_NVGPU_TEGRA_FUSE 
Encapsulate the tegra fuse functionality under the config flag
CONFIG_NVGPU_TEGRA_FUSE.

Bug 2834141

Change-Id: I54c9e82360e8a24008ea14eb55af80f81d325cdc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306432
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
3748be5792 gpu: nvgpu: move timer functions from soc files 
Move following timer functions from soc header and c file to timer
header and c file:
1. nvgpu_delay_usecs
2. nvgpu_us_counter
3. nvgpu_get_cycles

Bug 2834141

Change-Id: I04cf7229a0d35c90a320bbe64e80912b08cccefb
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306431
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
00eec69b3f gpu: nvgpu: add hal to get_ctx_buffer_offsets 
Currently, gr_gk20a_get_ctx_buffer_offsets is defined as a function.
However, this function is used in the common code. So, add new GR hal
to get_ctx_buffer_offsets.

Jira NVGPU-5047

Change-Id: I0cec6ff19194fa726722e6af3a2f11a188dc9087
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310352
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 2020-12-15 14:13:28 -06:00
Seema Khowala
007ecfb5bc gpu: nvgpu: support upto four stall interrupt lines 
Add two new variables in nvgpu_mc struct to support
upto four stall interrupt lines.

Variables:-

Total number of stall interrupt lines:
u32 irq_stall_count

Array to store irq_stall interrupt number for upto 4
stall irq lines:
u32 irq_stall_lines[4]

JIRA NVGPU-4864

Change-Id: I9b43fc20c78dbcaf97fe8e685bb77963f06d3f99
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310377
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 2020-12-15 14:13:28 -06:00
vinodg
4aff9bcd4e gpu: nvgpu: fix for load imbalance across cta subpartitions 
CTA_SUBPARTITION_SKEW load balancing is broken across
subpartitions. SW WAR to disable the CTA_SUBPARTITION_SKEW.

Jira NVGPU-5132
Bug 200593339

Signed-off-by: vinodg <vinodg@nvidia.com>
Change-Id: I3faae882a94fc6262cc287df44994cc04b4fd5d6
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308905
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 2020-12-15 14:13:28 -06:00
rmylavarapu
147564cbd5 gpu: nvgpu: NVGPU migration to support latest ucode 
Changes:
- Send down BOARDOBJGRP classId to the PMU. Assign each
  BOARDOBJ the classId of its parent group which is set
  to zero in current implementation. Changed in NVGPU to send
  board obj grp classid to PMU.
- Disable IPC VMIN support as pmu-tu10a profile doesn't support.
- Change in clk vf point enumeration types.
- Change in pstate type values.
- Updated ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info
  NVGPU-PMU interface struct with b_ver_expected_is_mask to send
  whether the expected version is single value or should be
  interpreted as a bit mask with bits corresponding to
  expected versions set.

NVBUG-200593676
NVGPU-5066

Change-Id: I17b172d88f8b74fbf78044caf7f64cd8811f9fb7
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
dc32307c13 gpu: nvgpu: Rename therm public struct 
Renamed therm public struct to match with the other
units.

NVGPU-4449

Change-Id: I675ce43b136139420b8cc1eecdc395d9165d9f30
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307090
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 2020-12-15 14:13:28 -06:00
Petlozu Pravareshwar
6859c9c5a6 gpu: nvgpu: Add nvgpu macro for a pthread API 
Add nvgpu macro for pthread API pthread_cleanup_pop(0). The argument
zero would mean that the thread cancellation cleanup handler which is
pushed onto the thread's stack using pthread_cleanup_push() will not
get executed.

JIRA NVGPU-5110

Change-Id: I89a45ccccd8709685f487513bf99d622a82ed891
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
9aa669797d gpu: nvgpu: add pbdma gops for nvgpu_next 
Add pbdma gops for nvgpu-next.

Jira NVGPU-4979

Change-Id: If04f5c09cd4a13b0f536a15dbe2b4bd9eb24107a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
2e4fb38870 gpu: nvgpu: add eng_config hal for nvgpu_next 
Add gr.eng_config hal for nvgpu_next.

Jira NVGPU-5049

Change-Id: Ieb342cb0416f965a3f80e3a6e3f0f43a853485ff
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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Vedashree Vidwans
5fa0d7f994 gpu: nvgpu: add bundle programming for nvgpu_next 
Update bundle programming for nvgpu_next.

JIRA NVGPU-5004

Change-Id: I1c452a9e78cd018de86fb57de10291c4411e7d89
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
e424e4791a gpu: nvgpu: perf: Refactor Perf unit 
-Renamed and moved nvgpu_pmu_perf struct from public
to unit specific
-Renamed all functions as per public/private format

NVGPU-5029

Change-Id: If3f479bb1443850a5c8a8714cd1c9da346cb566a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300609
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
14f268563a gpu: nvgpu: add gr.zbc hal for nvgpu_next 
Add gr.zbc hal for nvgpu_next

Jira NVGPU-5084

Change-Id: I678dac83ea67818e1b657b22840f3f4a04584ba8
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Seema Khowala
ffe44aab13 gpu: nvgpu: mc: add hooks for nvgpu-next 
JIRA NVGPU-4864

Change-Id: I692d041d005b0d62813df5f16d21c8ae92a2c3e0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2293201
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
sagar
88e27271eb gpu: nvgpu: fix static analysis issues 
coverity tool is not detecting the lenght validation done at caller.
moved length checks to appropriate functions.

used macro instead of hardcoded values.

Jira NVGPU-4780

Change-Id: Ie6b420a6e625eed5374715fd7ca5c87d3ba3d015
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2302335
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Sagar Kamble
630eaa46cb gpu: nvgpu: update the config options & makefile 
Added dependency between the Kconfig options as follows where
'->' indicates 'depends on' relation:

SUPPORT_CDE -> COMPRESSION -> DMABUF_HAS_DRVDATA
DGPU -> GK20A_PCI

Defined Kconfig option for VPR and for DGPU that is dependent GK20A_PCI
as well. DGPU related sources are now compiled under config flag DGPU.
Also update conditional compilation of the driver paths w.r.t DGPU,
VPR and COMPRESSION flags.

Bug 2834141

Change-Id: Ia0a39d6d4cf8b36e7f955b7355a5ab41783f821c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299627
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Abdul Salam
29d4831780 gpu: nvgpu: Segregate volt unit members based on their accessibility 
Currently all unit specific private members are inside ucode_volt_inf.h.
This patch moves the members specific to pmuif to ucode_volt_inf.h and
local to volt.h.
Append all unit specific local functions with volt/nvgpu.
Move volt specific rpc handler from g->pmu to g->pmu->volt.

NVGPU-4492

Change-Id: I626e002b3876c6c5330dec4396b7661b986c6119
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299555
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
ed4eb79ac1 gpu: nvgpu: SWUD Lite updates 
Updated minor typo errors found during code inspection

JIRA NVGPU-4785
JIRA NVGPU-4789

Change-Id: I37384a852e9a2783e3033a6f12c21eafc00e5bcf
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300560
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
43324f7b1b gpu: nvgpu: Reconcile sim escape paths between RM and nvgpu 
SIM models are getting updated to have same escape read path
for RM and nvgpu. Updated nvgpu driver code to have same escape
read mechanism as RM.

This is required for igpu to pass on NET21.

Bug 2539889

Change-Id: I5d37ceb799cafb7fc7dec611fda5f5caac7d7f17
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2130414
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Lakshmanan M <lm@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Rajesh Devaraj
50d71f7c56 gpu: nvgpu: report fecs ctxsw init error 
This patch adds callback to report fecs ctxsw init error to 3LSS.
It also moves the related wrapper function to nvgpu_err header
file and adds doxygen documentation.

JIRA NVGPU-5042

Change-Id: I2a051cf19c2940859169799a4dd51adf8870eff4
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300003
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Sagar Kamble
18f9d05aae gpu: nvgpu: spec_barrier & DMA_ERROR_CODE update 
These macros are not defined in future kernel.

Bug 2834141

Change-Id: Ib2ee419b66f4d949fd538dfbb04b8cffa73c1e44
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299626
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Scott Long
4fd8df5ca0 gpu: nvgpu: fix misra 10.5 violations 
MISRA Advisory Rule 10.5 states that the value of an expression should
not be cast to an inappropriate essential type.

This change eliminates such a violation in the posix implementation
of nvgpu_thread_cleanup_pop().

Jira NVGPU-3178

Change-Id: I2ad363b4d60c321fa20b23c167d783bebaceb7d3
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298986
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Sagar Kamble
d0d8ef79d1 gpu: nvgpu: use READ_ONCE/WRITE_ONCE 
In the upstream kernel ACCESS_ONCE is now deprecated with reason as
given in the following related commit:

    commit 381f20fceba8e ("security: use READ_ONCE instead of deprecated
    ACCESS_ONCE")

    ACCESS_ONCE() does not work reliably on non-scalar types. For
    example gcc 4.6 and 4.7 might remove the volatile tag for such
    accesses during the SRA (scalar replacement of aggregates) step.

Replace usages of ACCESS_ONCE with READ_ONCE and WRITE_ONCE in nvgpu.

Bug 2834141

Change-Id: I9904c49e1a4d7b17ed2fe54360051d08595a2982
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294096
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
rmylavarapu
9508cc6f42 gpu: nvgpu: sbr: Load and execute PUB 
Implmented functions to load and execute PUB which
is the safety POR.
PUB has following functionality:
1) Lower PLM
2) Reset PMU
3) FBPA register access to devtools

Secure Boot and Runtime (SBR) microcode comprises of
single PLM Update Binary (PUB) which will execute on
SEC2 Engine Falcon. NVGPU shall load and execute PUB
and wait for falcon halt. On successful halt NVGPU
shall proceed with ns ucode loading on respective
falcons.

NVGPU-4549

Change-Id: I8ea897a026bbe2b1714823aba51bfa51864dd68a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292330
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Antony Clince Alex
3e6332af9e nvgpu: posix: add fault injection handle 
Add fault injection handle for usleep.

Jira: NVGPU-4884

Change-Id: Ibf1fab6680068ff3da7b6e12d9efdb9f09bd1bc9
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299952
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Petlozu Pravareshwar
d0e81397d5 gpu: nvgpu: unit: update fault injection handler 
Update fault injection handling for following mock API:
 - sem_wait()

JIRA NVGPU-3909

Change-Id: I60271153249b77732eb53ef0038a886a51b5c971
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298872
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
shashank singh
0b4ccc7247 gpu: nvgpu: ignore deterministic submit flag for safety 
Safety only supports usermode submits so there is no need to process
DETERMINISTIC submit flag. For safety, while processing DETERMINISTIC
submit flag we are only setting deterministic field of struct
channel_gk20a and taking power reference with gk20a_busy(). On qnx
safety deterministic field is just used to check the syncpoint
allocation and taking power reference is a noop.

Jira NVGPU-4378

Change-Id: I1dc256db7d9fab93bef8fcc42bdb36f611b3ef40
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284644
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Petlozu Pravareshwar
038b928650 gpu: nvgpu: unit: update fault injection handler 
Update fault injection handling for following mock API:
 - nvdt_open()

JIRA NVGPU-3909

Change-Id: I9cf20f64cea60a1d039fa9f9622222a43dabb813
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298355
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Abdul Salam
8e840a5af1 gpu: nvgpu: Segregate clk unit members based on their accessibility 
Current clk unit has multiple header files under include folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within clk unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_clk_inf.h from include which only
clk can access.
All public items are moved into include/clk.h which other units can
access and removed the clk_xxx.h files

NVGPU-4689

Change-Id: I469270ae539e09a3f6fe6187207791732407863e
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298220
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Dinesh
0ae451059c gpu: nvgpu: Fix misra rule 5.1 
This is fixing the following misra violation

MISRA 5.1 :
	Declaration with identical names.

The first 31 characters of identifiers
"nvgpu_nvhost_syncpt_unit_interface_get_aperture" and
"nvgpu_nvhost_syncpt_unit_interface_get_byte_offset" are identical.

JIRA NVGPU-4811

Change-Id: Ib862c4acd53cf748b47c1edffa91b5f033c08953
Signed-off-by: Dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298136
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
ajesh
1c1dca5d6f gpu: nvgpu: avoid hard coded constants 
Replace the hard coded numeric constants in posix unit.

Jira NVGPU-4954

Change-Id: I9f57e2d60b44c942924c47a7e38c237c732b13b0
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289633
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
tkudav
03393131fb gpu: nvgpu: Add BUG_ON to avoid division of zero 
Confirm that ptimer_src_freq is not zero before using it in
arithmetic operations. This check will avoid accidental
division by zero.

JIRA NVGPU-4925

Change-Id: I44cb895e00d64303f4a6bc0ab1f4e3018a33fa6a
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294654
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Petlozu Pravareshwar
c6a0ffe0d6 gpu: nvgpu: unit: update fault injection handler 
Update fault injection handling for following mock APIs:
 - NvTegraSysInit()
 - waitfor()
 - procmgr_daemon()
 - procmgr_ability()
 - sem_init()
 - sem_post()
 - pthread_sigmask()
 - sigaction()

JIRA NVGPU-3909

Change-Id: I7e40289f1f57bc61261aeda09af531e47da9674e
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2290958
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
sagar
8c04d2f000 gpu: nvgpu: skip classes in obj_alloc 
Currently, we are performing obj ctx alloction for bellow classes

 1. VOLTA_COMPUTE_A
 2. VOLTA_DMA_COPY_A
 3. VOLTA_CHANNEL_GPFIFO_A

In safety, we use Async CE but not GRCE.
So allocating obj context only for COMPUTE_A and return success(0) for
all other valid classes, after setting class in the channel struct.

Jira NVGPU-4378

Change-Id: Ie99872e062cc66f9ddf699397a13df85c3d8d59e
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287486
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
tkudav
052bcfb2d2 gpu: nvgpu: Add doxygen comments for common.top 
common.top HAL get_max_lts_per_ltc was wrongly moved under
NON-FUSA HAL. Move it outside the @cond DOXYGEN_SHOULD_SKIP_THIS
and add doxygen comments for it.

JIRA NVGPU-5021

Change-Id: I8422be878c427df850ac4580283d777abd417462
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294561
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
shashank singh
fa42a07343 gpu: nvgpu: add missing pmu gops in doxygen 
gops for pmu_early_init is skipped in doxygen documentation by putting
it under DOXYGEN_SHOULD_SKIP_THIS. But it is needed in safety so move it
outside of the condition.

Change-Id: I7bab8a3617dd7b022a4b135b2db5893499458e75
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294117
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Abdul Salam
17cc9b2b98 gpu: nvgpu: Refactor Clock unit. 
Current clk unit has multiple header files under pmuif folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within clk unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_clk_inf.h from pmuif which only
clk can access.
All public items are moved into include/clk.h which other units can
access
This will help in documentation of items for public items.

NVGPU-4491

Change-Id: Iccb0571e05ecb3cb13363390bed8c7214409b543
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292318
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00