Currently, the ECC errors go unnoticed. ECC errors in GR are handled
by incrementing the ecc counters and clearing the intr registers. No
action is taken bassed on the ECC counters. The ECC intr prints are
also not printed by default.
Ideally, the ECC errors should trigger recovery if they cross the
error threshold. While we wait for the ideal ECC handling, convert
the conditional ECC prints to error messages.
JIRA NVGPU-7058
Change-Id: I2e54aeb5aef1d76dd6d4162eedd21cd529089b54
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2573029
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Tested-by: V M S Seeta Rama Raju Mudundi <srajum@nvidia.com>
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Currently, cbc init and compression tests are failing because MMU marks
cbc to be not safe.
- Modify cbc.get_base_divisor hal to use ltc_count = 1 for Tegra devices
- Update fb.cbc_configure to write compbit_backing_size value to
fb_mmu_cbc_top register.
- After config confirm that CBC is marked safe.
Bug 3353418
Change-Id: I1e9c27f47f7bfcf476f2499231951382e2e8653d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2570550
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Engine Level Power Gating(ELPG) for ga10b is enabled
on tot for silicon. elpg needs to be enabled
only after verification on silicon and after stress
testing the feature. To avoid issues during ga10b bring-up
with unverified ELPG feature, disable it by setting both
can_elpg_init and elpg_enable to false in ga10b platform
data.
Jira NVGPU-7033
Change-Id: I664d6e031339aa912b78769bd58a4e6d77dca1d0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2564197
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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Tested-by: Krishna Reddy <vdumpa@nvidia.com>
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It is observed that recovery on receiving the ESR MMU NACK exception
does not get triggered as the error returned by tpc level handler
is masked.
NACK is marked handled but recovery is not done and subsequent fb
intr handler does not trigger recovery since NACK is handled.
This leaves the HW engines in bad state.
Fix the tpc error return logic to trigger recovery during ESR MMU
NACK exception.
Bug 3318939
Change-Id: I475826f734e4366e853607e1e0338290ee28249b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2564764
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Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Move interrupt specific data-members from common.mc to common.cic
Some of these data members like sw_irq_stall_last_handled_cond need
To be initialized much earlier during the OS specific init/probe stage.
Also, some more members from struct nvgpu_interrupts(like stall_size,
stall_lines[]), which will soon be moved to CIC will also need to be
initialized early during the OS specific probe stage.
However, the chip specific LUT can only be initialized after the
hal_init stage where the HALs are all initialized.
Split the CIC init to accommodate the above initialization requirements.
JIRA NVGPU-6899
Change-Id: I9333db4cde59bb0aa8f6eb9f8472f00369817a5d
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2552535
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This change adds lsf_ucode_desc_wrapper to hold the pkc signature
header and corresponding lsf_lsb_header_v2. During blob preparation
based on the flag is_sig_pkc, the new header defines will be
packed into ls blob and passed to acr.
The flag NVGPU_PKC_LS_SIG_ENABLED is also added, which will be set
based on the acr core selection.
JIRA NVGPU-6365
Change-Id: I74e25d7c0f69d4007893e46006f97f2a607fd11f
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Signed-off-by: deepak goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2506136
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At present, there is an inconsistency in the order in which
gpc_tpc masks are reported to the userspace. Both gpc and
tpc masks are reported using physical-ids. However, the
gpc_tpc_masks array is ordered by logical gpc-ids and
not physical-ids. This creates a mismatch between the gpc
reported as enabled in the gpc_mask and its corresponding
gpc_tpc_mask.
Introduce field "gpc_tpc_mask_physical" which stores the
gpc_tpc_masks in physical order and update
NVGPU_GPU_IOCTL_GET_TPC_MASKS to return this field.
Bug 200665942
Change-Id: I63aa83414a59676b7e7d36b6deb527e2f3c04cff
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2531114
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- Add gops_fbp_fs and gops_gpc_pg struct
- Add HALs to write to NV_FUSE_CTRL_OPT_FBP and
NV_FUSE_CTRL_OPT_GPC fuses needed for floorsweeping
- Add set_fbp_mask and set_gpc_mask to probe FBP and GPC mask
respectively during gpu probe
- Add sysfs node: fbp_fs_mask and gpc_fs_mask to store
FBP and GPC floorsweeping mask sent from userspace
- Move the floorsweeping programming early in NVGPU’s GPU init
function and then issue a PRI init.
JIRA NVGPU-6433
Change-Id: I84764d625c69914c107e1e8c7f29c476c2f64f78
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2499571
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Enable nvriscv debug buffer feature in NVGPU.
Debug buffer is a feature to print the debug log from ucode onto console
in real time.
Debug buffer feature uses the DMEM, queue and SWGEN1 interrupt to share
ucode debug data with NVGPU.
Ucode writes debug message to DMEM and updates offset in queue to trigger
interrupt to NVGPU.
NVGPU copies the debug message from DMEM to local buffer to process and
print onto console.
Debug buffer feature is added under falcon unit and required engine
can utilize the feature by providing required param through public
functions.
Currently GA10B NVRISCV NS/LS PMU ucode has support for this feature
and enabled support on NVGPU side by adding required changes, with this
feature enabled, it is now possible to see prints in real time.
JIRA NVGPU-6959
Change-Id: I9d46020470285b490b6bc876204f62698055b1ec
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548951
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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- Fix GSP/PMU registers priv errors which are seen as part of boot sequence.
- Couple of GSP/PMU Falcon/NVRISCV registers are allowed to access
upon NVRISCV bootrom completion but these registers were needed
to configure on legacy chips to bootstrap/configure Falcon.
- Add is_falcon2_enabled or NVGPU_PMU_NEXT_CORE_ENABLED check
to skip these registers.
JIRA NVGPU-7025
Change-Id: I087a477ade6736398dea113f89894a0ff73ae647
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2553127
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Added below IVC commands to support VAB on HV.
* TEGRA_VGPU_CMD_FB_VAB_RESERVE - Enable & Configure VAB tracking
* TEGRA_VGPU_CMD_FB_VAB_FLUSH_STATE - Dump VAB to user buffer
* TEGRA_VGPU_CMD_FB_VAB_RELEASE - Disable VAB tracking
Also set HAL and enable VAB for ga10b vgpu.
Jira GVSCI-4619
Change-Id: Id7564611c24740ab8613e4baa420ee58fb52759a
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2507268
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Changes:
- This change will only init gsp software
state, nvgpu_gsp_bootstrap need to be called.
- CONFIG_NVGPU_GSP_SCHEDULER flag is created to
compile out the gsp scheduler code when needed.
- Created GSP engine reset which is needed when
ACR completed execution and need to load gsp fw.
NVGPU-6783
Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I2ce43e512b01df59443559eab621ed39868ad158
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554267
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Issue observed:
- In GA10B, it was observed that after recovery happens
ELPG does not engage.
- It was because, after CE reset, when nvgpu_submit_twod test
was run to engage ELPG, IDLE_FLIPPED_PWR_OFF signal was asserted.
- This means that when ELPG was engaged (engine is in PWR_OFF),
some idle signal flips (becomes non-idle) and this causes
IDLE_SNAP. After IDLE_SNAP is hit, ELPG will not engage further.
- After debugging from WAVES, it was observed that:
LCE0/LCE1 are not done with the reset sequence.
- The state of these LCE is RESET0. A pri request (pri read
to NV_CE_PCE_MAP register in CE) is seen that kicks it out of
RESET0. After this state, it goes through few states to update
some internal states (states RESET1/RESET2/PCE_MAP etc) and then
eventually settles down to IDLE state.
Solution:
- Read ce_pce_map_r register in recovery sequence (after ce reset).
- It is observed that when this read is added recovery is complete
and post that when nvgpu_submit_two test is executed, ELPG is engaging.
- This means that a pri read is needed after CE reset so that it settles
to idle state properly and post that ELPG can engage properly.
Bug 200734258
Change-Id: I5bb84921ca62a740fde81ffe6c29ccde4ebb341b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554493
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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Upstream Linux commit 393b06383fb7 ("debugfs: remove return value of
debugfs_create_bool()") updated the function debugfs_create_bool() to
remove the return value because it was not needed and user do not need
to check the return value. This breaks building the NVGPU driver against
the current upstream Linux kernel and the following error messages are
seen ...
nvgpu/drivers/gpu/nvgpu/os/linux/debug.c: In function ‘gk20a_debug_init’:
nvgpu/drivers/gpu/nvgpu/os/linux/debug.c:469:25: error: void value not ignored as it ought to be
l->debugfs_ltc_enabled =
^
nvgpu/drivers/gpu/nvgpu/os/linux/debug.c:507:32: error: void value not ignored as it ought to be
l->debugfs_runlist_interleave =
^
Fix this by not saving the value returned from debugfs_create_bool() and
remove the variables debugfs_ltc_enabled and debugfs_runlist_interleave
from the nvgpu_os_linux structure. Note that these variables are not
used anywhere in the driver and currently we don't check the return
value from debugfs_create_bool() and so there is no impact from this
change for older kernel versions.
JIRA LS-114
Change-Id: I539388c8645f2026292d8b9f33f55921dfda648f
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555299
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
On all chips except ga10b, the number of ROP, L2 units per FBP
were in sync, hence, their FS masks could be represented by a single
fuse register NV_FUSE_STATUS_OPT_ROP_L2_FBP. However, on ga10b, the ROP
unit was moved out from FBP to GPC and it no longer matches the number
of L2 units, so the previous fuse register was broken into two -
NV_FUSE_CTRL_OPT_LTC_FBP, NV_FUSE_CTRL_OPT_ROP_GPC.
At present, the driver reads the NV_FUSE_CTRL_OPT_ROP_GPC register
and reports incorrect L2 mask. Introduce HAL function
ga10b_fuse_status_opt_l2_fbp to fix this.
In addition, rename fields and functions to exclusively fetch L2 masks,
this should help accommadate ga10b and future chips in which L2 and ROP units
are not in same. As part of this, the following functions and
fields have been renamed.
- nvgpu_fbp_get_rop_l2_en_mask => nvgpu_fbp_get_l2_en_mask
- fuse.fuse_status_opt_rop_l2_fbp => fuse.fuse_status_opt_l2_fbp
- nvgpu_fbp.fbp_rop_l2_en_mask => nvgpu_fbp.fbp_l2_en_mask
The HAL ga10b_fuse_status_opt_rop_gpc is removed as rop mask is not
used anywhere in the driver nor exposed to userspace.
Bug 200737717
Bug 200747149
Change-Id: If40fe7ecd1f47c23f7683369a60d8dd686590ca4
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551998
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The NVGPU driver fails to build with current upstream Linux mainline
which will be Linux v5.14. Upstream Linux commit f39650de687e
("kernel.h: split out panic and oops helpers") re-organised some
kernel headers and removed the inclusion of 'linux/kernel.h' from
'include/asm-generic/bug.h'. This is now breaks the compilation of
NVGPU because the definitions in 'linux/limits.h' for UINT_MAX, INT_MAX,
etc are not found. Fix this by ensuring the 'linux/limits.h' is included
in 'nvgpu/types.h'.
JIRA LS-114
Change-Id: Id57322cd280532da6e6f9a16dbe54f88cd7a0cca
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554713
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
This CL covers the following modifications,
1) Added logic to skip the graphics unit specific sw context load
register write during context creation when MIG is enabled.
2) Added logic to skip the graphics unit specific sw method
register write when MIG is enabled.
3) Added logic to skip the graphics unit specific slcg and blcg gr
register write when MIG is enabled.
4) Fixed some priv errors observed during MIG boot.
5) Added MIG Physical support for GPU count < 1.
6) Host clk register access is not allowed for GA100.
So skipped to access host clk register.
7) Added utiliy api - nvgpu_gr_exec_with_ret_for_all_instances()
8) Added gr_pri_mme_shadow_ram_index_nvclass_v() reg field
to identify the sw method class number.
Bug 200649233
Change-Id: Ie434226f007ee5df75a506fedeeb10c3d6e227a3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2549811
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common.cic unit is divided into common.cic.mon and common.cic.rm
based on rm and mon process split.
CIC-mon subunit includes the code which is utilized in critical
interrupt handling path like initialization, error detection and
error reporting path. CIC-rm subunit includes the code corresponding
to rest of interrupt handling(like collecting error debug data from
registers) and ISR status management (status of deferred interrupts).
Split the CIC APIs and data-members into above two subunits.
JIRA NVGPU-6899
Change-Id: I151b59105ff570607c4a62e974785e9c1323ef69
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551897
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