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729 Commits

Author SHA1 Message Date
Terje Bergstrom
4493b6b200 gpu: nvgpu: gp10b: Enable CILP mode for compute 
Allow enabling CILP for compute. Set CTA by default.

Bug 1517461

Change-Id: I85cc931b810afb3ee6116de1200d01b52e1bc29e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/661298
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:03 +05:30
Mahantesh Kumbar
d40f3fb273 gpu: nvgpu: Handle MC pmu interrupts 
- Made changes to MC to get pmu interrrupts

Change-Id: I07aaec8392b1fbb34ae727bc7547a571aaeeb814
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/661212
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
 2016-12-27 15:22:03 +05:30
Mahantesh Kumbar
5452d16154 gpu: nvgpu: gp10b: gpmu elpg support 
Temporally used gm20b elpg sequencing values for gp10b elpg.

Bug 1525971

Change-Id: Ibffb5180979be9d7ee68cad67cd6f10cf23590c3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/662517
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
15839d4763 gpu: nvgpu: Implement gp10b context creation 
Implement context creation for gp10b. GfxP contexts need per channel
buffers.

Bug 1517461

Change-Id: Ifecb59002f89f0407457730a35bfb3fe988b907a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/660236
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
945e5e6832 gpu: nvgpu: gp10b: Correct SMMU bit number 
Bit 36 is the correct bit to indicate SMMU translation.

Bug 1580756

Change-Id: I761e70265d5981b07940f1d43716416829993827
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/658827
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
5d54f4660c gpu: nvgpu: gp10b: Change order of alpha & beta 
Change order of alpha & attribute buffers in CB. The new order
follows RM.

Change-Id: I2b24daa46055b3bd667a1026c282f74d56882623
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/657907
 2016-12-27 15:22:03 +05:30
Terje Bergstrom
59f267981c gpu: nvgpu: gp10b: Program CB sizes 
Program CB sizes.

Bug 1567274

Change-Id: Idc88f69b70e85bf950af852a9ca80a328d95883f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/654097
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
e5161d1518 gpu: nvgpu: gp10b: Implement SW methods 
Bug 1567274

Change-Id: I6d760eca7ac0931847f9a04a9d4a408519ade511
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/654098
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
230779e25b gpu: nvgpu: gp10b: Calc global context buffer size 
In gp10b we need to limit global context buffer size, and it needs
to be 128b aligned.

Change-Id: I51570e2457a374c09be4d611e683ae30917f9fc0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/657911
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
1f11c7ffe7 gpu: nvgpu: gp10b: Add new supported kind 
Bug 1567274

Change-Id: I38c3ffd6129893b02f6bef878a579925cf2bfa1e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/606931
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
a83e5281af gpu: nvgpu: gp10b: Define pagepool size 
Bug 1567274

Change-Id: I4369458d3af0c4da32af8a5881c8fe60b11f7632
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/606932
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
c23f7708ac gpu: nvgpu: gp10b: Define physical address width 
GP10B physical address width is 37 bits. Use old width for now,
and add gp10b specific definition. We can switch to new definition
once we've verified them.

Bug 1567274

Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601703
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
3cfc020b91 gpu: nvgpu: Write ZBC registers to DSS 
Bug 1567274

Change-Id: Ife98ae512c62bd26450e59338719c7a10635b5dd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601108
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
951100f636 gpu: nvgpu: Define gp10b big page size 
Set default big page size of 128kB.

Bug 1567274

Change-Id: Ie27c6ffa23b8d75ebd21afca267068604fb57f0b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/603498
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
e8c5b7dd17 gpu: nvgpu: Add SM registers 
Add SM registers which were taken into use in GPU
characteristics.

Bug 1551769
Bug 1558186

Change-Id: I705da9ac25556b6b94137199e0acd9af3c8e6422
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601020
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
2d23236ae2 gpu: nvgpu: Use queried interrupt ids 
Change-Id: I258b54447d09b32adc076de50997d792f0567af5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601019
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
7918de1c1b gpu: nvgpu: gp10b: Implement L2 query 
Bug 1567274

Change-Id: I0b8eaebc0949e70f6d8bfbb101048a3d95bec5e3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/602858
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:02 +05:30
Adeel Raza
68ad020887 gpu: nvgpu: headers for linsim CL 33823014 
Change-Id: I1b9172f0afa0391ce6289aa24dc1a993c723c90e
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/594681
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
caeddb940f gpu: nvgpu: gp10b: Enable interrupts in linsim 
Change-Id: I7d4211743793b905a20080bb44c62c036f23c854
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592336
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
317e7bb758 gpu: nvgpu: gp10b: Fill class numbers 
Fill class numbers to characteristics structure.

Bug 1567274

Change-Id: I129e79fa3f850899ae0c7d93704dc4786ad514d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/594404
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
0f4da5e118 gpu: nvgpu: Add own platform data to enable host1x 
Add gp10b platform data to enable sync point support.

Bug 1572701

Change-Id: Iaf03ecb8fb6b8bf4bb824e2a012c80dfe3f4fcae
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592099
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
23a4456260 gpu: nvgpu: gp10b: Add SM debug registers 
Add SM debug registers to gp10b, and regenerate headers.

Bug 1567274

Change-Id: Ifcfa65a6fbf16e89023caa5aaf4ae3a7846df749
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592646
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
1e4861a347 gpu: nvgpu: gp10b specific CB callbacks 
Bug 1570662

Change-Id: Icb7e90b1216acfd19bb3027dc9e9844eb08c99d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592101
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
0b50f2a202 gpu: nvgpu: Implement gp10b intr processing 
Bug 1567274

Change-Id: I2a6cef954b56d1f97208d29584e0748ec1c5e29d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/591628
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Kenneth Adams
16c511220e gpu: nvgpu: t18x, gp10b framework 
This change adds gp10b to the nvgpu build as
well as enabling CMA for buffer allocation.

Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76
Signed-off-by: Ken Adams <kadams@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/553324
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Terje Bergstrom
07b7a534fa gpu: nvgpu: Synchronize gp10b headers with gm20b 
Added all registers added to gk20a and gm20b to gp10b. Remove gp10b
trim registers, because they will not be accessed by CPU.

Bug 1567274

Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590312
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:02 +05:30
Adeel Raza
1f3b9d851a gpu: nvgpu: headers for linsim CL 33759297 
Change-Id: Iaafb651875481b7fa31504642df86311ec9933a5
Signed-off-by: Adeel Raza <araza@nvidia.com>
 2016-12-27 15:22:02 +05:30
Adeel Raza
badee8f41a gpu: nvgpu: headers for linsim CL 33688874 
Bug 1561645

Change-Id: Iccd909d54fc5b1d1c8fbc903b5908bf6f7f22ec8
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/553151
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
 2016-12-27 15:22:01 +05:30
Ken Adams
dfdd5ba3cb gpu: nvgpu: gp10b headers 
first cut.  just to get started...

Change-Id: I3682909f9ac0a5395ec834046789356f53d0c47d
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/447753
 2016-12-27 15:22:01 +05:30