Different SKUs may require different nvlink speed and hence the
nvlink speed value should come from VBIOS. The initpll number
corresponding to speed is present in VBIOS Low Power Nvlink table
header. Parse this data from VBIOS and set corresponding nvlink
speed and minion initpll DLCMD as default.
We can no longer update the GV100 VBIOS with necessary nvlink speed
value. Hence the hardcoding stays for GV100.
The nvlink speed should match across the endpoints. So in speed_config
fops, communicate the speed to nvlink core-driver for co-ordination
with Tegra endpoint.
Bug 2418403
Change-Id: Ib6f60951d4ca1c275968707d4cc6d738ba3a3f08
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1938046
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The Tegra endpoint no longer supports 25G nvlink speed. As
the dGPU nvlink endpoint is only used with Tegra nvlink
point, remove support for 25G nvlink speed to avoid speed
mismatch between endpoints.
Bug 2083356
Change-Id: I79609073af3975ce90421f66800380ec596084b3
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1940134
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.
JIRA NVGPU-1019
Change-Id: I8c9ad786a741b78293d0ebc4e1c33d4d0fc8f9b4
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921260
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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NVHSCLK registers used by NVLINK IP are part of dev_top
hardware headers. This patch adds "Top" as a separate
unit and exposes HALs to access dev_top registers. The top
unit contains top-level configuration information and any
extra registers or features that do not fit into another block's
feature set.
JIRA NVGPU-1053
JIRA NVGPU-966
Change-Id: Id9a43d4a1c5397959897a242ea97a39a1b95f916
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803632
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for calls to nvgpu_mutex_init and
improves related error handling.
JIRA NVGPU-677
Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805598
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Currently, we need to include the MC hardware header in nvlink file
to generate reset mask.
We can use the reset_enum present in DEVICE_INFO table's IOCTRL entry
which is meant to index into NV_PMC_ENABLE_DEVICE register bitfields.
This allows us to not #include the MC hardware header in nvlink IP
file.
JIRA NVGPU-966
Change-Id: I037498038b12f795ee444916fb586355ebf04bb3
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796819
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We parse the DEVICE_INFO table entries to get IOCTRL(NVLINK)
engine related information like the pri_base_addr, reset_enum,
and the intr_enum.
For grouping the chained entries per IP, the current parsing logic
relies on the fact that engine_type entry for an IP will be parsed
before other entries in the chained group.
As the enum_type entry (which contains the reset_enum) appears
ahead of the engine_type entry, the parsing logic fails and we read
reset_enum as 0.
Modify the parsing logic to group the chained entries correctly.
Also we were using a wrong API to extract the reset/intr_enum from the
table entry.
JIRA NVGPU-966
Change-Id: I68052db5d1c88a15e04f311486f3f639caf9ed9e
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796808
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We do not use the stored hshub_config* register values.
Remove these redundant fields from nvlink data structure too.
This also allows us to not #include a FB hardware header in
nvlink.
JIRA NVGPU-966
Change-Id: I3be169a958ec17370b55889d1e1fbabb887a79fd
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794955
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In the current code, gk20a.h includes io.h which gets directly included
in a lot of other files. io.h contains methods which uses a struct
gk20a as a parameter leading to a circular dependency between io.h
and gk20a.h. This can be mitigated by removing io.h from gk20a.h as
part of larger effort to moving gk20a.h to nvgpu/gk20a.h
JIRA NVGPU-597
Change-Id: I93e504fa9371b88152737b342a75580c65e8f712
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1787316
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VBIOS link_disable_mask should be sufficient to find the connected
links. As VBIOS is not updated with correct mask, we parse the DT
node where we hardcode the link_id. DT method is not scalable as same
DT node is used for different dGPUs connected over PCIE. Remove the
DT parsing of link id and use HAL to get link_mask based on the GPU.
JIRA NVLINK-162
Change-Id: Idb7b639962928ce48711a0d7fc277c4c324bee91
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1738967
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The sequence of INIT* minion dlcmd varies between nvlink 2.0 and 2.2.
The order is strict for 2.2. Also there are new dlcmds added to the
nvlink bringup sequence. Add HAL to allow sequence update for nvlink 2.2.
Old sequence:
INITLANEENABLE-> INITDLPL
New Sequence:
INITDLPL->INITDLPL_TO_CHIPA->INITTL->INITLANEENABLE
JIRA NVLINK-176
Change-Id: I49e0a726f56e7d6122ac4cddf0f0e021d16f1926
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1738329
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On nvlink 2.2, we poll for sublink substate to be stable before checking
sublink primary state. Currently, we read both TX and RX sublink state
during set_sublink_mode() irrespective of which sublink mode is changed.
This is not correct when we are polling on substate value while getting
sublink state.
JIRA NVLINK-164
Change-Id: I474705f059dbf41e5fb7e45bef455c33ee21aa95
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1734539
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Before nvlink 2.2, driver was responsible for setting the NVLink clocks
during NVLink initialization. For the purpose of security, NVLink PLL
handling is moved to Minion in nvlink 2.2 and driver should stop writing
to these registers.
JIRA NVLINK-167
Change-Id: I18392a29c322da55053037bfde62c8f74ee75288
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730597
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RXDET is supported only on nvlink 2.2 devices and forward.
Add HAL to run RXDET selectively based on chip. RXDET needs to be
done after the links are out of reset but before any other link
level initialization.
minion_send_cmd is also made non-static to support RXDET
functionality.
JIRA NVLINK-160
Change-Id: Ic65b8dbc7281743f62072089ff3c805521ac9b38
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729525
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On GV100, we could not enable reflck repeater at source of PLL
which is shared by link 0/1. So we do not allow link 0 and 1 to
be used on GV100. This refclk repeater is present only on GV100.
Remove the check as we currently use link3 on GV100 and do not
plan to use any other link.
JIRA NVLINK-162
Change-Id: I9ffcc0b20d084a208271d2c594ec64b5bafaabfb
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1734538
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TLC buffer sizes and credit init values do not match with
the values recommended by IAS for dGPU-Xavier configuration.
These buffer configuration values affect the latency over link.
JIRA NVLINK-158
Change-Id: I7822747cb0ae5a5efdd2d57e2104d0cb30bf9352
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1686601
Reviewed-by: Automatic_Commit_Validation_User
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Migrate to the new NVLINK MINION ucode format. The new format strips out
an unnecessary ACR header from the ucode image. Moving to the new format
will allow MINION ucode generation scripts to be unified.
Bug 2113404
Change-Id: I9a72d6c3fa5edd50a4ec5eb835d157672931f994
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709986
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The following changes implements the initial (as per bringup) nvlink driver.
(1) SW initialization of nvlink core driver structures
(2) Nvlink interrupt handling
(3) Device initialization (IOCTRL, pll and clocks, device level intr)
(4) Falcon support for minion
(5) Minion load and bootstrapping
(6) Link initialization and DL PROD settings
(7) Device Interface init (and switching HSHUB to nvlink)
(8) HS set/get mode for both link and sublink
(9) Topology discovery and VBIOS settings.
(10) Ensures we get physical contiguous memory when Nvlink is enabled
This driver includes a hack for the current single dev/single link limitation.
JIRA: EVLR-2331
JIRA: EVLR-2330
JIRA: EVLR-2329
JIRA: EVLR-2328
Change-Id: Idca9a819179376cc655784482b24b575a52fa9e5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1656790
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