MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. In the case of the pmu_setup_elpg operation, all
implementations were always returning 0, so this patch changes the
signature to return void instead.
JIRA NVGPU-3036
Change-Id: I6f0a79314535ba9e3c65d28399b117b058bb23ca
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092680
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- Move the perfmon unit source code to common/pmu/perfmon/ folder
- Separate perfmon unit headers under include/nvgpu/pmu/pmu_perfmon.h
- Make a new structure: nvgpu_pmu_perfmon for perfmon unit
- This new struct combines all perfmon unit variables like
perfmon_query, perfmon_ready etc. into one
structure as a part of perfmon unit refactoring.
- Use pmu_perfmon struct to access all perfmon variables.
- Eg: pmu->pmu_perfmon->perfmon_query, pmu->pmu_perfmon->perfmon_ready
and so on.
JIRA NVGPU-1961
Change-Id: I57516c646bfb256004dd7b719e40fafd3c2a09b2
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2080555
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Created PMU super surface unit & moved structs/functions related to
super surface under a unit, separated super surface structs into
private/public based on its usage/access, made changes to supper
surface dependent files to reflect supper surface changes
respective to unit.
JIRA NVGPU-3045
Change-Id: I6ac426052eb60f00b432d9533460aa0afd939fe3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088405
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lsfm-LS falcon manager
Created lsfm unit under common/pmu/lsfm, moved functions &
variables related to lsfm functionality under lsfm unit,
within lsfm unit created separate files based on init which
does chip specific s/w init, separated private/public
functionality.
JIRA NVGPU-3021
Change-Id: Iad4a4e5533122fb2387a4980581a0d7bcdb37d67
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2080546
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This patch fixes below two issues.
1.Currently clk arb exit is called after GPU registers are released.
This causes crash when clk arb WQ accesses GPU HW register for status.
The ideal way is to exit the clk_arb which removes the WQ from running
before calling lockout register.
2.Check if dGPU is dying during processing of PMU Commands.
This prevents race condition when PMU is waiting for response and device
is shutdown.
Bug 200488054
Change-Id: I812b07af7db4494d5ea2ed6197742ceb23d30a4b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081916
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Added the following HALs
- ramin.base_shift
- ramin.alloc_base
Use above HALs in mm, instead of using hw definitions.
Defined nvgpu_inst_block_ptr to
- get inst_block address,
- shift if by base_shift
- assert upper 32 bits are 0
- return lower 32 bits
Added missing #include for <nvgpu/mm.h>
Jira NVGPU-3015
Change-Id: I558a6f4c9fbc6873a5b71f1557ea9ad8eae2778f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077840
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pmu_ipc.c had functionality for rpc response handling and message cond
checks. This patch moves them to msg unit. And prepare cmd.h to group
together structs and functions related PMU commands.
JIRA NVGPU-1970
Change-Id: Iec5d72d02ab3ee51963631c828b301c56af8dc48
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079146
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PMU message handling unit can't be part of command handling unit as it
creates circular dependencies with the PMU tasks (clk, therm etc.)
PMU allocator unit shall encompass DMEM allocator and other allocators
used by PMU.
JIRA NVGPU-1970
Change-Id: I6ae3fa189d553eb9f79adf1abc753e1bb536241b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079144
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PMU mutexes used by FIFO and runlists is functionality independent of
the PMU command and message management.
Remove related functionality from pmu_ipc.c and prepare pmu_mutex.c.
Prepare PMU HAL unit that contains gk20a specific PMU mutexes
handling.
JIRA NVGPU-1970
Change-Id: I0204be2ef9d2c000004667af3c18dc527d7ac25f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079142
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PMU commands and messages management is based on sharing the data
through sequences. Functions for sending commands/allocating
payload update sequence data acquiring lock and those for
working on received messages read/free the sequence data
releasing lock.
JIRA NVGPU-1970
Change-Id: I4204dbfbf6f57b0f5a7016aed74ffea6e91ab06c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079141
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Move nvgpu_gr_wait_initialized to a gr.init hal function.
Move to hal function to avoid circular dependencies of headers.
Update nvgpu_gr_wait_initialized call to
g->ops.gr.init.wait_initialized
JIRA NVGPU-3016
Change-Id: Ia2e5f78da8528c76a8d08512151483579f250676
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085740
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Description:
nvgpu_clk_pmupstate is the global structure in clk units. It is declared
in clk.h and all clk units will include clk.h header.
nvgpu_clk_pmupstate struct will have structure pointers to all clk units
and will include genereic function pointers which are used by most clk
units. The reason why the function pointers is defined in this sturct,
and not included inside g->ops is because, these are only clk specific
functions and rest of the driver code is not dependent on this.
Each unit will have init function to allocate memory for its structure
and will initialize its local functions.
Changes:
1) Introduced nvgpu_clk_pmupstate in clk.h file. All the changes needed
to call the above struct from individual clk units.
2) Removed cyclic dependency headers in clk units by calling function
through pointers defined in clk.h.
3) Initialization of each unit is done in respective unit instead of
doing it in clk unit. Added *_init_pmupstate and *_free_pmupstate to
individual clk units.
4) Each unit clean up will be done separately while refactoring that
unit.
NVGPU-1963
NVGPU-2965
Change-Id: Iee79d7a812b62407252636057b104f952c94a229
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033537
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Created gr falcon hal unit with moving following hal functions
from gr to gr falcon:
u32 (*fecs_base_addr)(void);
u32 (*gpccs_base_addr)(void);
void (*dump_stats)(struct gk20a *g);
u32 (*fecs_ctxsw_mailbox_size)(void);
u32 (*get_fecs_ctx_state_store_major_rev_id)(struct gk20a *g);
Modified chip hals to populate these new functions and related code
now refers to gr falcon hals.
Modified kernel headers to have following defs for
fecs/gpccs base address in gm20b/gp10b/gv11b/tu104:
static inline u32 gr_fecs_irqsset_r(void);
static inline u32 gr_gpcs_gpccs_irqsset_r(void);
Created base gm20b hals for fecs/gpccs_base_addr and
removed redundant gp106 related hals.
JIRA NVGPU-1881
Change-Id: I16e820cc1c89223f57988f1e5723fd8fdcbfe89d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081245
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As part of PG unit refactoring move chip specific PG code
from common/pmu/pmu_<chip_name>.c/.h files to common/pmu/pg
folder
Make new files such as pg_sw_gp106.c/.h, pg_sw_gp10b.c/.h
and pg_sw_gv11b.c/.h for PG code.
NVGPU-1973
Change-Id: I97fa2395e388559edc26be5d64bfbc547d6a3e22
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077111
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As part of ACR bootstrap, falcon bootstrap request is sent to engine HAL
functions along with bootloader structure & perform falcon boot, but
this adds constraint to HAL separation due to struct parameter, so
made ACR to handle falcon boot by using falcon interfaces along with
new HAL ops to setup engine falcon setup. This also helps to reduce
code duplication too.
JIRA NVGPU-2039
Change-Id: I6ca29390b74d75bad0467a3c17623a395ec9bc25
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072940
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- Make a new structure: nvgpu_pmu_pg for PG unit
- This new struct combines all PG unit variables like
elpg_stat, elpg_refcnt, pg_init etc. into one
structure as a part of PG unit refactoring.
- Use pmu_pg struct to access all PG variables.
- Eg: &pmu->pmu_pg.elpg_mutex, &pmu->pmu_pg.pg_mutex
and so on.
NVGPU-1973
Change-Id: I9973072826f4089f6315827bce49fa30dbcbcdda
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071306
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This patch does the following.
1. Remove unused functions from volt_pmu.c.
2. Append public functions with nvgpu.
3. Remove GP106 functions and rename TU104 to generic functions.
4. Rename volt struct from gpu_ops.
5. Remove the unused volt.h header file.
6. Make local functions as static and put in order.
7. Remove unused inclusion on header files.
8. After 4, generic functions can be called directly instead of g->ops.
Jira NVGPU-1956
Change-Id: Icaea0ca817d37cccfc09241baa2f047ec2688169
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076535
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This struct was earlier moved to falcon_priv.h to give exclusive access
to only falcon unit. However with HAL unit needing access to this we
need to move it public header nvgpu/falcon.h.
JIRA NVGPU-1993
Change-Id: Ia3b211798009107f64828c9765040d628448812a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069688
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Semantics of the engine bootloader bootstrap are to set falcon mailbox0
register to non-zero value and verify that it is cleared to ascertain
successful completion of bootstrap.
Read was done in the engine bl_bootstrap related functions. Hence move
the write as well to those functions.
JIRA NVGPU-1993
Change-Id: I6d04148fbf1d517f0af8b4cfc2ee144d38704647
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034511
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Currenlty struct hs_acr passed to engine falcon bootstrap function
to pass falcon info to the falcon unit to execute the ACR HS bin
using engine falcon, as engine already cached the falcon info as
part its structure so removed struct hs_acr parameter pass.
JIRA NVGPU-2907
Change-Id: I0b647b2763c52e97de0c17cfdd273486138ee404
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069593
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Add new power/clock gating functions that can be called by
other units.
New clock_gating functions will reside in cg.c under
common/power_features/cg unit.
New power gating functions will reside in pg.c under
common/power_features/pg unit.
Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable
elpg and also in gr_gk20a_elpg_protected macro to access gr registers.
Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled
and slcg_enabled thread safe.
JIRA NVGPU-2014
Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025493
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