Fix for MISRA error Rule 14.2
Using a comma operator in the first clause of the for loop.
The first clause should either be empty or assign a value to the loop counter.
Jira NVGPU-3227
Change-Id: Ia46d8c9a8fb99f9e49be2eb56cabef6947c5b44b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111678
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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Fix MISRA error for Rule 14.3
The switch governing value "offset" cannot reach the default case.
Execution cannot reach this statement "default:".
Change switch statement with if else checking
Jira NVGPU-3227
Change-Id: Ib1ccfe2d3bef94ffaf3e0f963bc21260844d0c91
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110759
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Fix for MISRA Rule 14.2.
Using a comma operator in the first clause of the for loop.
The first clause should either be empty or assign a value to the loop counter.
Don't update the loop counter within the loop body.
Jira NVGPU-3227
Change-Id: I6bee94c0ce7198d6ff4e465e2e0d982d3d358161
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110758
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create a new unit common.fbp which initializes fbp support and provides
APIs to retrieve fbp data.
Create private header with below data
struct nvgpu_fbp {
u32 num_fbps;
u32 max_fbps_count;
u32 fbp_en_mask;
u32 *fbp_rop_l2_en_mask;
};
Expose below public APIs to initialize/remove fbp support:
nvgpu_fbp_init_support()
nvgpu_fbp_remove_support()
vgpu_fbp_init_support() for vGPU
Expose below APIs to retrieve fbp data
nvgpu_fbp_get_num_fbps()
nvgpu_fbp_get_max_fbps_count()
nvgpu_fbp_get_fbp_en_mask()
nvgpu_fbp_get_rop_l2_en_mask()
Use above APIs to retrieve fbp data in all the code.
Remove corresponding fields from struct nvgpu_gr since they are no
longer referred from that structure
Jira NVGPU-3124
Change-Id: I027caf4874b1f6154219f01902020dec4d7b0cb1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108617
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Remove gr_priv.h from outside gr files.
Add hal function in gr.init for get_no_of_sm. This helps
to avoid dereferencing gr in couple of files for g->gr->config and
avoid gr_priv.h include in those files.
Replace nvgpu_gr_config_get_no_of_sm call with
g->ops.gr.init.get_no_of_sm for files outside gr unit.
Jira NVGPU-3218
Change-Id: I435bb233f70986e31fbfcb900ada3b3bda0bc787
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109182
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Move remaining chip specific gr hal files to hal.gr.gr unit.
Remove unused headers include from hal files in hal.gr.gr unit
Update gr hal headers include location in the files currently
using these headers.
Jira NVGPU-3219
Change-Id: Ic632020a90ac4b8ac1e0359e979864b42f0ef2c0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105489
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MISRA rule 11.3 states that a cast shall not be performed between
a pointer to object type and a pointer to a different object type.
The following gr context routines convert a gr context buffer pointer
in the form of a u8 * to a u32 * before referencing the context buffer's
contents:
* gm20b_ctxsw_prog_check_main_image_header_magic
* gm20b_ctxsw_prog_check_local_header_magic
* gm20b_ctxsw_prog_get_num_gpcs
* gm20b_ctxsw_prog_get_num_tpcs
* gm20b_ctxsw_prog_get_extended_buffer_size_offset
* gm20b_ctxsw_prog_get_ppc_info
* gm20b_ctxsw_prog_get_local_priv_register_ctl_offset
Because the gr context buffer pointer starts out as a u32 * the
conversion to a u8 * isn't strictly necessary.
So this patch eliminates the conversion and the 11.3 rule violations
accordingly.
JIRA NVGPU-782
Change-Id: I0d24b539ad6ee8e56318287ce8640764285ed54d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102986
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gr_gk20a.ctx_vars struct right now stores sizes for golden_image, zcull,
pm_ctxsw, and gfxp_preemption_buffer.
but these sizes should be really owned by respective units and should
be assigned to units as soon as they are queried from FECS
Add new structure to nvgpu_gr_falcon to hold sizes that will be queried
from FECS
struct nvgpu_gr_falcon_query_sizes {
u32 golden_image_size;
u32 pm_ctxsw_image_size;
u32 preempt_image_size;
u32 zcull_image_size;
};
gr.falcon unit now queries sizes from FECS and fills this structure.
gr.falcon unit also exposes below APIs to query above sizes
u32 nvgpu_gr_falcon_get_golden_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_pm_ctxsw_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_preempt_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_zcull_image_size(struct nvgpu_gr_falcon *falcon);
gr.gr unit now calls into gr.falcon unit to initailize sizes, and then
uses above exposed APIs to set sizes into respective units
vGPU will too fill up struct nvgpu_gr_falcon_query_sizes with all the sizes
and then above APIs will be used to set sizes into respective units
All of above means size variables in gr_gk20a.ctx_vars struct are no more
being referred. Delete them.
Jira NVGPU-3112
Change-Id: I8b8e64ee0840c3bdefabc8ee739e53a30791f2b3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103478
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struct gr_gk20a defines boolean flag golden_image_initialized to
indicate if golden_image is initialized or not
common.gr.obj_ctx also added a flag of its own to check if golden_image
is ready
Add new API nvgpu_gr_obj_ctx_is_golden_image_ready() in
common.gr.obj_ctx unit to get status of golden_image
Use this new API everywhere to check if golden image is ready
Remove g->gr.ctx_vars.golden_image_initialized
Also remove ctx_mutex from struct gr_gk20a
Add new flag golden_image_initialized to struct nvgpu_pmu_pg and set it
when golden image is initialized. This is needed to avoid circular
dependency between GR and PMU
Jira NVGPU-3112
Change-Id: Id391294cede6424e15a9a9de29c40d013b509534
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099400
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Move gr_gk20a_handle_fecs_error from gr_gk20a.c to
nvgpu_gr_intr_handle_fecs_error in common.gr.intr unit
Move gr_gp10b_handle_fecs_error and gr_gv11b_handle_fecs_error
to hal.gr.intr unit
JIRA NVGPU-3016
Change-Id: I5b7c48ebfd7b13f497980c4d0b64d718649154bd
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103741
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Move gr_gp10b_handle_sm_exception from gr_gp10b to
gp10b_gr_intr_handle_sm_exception in hal.gr.intr unit
Move gr_gk20a_handle_sm_exception from gr_gk20a to
nvgpu_gr_intr_handle_sm_exception in common.gr.intr
Move nvgpu_report_gr_sm_exception to common.gr.intr
JIRA NVGPU-3016
Change-Id: I545ddca052122f87685f35f515831841a246dab3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103736
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g->ops.gr.get_preemption_mode_flags() hal is used to fetch information
on supported preemption modes and default preemption mode
Temporary struct nvgpu_preemption_modes_rec is used for this purpose
and is defined in gk20a/gr_gk20a.h right now.
Split above hal into two separate hals and move them to hal.gr.init unit
g->ops.gr.init.get_supported__preemption_modes()
g->ops.gr.init.get_default_preemption_modes()
These hals now return respective flags in pointers passed in function
parameter list, so there is no need to use temporary structure anymore
Hence delete struct nvgpu_preemption_modes_rec
Implement gm20b/gp10b chip specific hals in hal.gr.init unit.
Delete g->ops.gr.get_preemption_mode_flags() hal
Jira NVGPU-3126
Change-Id: I84f507fcd8d122bb7f0ecf697e8b4f16c9339ce1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102455
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Register gk20a non-arch-specific functions for gm20b
gpu_ops.fecs_trace,
Register nvgpu_os_linux_ops.fecs_trace.init_debugfs
gp10b_fecs_trace_flush is now replaced by gm20b_fecs_trace_flush in
fecs_trace_gm20b.* and the fecs_trace_gp10b.* files are removed.
Bug 2052906
Change-Id: Ie7598dbfe876e68ec0a1e2250dff9fa2de3c975f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088526
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MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. This patch contains fixes for all 17.7 violations
in the following units:
- nvgpu.hal.bus
- nvgpu.hal.fb
- nvgpu.hal.fifo
- nvgpu.hal.gr
JIRA NVGPU-3153
Change-Id: Iac9477ee7c36a0f2f8840e178dc5418e600f9c84
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100652
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gfxp_wfi_timeout_count/unit fields were stored in gr_gk20a.ctx_vars
struct so that any user could configure them through sysfs nodes
But the sysfs nodes are legacy and not being actively used by anyone.
Hence delete the sysfs nodes to configure these fields.
Since the gfxp timeout unit/count can now be statically programmed,
make following changes
- remove g->ops.gr.init_gfxp_wfi_timeout_count() hal
- remove g->ops.gr.get_max_gfxp_wfi_timeout_count() hal
- update g->ops.gr.init.preemption_state() hals to configure the values
using macros instead of caller passing the values
- update g->ops.gr.init.gfxp_wfi_timeout() hals to configure the values
using macros instead of caller passing the values
Finally, we don't need to store gfxp_wfi_timeout_count/unit fields
anymore, hence delete them from gr_gk20a.ctx_vars
Jira NVGPU-3112
Change-Id: Idbe5ab3053228dd177aca253545aac36d38ca8ad
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100219
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Removed unused struct from gr_gk20a.h
Change static allocation for struct gr_gk20a to dynamic type.
Change all the files that being affected by that change.
Call gr allocation from corresponding init_support functions, which
are part of the probe functions.
nvgpu_pci_init_support in pci.c
vgpu_init_support in vgpu_linux.c
gk20a_init_support in module.c
Call gr free before the gk20a free call in nvgpu_free_gk20a.
Rename struct gr_gk20a to struct nvgpu_gr
JIRA NVGPU-3132
Change-Id: Ief5e664521f141c7378c4044ed0df5f03ba06fca
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095798
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Move the nvgpu_report_gr_exception call from gr_gk20a to
gr_intr.c as nvgpu_gr_intr_report_exception
Move local function gk20a_gr_get_channel_from_ctx to gr_intr.c
as nvgpu_gr_intr_get_channel_from_ctx
JIRA NVGPU-1891
Change-Id: I21521ad50989582d8f166a98a21ea3b1dcd3bbff
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098229
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Move zcull size initialization to hal.gr.zcull unit.
This removes zcull dependency on falcon unit
Add new variable zcull_image_size to gr_gk20a.ctx_vars struct
Pass the size to nvgpu_gr_zcull_init()/vgpu_gr_init_gr_zcull() as
parameter to initialize zcull info
Jira NVGPU-3112
Change-Id: I54d966073dad658b4aad3a529f44c0478208b10c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098507
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Added new function to add require sw initionaltions. before enabling
gr hw. Added nvgpu_netlist_init_ctx_vars and nvgpu_gr_falcon_init_support
as part of this function:
int nvgpu_gr_prepare_sw(struct gk20a *g)
Moved following structure defs from gr_gk20a.h to gr_falcon.h and
renamed appropriately:
gk20a_ctxsw_ucode_segment -> nvgpu_ctxsw_ucode_segment
gk20a_ctxsw_ucode_segments -> nvgpu_ctxsw_ucode_segments
Moved following struct to gr_falcon_priv.h:
gk20a_ctxsw_ucode_info -> nvgpu_ctxsw_ucode_info
Moved following data from struct gk20a to new structure in gr_falcon_priv.h
struct nvgpu_gr_falcon:
struct nvgpu_mutex ctxsw_disable_lock;
int ctxsw_disable_count;
struct gk20a_ctxsw_ucode_info ctxsw_ucode_info;
Also moved following data from gr_gk20.h to struct nvgpu_gr_falcon:
struct nvgpu_mutex fecs_mutex;
bool skip_ucode_init;
wait_ucode_status
GR_IS_UCODE related enums
eUcodeHandshakeInit enums
Now add a pointer to this new data structure from struct gr_gk20a to
access gr_falcon related data and modified code to reflect this
change:
struct nvgpu_gr_falcon *falcon;
Added following functions to access gr_falcon data:
struct nvgpu_mutex *nvgpu_gr_falcon_get_fecs_mutex(
struct nvgpu_gr_falcon *falcon);
struct nvgpu_ctxsw_ucode_segments *nvgpu_gr_falcon_get_fecs_ucode_segments(
struct nvgpu_gr_falcon *falcon);
struct nvgpu_ctxsw_ucode_segments *nvgpu_gr_falcon_get_gpccs_ucode_segments(
struct nvgpu_gr_falcon *falcon);
void *nvgpu_gr_falcon_get_surface_desc_cpu_va(
struct nvgpu_gr_falcon *falcon);
JIRA NVGPU-1881
Change-Id: I9100891989b0d6b57c49f2bf00ad839a72bc7c7e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2091358
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Add new hal g->ops.gr.init.detect_sm_arch() in hal.gr.init unit to get
SM arch information. Remove g->ops.gr.detect_sm_arch().
Move corresponding functions to hal.gr.init unit
Remove unused function declaration for gr_gv11b_init_sw_veid_bundle()
Jira NVGPU-2961
Change-Id: Idfd5ce19c06978dc31cbcec2cd01cb2912eb3cf9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2097534
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Add new hal g->ops.gr.init.get_patch_slots() in hal.gr.init unit to get
patch slot count. Remove g->ops.gr.get_patch_slots().
Move corresponding functions to hal.gr.init unit
This hal does not need to be set for vGPU since it is not called in
that case
Jira NVGPU-2961
Change-Id: Ide488ae93af53a755da95faa268563070bd24bea
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2097533
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Add new HAL API g->ops.gr.init.get_max_subctx_count() in hal.gr.init
unit that returns max subctx count defined by h/w
Use this new hal in all GR code instead of using value stored in struct
fifo_gk20a
Jira NVGPU-2961
Change-Id: I5db1d827c3b7581a5ba7aca4314ba2f5a590d80c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2097532
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Add three hals in gr.falcon
- fecs_host_intr_status
This reads the fecs_host_intr_status, set the variables in the
nvgpu_fecs_host_intr_status struct to report back for gr to handle the
interrupts properly
- fecs_host_clear_intr
This helps to clear the needed bits in fecs_host_intr.
- read_fecs_ctxsw_mailbox
This reads the ctxsw_mailbox register based on register index.
Use these hals in gk20a_gr_handle_fecs_error and
gp10b_gr_handle_fecs_error functions.
JIRA NVGPU-1881
Change-Id: Ia02a254acc38e7e25c7c3605e9f1dda4da898543
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093917
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Move get_nonpes_aware_tpc hal to hal.gr.init . This hal is
implemented for gv11b.
Update sm_id_numbering hal to pass the gr_config struct pointer
as parameter to avoid dereferencing from gr inside hal.
JIRA NVGPU-2951
Change-Id: I1e06b634cc36741e116e41e581a18c7f5b373945
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093835
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Modify read_pending_interrupts hal to report the pending gr interrupt
bit back to isr to process.
semaphore_timeout interrupt bit is removed after gk20a chip.
Remove that bit checking from the isr function.
Remove some static functions for handling interrupt, which only calls
gk20a_gr_set_error_notifier. Call that function directly from isr
JIRA NVGPU-3016
Change-Id: Ic7084f038114fbce6d6b5c10a806dee6280e5c0a
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092876
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Refactor the ECC code present under gp10b/, gv11b/, and tu104/. To
do this a few things were required:
Firstly, move the ecc related C and H files under the aforementioned
directories over to their new home under hal/gr/ecc/. Also copy over
the ECC HAL code present in gp10b/gp10b.c - not sure why this was
there but it, too, needed to be refactored. Also handle all the
updated header paths and Makefiles to take these movements into
account.
Secondly add a new HAL in GR (gr.ecc) to handle ECC HAL ops. There's
only two: detect and init. init() was copied over from gr and detect
was added so that the common ECC code can call it in a chip agnostic
way. This is required so that the ECC detect can be moved out of the
gp10b init characteristics function.
Lastly update the ECC init flow in the common ecc module to call
detect() right before init().
JIRA NVGPU-3074
Change-Id: Iba1464a904f9a91a45f30902beadf6f912607e40
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090977
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