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112 Commits

Author SHA1 Message Date
deepak goyal
77d1e765f5 gpu: nvgpu: ga10b: Fix logic for BROM pass status 
Current code assumes riscv brom passed if it does not times out.
This patch explicitly checks for brom pass/fail or timeout.

Bug 3361416

Change-Id: I399a6cf9d32be92b24990532f81892642513ba54
Signed-off-by: deepak goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2585786
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-08-31 08:54:35 -07:00
mkumbar
de267c034c gpu: nvgpu: ga10b: Enable PKC support 
-Enable PKC support in ACR and LS-PMU
-Update the PMU f/w version.
-Enable PMU support by default.

Change-Id: I42bbe1b64ddc6ead9641c97d1ed27a9f4020510a
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2568609
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Deepak Goyal <dgoyal@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
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 2021-08-08 14:23:36 -07:00
smadhavan
d9add2db52 gpu: nvgpu: pkc signature verification support 
This change adds lsf_ucode_desc_wrapper to hold the pkc signature
header and corresponding lsf_lsb_header_v2. During blob preparation
based on the flag is_sig_pkc, the new header defines will be
packed into ls blob and passed to acr.
The flag NVGPU_PKC_LS_SIG_ENABLED is also added, which will be set
based on the acr core selection.

JIRA NVGPU-6365

Change-Id: I74e25d7c0f69d4007893e46006f97f2a607fd11f
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Signed-off-by: deepak goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2506136
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 2021-07-19 16:04:25 -07:00
mkumbar
fcf31d7063 gpu: nvgpu: ga10b: fix GSP/PMU priv error 
- Fix GSP/PMU registers priv errors which are seen as part of boot sequence.
- Couple of GSP/PMU Falcon/NVRISCV registers are allowed to access
  upon NVRISCV bootrom completion but these registers were needed
  to configure on legacy chips to bootstrap/configure Falcon.
- Add is_falcon2_enabled or NVGPU_PMU_NEXT_CORE_ENABLED check
  to skip these registers.

JIRA NVGPU-7025

Change-Id: I087a477ade6736398dea113f89894a0ff73ae647
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2553127
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 2021-07-16 16:44:08 -07:00
Antony Clince Alex
68e11c8bd3 gpu: nvgpu: remove nvgpu_next_gpuid.h 
Replace all usages of NVGPU_NEXT_GPUID and NVGPU_NEXT_DGPU_GPUID
with NVGPU_GPUID_GA10B and NVGPU_GPUID_GA100.

Remove nvgpu_next_gpuid.h and update yaml.

Jira NVGPU-4771

Change-Id: I3baf0de4eb5266b79aabd5c6ddf8442bf8f73419
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547735
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 2021-06-27 05:03:09 -07:00
Antony Clince Alex
d2919409e9 gpu: nvgpu: rename/collpase nvgpu_next functions and structs 
Replace all nvgpu_next functions/structs either by 1) collapsing them
into nvgpu legacy functions/structs 2) renaming them as follows:
- nvgpu_next_*() => nvgpu_(ga10b/ga100)_*()
- nvgpu_next_*() => (ga10b/ga100)_*()
- nvgpu_next_*() => nvgpu_*() [only if this doesn't cause collision]
- nvgpu_next_*() = > nvgpu_*_extra()

Create hal.sim unit and move Ampere+ SIM code into it.

Jira NVGPU-4771

Change-Id: I215594a0d0df4bd663bd875a0d0db47bcb9ff6a2
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548056
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2021-06-27 05:02:58 -07:00
Antony Clince Alex
f9cac0c64d gpu: nvgpu: remove nvgpu_next files 
Remove all nvgpu_next files and move the code into corresponding
nvgpu files.

Merge nvgpu-next-*.yaml into nvgpu-.yaml files.

Jira NVGPU-4771

Change-Id: I595311be3c7bbb4f6314811e68712ff01763801e
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547557
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2021-06-27 05:02:53 -07:00
Antony Clince Alex
c7d43f5292 gpu: nvgpu: remove usage of CONFIG_NVGPU_NEXT 
The CONFIG_NVGPU_NEXT config is no longer required now that ga10b and
ga100 sources have been collapsed. However, the ga100, ga10b sources
are not safety certified, so mark them as NON_FUSA by replacing
CONFIG_NVGPU_NEXT with CONFIG_NVGPU_NON_FUSA.

Move CONFIG_NVGPU_MIG to Makefile.linux.config and enable MIG support
by default on standard build.

Jira NVGPU-4771

Change-Id: Idc5861fe71d9d510766cf242c6858e2faf97d7d0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547092
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 2021-06-27 05:02:47 -07:00
Sagar Kadamati
3e43f92f21 gpu: nvgpu: add ga10b & ga100 sources 
Mass copy ga10b & ga100 sources from nvgpu-next repo.
TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1

Jira NVGPU-4771

Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-06-17 12:56:16 -07:00
Sagar Kamble
ac30c4cb65 gpu: nvgpu: change acr bootstrap completion info message 
Following information message was printed unconditionally. Often, it
is not useful.

nvgpu_acr_wait_for_completion:100  [INFO]  flcn-0: sctl reg 7021 cpuctl reg 50

It is okay to move this to nvgpu_acr_dbg.

bug 200734207

Change-Id: Ie66caf20d0e2eb692532e26bf89417342a054cf8
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2536471
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2021-06-02 19:40:26 -07:00
Ramesh Mylavarapu
a9a7e4f018 gpu: nvgpu: allocate wpr reserve space for NVRISCV pmu 
Falcon image is cleanly partitioned between a code and
data section where we don't need extra reserved space.
NVRISCV image has no clear partition for code and data
section, so we need reserved wpr space for runtime use.

Bug 200709761

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I80fa89fc10d0a0fd2fb8b74bae499b66d5563e00
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2509553
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2021-05-04 18:04:30 -07:00
smadhavan
5dacead521 nvgpu: gpu: adds support for ACR dbg/prod. 
ACR ucode is encrypted using different keys for prod/dbg boards.
This change adds a check to select ACR ucode based on board type.

ACR ucode binaries are also renamed with "nv_" prefix to conform
to release naming conventions.

Bug 2672836

Change-Id: I48818f018f903c0d03642c12485d60e392121eb6
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2492587
Reviewed-by: Andrey Jivsov <ajivsov@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2021-05-04 10:05:52 -07:00
Divya Singhatwaria
6ffadc0e32 gpu: nvgpu: Remove hard coded constants from ACR 
During code inspection use of some hard coded
constants was found in some parts of the code.
Some constants are replaced by macros and some
are declared using const keyword.

JIRA NVGPU-6260

Change-Id: I95112dfcac7c8b996789a68e7ddf78b16713a823
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485727
(cherry picked from commit b7e554267d9ef94ae5ac4529f4758127b97d3ba5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2492451
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Andrey Jivsov <ajivsov@nvidia.com>
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 2021-03-27 04:57:37 -07:00
ajesh
0030dc3eb4 gpu: nvgpu: fix MISRA violations in Posix unit 
Fix violations of MISRA rule 5.4 in Posix unit.

JIRA NVGPU-6534

Change-Id: I9471e5fca913ca8cc19403998fdbe5450fb49879
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488184
(cherry picked from commit f9bc21ca8d96e9c531a1b0077cfe1e78502e7ee5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491855
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2021-03-04 00:37:15 -08:00
deepak goyal
90e5950174 nvgpu: gpu: adds support for ACR dbg/prod. 
ACR ucode is encrypted using different keys for prod/dbg boards.
This change adds a check to select ACR ucode based on board type.
Note: This support is added for t18x. In the sub-sequent CL, support
for T210 will be added.

Bug 2672836

Change-Id: Ib209f25463d05edae576cfd47b63f562cb8f61e6
Signed-off-by: deepak goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2471590
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-01-22 07:02:48 -08:00
mkumbar
65111b64f2 gpu: nvgpu: Add RISCV LS PMU support 
-Add RISCV LS PMU support by adding RISCV LS PMU ucode to the blob.
-Modify the PMU RTOS sequence based on NEXT CORE enable flag.

JIRA NVGPU-6303

Change-Id: I4e2b989f9903b72a6327c931eb3c02f8cef2aa75
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2447388
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-17 18:36:44 -06:00
mkumbar
ee7cdf1fff gpu: nvgpu: Add multiple signature parsing support for ACR 
- Add multiple signature parsing support for ACR using ucode version
fuse value.
-Signature file contains multiple signatures and need to select
one signature using ucode version to validate the ucode.

Bug 200673810

Change-Id: I39007d4e2e8bb959caf278275d153b633a775def
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2455171
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
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 2020-12-15 14:13:48 -06:00
smadhavan
260365bfe1 gpu: nvgpu: acr: falcon2 acr interface 
This change:
* adds new flcn2_acr_desc to hold the ls ucode blob and wpr details
* adds nvgpu_mem type struct acr_falcon2_dmem_desc to copy the acr desc
  struct to sys mem. The addr of this mem location is then passed to
  ucode for consumption.
* changes return type of patch_wpr_info_to_ucode to int as it is required
  for nvgpu-next and return 0 for legacy implementations.

JIRA NVGPU-5736

Change-Id: I2f0ef655602ecdddb022c7330171b81db8cc4ce5
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2410683
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:13:28 -06:00
smadhavan
992b848ba6 gpu: nvgpu: make acr_wait_for_completion non-static 
This change makes acr_wait_for_completion
externally linked for use in nvgpu-next.

This will also add print of timeout limit used
when timeout error happens.

JIRA NVGPU-5736

Change-Id: If71f1394fabf37795adf7350a97de5dbd54290da
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2413800
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Deepak Nibade
7a937a6190 gpu: nvgpu: add debug logs for common.gr debugging 
Add separate flag gpu_dbg_gr to enable common.gr specific debugging.
Add this flag to all the existing debug logs that use gpu_dbg_fn or
gpu_dbg_info for debugging. Also add many other debugging logs that
might be helpful in debugging.

Removing debug log in gv11b_gr_init_get_nonpes_aware_tpc() as it dumps
too much data that does not seem useful.

Batch all interrupt enable functions in gr_init_setup_hw() together for
readability.

Jira NVGPU-5648

Change-Id: I0b857650122cdb1f974b452d28c26e7f142baf61
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2411740
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 2020-12-15 14:13:28 -06:00
deepak goyal
215403552f gpu: nvgpu: falcon2 core loading support 
- Added ops for new core.
- Added firmware structs for new core.

JIRA NVGPU-5736

Change-Id: Ifebc8987bf3a749803c1c5539e7d08716c1842a4
Signed-off-by: deepak goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2372104
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 2020-12-15 14:13:28 -06:00
mkumbar
880a639a86 gpu: nvgpu: skip simulation check for pmu-lsfm unit 
skip simulation check for pmu-lsfm unit as lsfm unit execution
is required on simulation to support secure boot of ctxsw.

JIRA NVPU-5200

Change-Id: I85b8896643551e782b59663b13c52df36169754c
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2396449
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 2020-12-15 14:13:28 -06:00
mkumbar
be6b37ba50 gpu: nvgpu: add support for ls_falcon_ucode_desc_v1 
igpu-next LSPMU ucode built with newer ucode descriptor which adds
changes to ACR blob construction.
Constructing ACR blob with legacy ucode descriptor by fetching required
data from ucode using newer descriptor.

JIRA NVGPU-5857

Change-Id: I6d830be1ec955242b95f522e648528a6b36e7cf5
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2382855
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
mkumbar
8fbc4e5b56 gpu: nvgpu: update ACR sub-wpr support 
update ACR sub-wpr support by deleting FRTS_VBIOS_TABLES
sub-wpr id support.
FRTS_VBIOS_TABLES sub-wpr causing NEXT dGPU ACR AHESASC
to hit ACR_ERROR_FLCN_ID_NOT_FOUND error and these tables
are not supported by NVGPU.

JIRA NVGPU-5462

Change-Id: I2de20b27a1a3ecbf4b3acb793eb22c637c4faba6
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2368213
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
smadhavan
c261f7573b gpu: nvgpu: support nvgpu-next secure boot 
Add NVGPU_NEXT_GPUID in
nvgpu_acr_init, nvgpu_acr_lsf_fecs_ucode_details,
and nvgpu_acr_lsf_gpccs_ucode_details functions.

JIRA NVGPU-5323

Change-Id: I514ab6de08ffaad323072499a92acef24668d3fc
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2361630
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:13:28 -06:00
smadhavan
f48c4e1887 gpu: nvgpu: remove fmodel check in secure boot 
This patch removes fmodel check in functions nvgpu_acr_init,
nvgpu_acr_construct_execute and nvgpu_acr_hs_bootstrap_acr since these
are called based on NVGPU_SEC_PRIVSECURITY flag and are independent of
platform for secure boot path.

JIRA NVGPU-5323

Change-Id: I8647ecc1de80900995dae953b4645bc8d281b829
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2367219
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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 2020-12-15 14:13:28 -06:00
mkumbar
4b206055ae gpu: nvgpu: Move SEC2 RTOS ucode to last in the WPR blob 
-This change is required to have reduced access of WPR1 region
for ACRLIB hosting falcon.
-By doing the above we allow only L3 Read access for ACRLIB
hosting falcon, enforcing better security.
-Fixed freeing of ACR resource at exit upon failure.

JIRA NVGPU-5459

Change-Id: I9c32a1fe723570cf3768f7e741a7a2e9d96cc1bf
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2365589
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2020-12-15 14:13:28 -06:00
mkumbar
2dfa74c831 gpu: nvgpu: ACR interface update 
FALCON_ID_END is used in ACR lsf_ucode_desc interface to allocate
space for dependency map but now more number of  FALCON’s supported
which will cause wrong allocation for dependency map, so required to
have its definition.

JIRA NVGPU-5462

Change-Id: Idaaa24ea1d2767a0b4ef44b1376239f945e39912
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2357747
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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 2020-12-15 14:13:28 -06:00
mkumbar
c43e3e4aeb gpu: nvgpu: acr: add fecs/gpccs sig files read for next dgpu 
add fecs/gpccs sig file read for next dgpu.

JIRA NVGPU-5461

Change-Id: Ib135dab8961c53d62fb7a95e378eba4c81d729a2
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2354622
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00
mkumbar
91af7efd23 gpu: nvgpu: enable ACR support for NEXT dGPU 
-Enabled ACR support for NEXT dGPU
-Blob creation & boot strap of LSPMU support skipped by ACR
 by checking flag "support_ls_pmu", lspmu support is not
 required until PSTATE support is enabled.

JIRA NVGPU-5461

Change-Id: I5a4c688926ca1c55aeb4cbbb9668c55bb35f9119
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2344582
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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Reviewed-by: Abdul Salam <absalam@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
1f6dfb54d1 gpu: nvgpu: Remove hard coded constants from ACR 
During code inspection use of some hard constants was
found in some parts of the code.
Those constants are replaced by macros

JIRA NVGPU-5030

Change-Id: I09212be40746317440218bc7ada9a578dde7c6ed
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2301596
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
48acd86cb3 gpu: nvgpu: ACR branch coverage for ucode blob 
- Add test scenarios for achieving branch coverage
  for failure of dynamic memory allocation while
  preparing ucode blob.
- Add more branch coverage for nvgpu_acr_bootstrap_hs_acr()
- Move GR reg space required for ACR tests to ACR unit test
  itself to remove dependency on GR unit

JIRA NVGPU-4319

Change-Id: I770a696a1681eb05243c7168878793a30cd59c13
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2286257
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:13:28 -06:00
mkumbar
5a17a7b85a gpu: nvgpu: ACR unit doxygen update 
Update doxygen for ACR intefaces.

JIRA NVGPU-4152

Change-Id: Id26d8c057c38d5f38bb9e09a18db65b8fc1e2877
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2275020
Tested-by: Deepak Goyal <dgoyal@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
smadhavan
2db5c623c4 nvgpu: gpu: adds support for ACR dbg/prod. 
ACR ucode is encrypted using different keys for prod/dbg boards.
This change adds a check to select ACR ucode based on board type.
Note: This support is added only for t19x.

This patch also enables the prints "DEBUG MODE" indicative of board/
acr_ucode signature type and sctl and cpuctl reg values.

Bug 2350733
Bug 2672832
Bug 2672836
JIRA NVGPU-4001

Change-Id: I936b811b5836152206b11ec615ee75d201939968
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2268880
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
4b0499498b gpu: nvgpu: Unit tests for common.hal.pmu.pmu 
Updating the test case to cover the
following ECC API:
- gv11b_pmu_ecc_init()

Also, since g->ops.pmu.secured_pmu_start is
called from nvgpu_pmu_rtos_init() (non-safe code)
so moved gv11b_secured_pmu_start() function under
CONFIG_NVGPU_LS_PMU flag

JIRA NVGPU-2192

Change-Id: Ia8d0386e81010b21b40437654c1f1667a450e060
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2274227
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
smadhavan
a46abe4d64 gpu: nvgpu: Reduce ACR timeout wait to 100msec 
10s wait for ACR timeout is longer than time allowed for
entire GPU boot sequence. Hence we need to reduce it.

This patch reduces ACR timeout wait period to 100msec
for silicon platforms and retains the existing 10s for
non silicon.

JIRA NVGPU-4898

Change-Id: I29e58b34f09ed595336bf833ed6db13553794827
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2282857
Reviewed-by: Automatic_Commit_Validation_User
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 2020-12-15 14:10:29 -06:00
Scott Long
20114c7c8c gpu: nvgpu: acr: misra 12.1 fixes 
MISRA Advisory Rule states that the precedence of operators within
expressions should be made explicit.

This change removes the Advisory Rule 12.1 violations from acr code.

Jira NVGPU-3178

Change-Id: Ibfcb23dbf9931efd1890c9b548c36462c55ae47d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2277477
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
mkumbar
2b36d309cc gpu: nvgpu: acr: update doxygen for acr interfaces 
Update doxygen for ACR intefaces.

Change-Id: Iede7be6ab6ba2ad34f564b7142e07f797a172ecf
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263178
Reviewed-by: Automatic_Commit_Validation_User
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 2020-12-15 14:10:29 -06:00
Sagar Kadamati
42ccc21c62 gpu: nvgpu: fix static violations in common 
* Updated types and added error checks
 * Modified GR condition for ctxsw disable count
   CERT-C error check was added to detect error on integer overflow
   But below logic couldn't detect first overflow, so updated condition

   INT_MAX < gr->ctxsw_disable_count --> it became true after overflow
   So, we didn't detected in first overflow and lead to assert on enable

JIRA NVGPU-3400

Change-Id: I6b0265a464f8f19efa7b0761612c6e9ffb3bd2bd
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2206282
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
8592b0591c gpu: nvgpu: Add fail scenarios in ACR unit tests 
- Add more fail scenarios in ACR unit tests to cover
  branches
- Return "err" value when "get_lsf_ucode_details" ops
  for fecs fails.

JIRA NVGPU-4319

Change-Id: Ic9ba0afb26b23f6e0c0ebd76feae5b1ba3098b93
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2252801
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
3853636720 gpu: nvgpu: Adding more tests in ACR unit 
Test the following function:
nvgpu_acr_construct_execute()

Also, add check for "invalid falcon id"
in the function nvgpu_acr_is_lsf_lazy_bootstrap()

JIRA NVGPU-4123

Change-Id: Icedca3eec76f5cedbd5f2857755a0a79c476dc8b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214742
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 2020-12-15 14:10:29 -06:00
Mahantesh Kumbar
e83278f4e4 gpu: nvgpu: NVGPU ACR interface doxygen update 
-Adding detailed description for NVGPU-ACR interfaces
 required for doxygen

JIRA NVGPU-4152

Change-Id: I2c0b5d173f04bf6ea995995ee9dfa0652e424db4
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2219874
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Mahantesh Kumbar
cb63f7db2f gpu: nvgpu: Moved NVGPU-ACR interfaces to separate file 
-Moved NVGPU-ACR interfaces to separate header file from
 ACR blob/bootstrap header files.
-Separation needed for NVGPU-ACR interface specification
 doxygen.

JIRA NVGPU-4152

Change-Id: Ia502380e62f53e0372549544e31ffff150e05017
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2219038
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 2020-12-15 14:10:29 -06:00
Mahantesh Kumbar
fbf219d8ba gpu: nvgpu: ACR func/struct version update for FUSA 
-Renamed ACR structs for FUSA, ACR FUSA code has struct names
 ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
 code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to  acr_blob_construct.c/h

JIRA NVGPU-2516

Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218265
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 2020-12-15 14:10:29 -06:00
Philip Elcan
67e1fbca1f gpu: nvgpu: acr: update acr init APIs 
Remove the second parameter for the nvgpu_acr_init() and
acr_construct_execute() functions so they only require the gk20a
object. The g->acr was always passed for this parameter. And this
makes the API signature match the other init functions in the driver.

JIRA NVGPU-3980

Change-Id: I8c513b1dcb9c6083f0f3e2f7b6f31dc78c5c8200
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202971
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Divya Singhatwaria
ac4520b0f7 gpu: nvgpu: Fix CERT-C violations in ACR unit 
Fixed the CERT-C INT30 and INT31 violations
in the ACR unit using:
nvgpu_safe_add_u32() and  nvgpu_safe_sub_u32()

JIRA NVGPU-4073

Change-Id: I360c8094578c65463e196bbb30e399d0369d0b00
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199438
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Mahantesh Kumbar
837f2a58f4 gpu: nvgpu: ACR's bootstrap_hs_acr() parameters clean up 
Private data struct "struct hs_acr" used incorrectly by adding
as input param to public function for ACR unit. Cleaned up &
added required chip specific ACR unit's function.

JIRA NVGPU-3811

Change-Id: I6cdcdb71c48ebff349de2b7a587d4d2cb0f0212c
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195019
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Mahantesh Kumbar
357828537d gpu: nvgpu: ACR bootstrap update 
Removed HS self-load & bootstrap public function as no other unit access
this function. Made changes to ACR bootstrap function to load & bootstrap
ACR HS ucode on respective Engine Falcon using Falcon unit HS ucode load
& bootstrap function.

JIRA NVGPU-3811

Change-Id: I293f12137e568610a0b95f668a8408f9fce0a5f0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195018
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Mahantesh Kumbar
e77a911568 gpu: nvgpu: Move HS Falcon ucode bootstrap to Falcon unit 
Moving HS ucode bootstrap from ACR unit to Falcon unit as HS ucode
bootstrap needs to be accessed by multiple units. Currently FB unit
calls ACR unit function to do self HS load & bootstrap memory unlock
HS ucode. This adds dependency on ACR unit which is not correct. So,
moving to Falcon unit to make it generic.

JIRA NVGPU-3811

Change-Id: I3696296c9df661d821199cb93872265ef6d10bfc
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195016
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
smadhavan
238be35d5a gpu: nvgpu: Remove pmu_bl from GPU secure boot flow 
ACR HS ucode is currently loaded by pmu_bl.bin (falcon bootloader),
but ACR ucode can be loaded without bootloader support by directly 
copying non-secure/secure code to respective IMEM offset along with 
required data to DMEM, with this bootloader dependency is removed.

This patch uses nvgpu_acr_self_hs_load_bootstrap to directly load
acr ucode to imem using priv writes. This also removes the bootloader
related code

JIRA NVGPU-3811

Change-Id: Ie2632eb26e421de3765a99c5426471eb37bf1bc9
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2169976
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00