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540 Commits

Author SHA1 Message Date
Mahantesh Kumbar
b9696ee643 gpu: nvgpu: ga10b: update NVRISCV LSPMU 
- Set NVRISCV LSPMU app version to 0.
- Setting app version to 0 helps to load and boot
  multiple LSPMU ucode's without modifying the
  NVGPU driver.
- Add support for PMU NVRISCV prod and dbg bin's.
- This is corresponding change to LSPMU MPSK CL
  https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2576049

JIRA NVGPU-7061

Change-Id: I800953ca97af3badde1983aa99e09b4fe7453203
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2575341
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-08-22 11:05:03 -07:00
Vedashree Vidwans
e13ab1f9ea gpu: nvgpu: pmu: remove hw access from remove_pmu_support 
GPU HW registers are locked before remove_pmu_support.
Remove functions accessing HW registers.

Bug 3357477

Change-Id: I34a1923bfdb3afacd462f2646e2821569573a81a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2577627
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-08-17 09:45:42 -07:00
Sagar Kamble
f4571194b0 gpu: nvgpu: stop ELPG init thread during unload 
ELPG initialization thread creation can fail when the process is killed.
That leads to driver resume failure.

That thread was stopped on suspend and re-created on resume. To avoid
the issue above, don't stop the ELPG thread in suspend and let the
first created thread handle the ELPG state transitions always.
And stop the ELPG thread during unload.

Also fix couple of instances of config flag as:

s/CONFIG_PMU_POWER_PG/CONFIG_NVGPU_POWER_PG

bug 3345977

Change-Id: I8952edf8d1664ed258f238e265002e716d1bf5c2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2573763
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Ashish Mhetre <amhetre@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-08-11 01:55:46 -07:00
mkumbar
de267c034c gpu: nvgpu: ga10b: Enable PKC support 
-Enable PKC support in ACR and LS-PMU
-Update the PMU f/w version.
-Enable PMU support by default.

Change-Id: I42bbe1b64ddc6ead9641c97d1ed27a9f4020510a
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2568609
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Deepak Goyal <dgoyal@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-08-08 14:23:36 -07:00
smadhavan
d9add2db52 gpu: nvgpu: pkc signature verification support 
This change adds lsf_ucode_desc_wrapper to hold the pkc signature
header and corresponding lsf_lsb_header_v2. During blob preparation
based on the flag is_sig_pkc, the new header defines will be
packed into ls blob and passed to acr.
The flag NVGPU_PKC_LS_SIG_ENABLED is also added, which will be set
based on the acr core selection.

JIRA NVGPU-6365

Change-Id: I74e25d7c0f69d4007893e46006f97f2a607fd11f
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Signed-off-by: deepak goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2506136
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-19 16:04:25 -07:00
mkumbar
860027dc8c gpu: nvgpu: ga10b nvriscv pmu ucode update 
-PMU ucode from gpmu/ga10b branch.
-Perfmon, PG and ACR features are enabled with bin.
-update APP_VERSION_NVGPU_NEXT_CORE PMU app version
 to 30147895
-Add dummy bytes to pmu boot params.
-P4 CL #30187066

JIRA NVGPU-6955

Change-Id: I17c51edaa2d4f8cd34e0e43044d62aae52b8ef2a
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2559075
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-18 00:05:04 -07:00
mkumbar
87984ea344 gpu: nvgpu: support nvriscv debug feature 
Enable nvriscv debug buffer feature in NVGPU.
Debug buffer is a feature to print the debug log from ucode onto console
in real time.
Debug buffer feature uses the DMEM, queue and SWGEN1 interrupt to share
ucode debug data with NVGPU.
Ucode writes debug message to DMEM and updates offset in queue to trigger
interrupt to NVGPU.
NVGPU copies the debug message from DMEM to local buffer to process and
print onto console.

Debug buffer feature is added under falcon unit and required engine
can utilize the feature by providing required param through public
functions.

Currently GA10B NVRISCV NS/LS PMU ucode has support for this feature
and enabled support on NVGPU side by adding required changes, with this
feature enabled, it is now possible to see prints in real time.

JIRA NVGPU-6959

Change-Id: I9d46020470285b490b6bc876204f62698055b1ec
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548951
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-17 12:45:00 -07:00
mkumbar
fcf31d7063 gpu: nvgpu: ga10b: fix GSP/PMU priv error 
- Fix GSP/PMU registers priv errors which are seen as part of boot sequence.
- Couple of GSP/PMU Falcon/NVRISCV registers are allowed to access
  upon NVRISCV bootrom completion but these registers were needed
  to configure on legacy chips to bootstrap/configure Falcon.
- Add is_falcon2_enabled or NVGPU_PMU_NEXT_CORE_ENABLED check
  to skip these registers.

JIRA NVGPU-7025

Change-Id: I087a477ade6736398dea113f89894a0ff73ae647
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2553127
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-16 16:44:08 -07:00
Ramesh Mylavarapu
b38b8a794d gpu: nvgpu-next: Update pg pre and post init structs 
SECURITY_HARDENING feature in pmu ucode leads to failure
in pg pre and post init rpcs due to mismatch is interface
struct size. This change will update pg pre and post init
nvgpu-pmu interface structs as per pmu ucode.

NVGPU-6421

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: Ied9179b3a7ee1923dba56e792979115f3a19f7e5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551026
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-06-30 10:22:45 -07:00
Antony Clince Alex
68e11c8bd3 gpu: nvgpu: remove nvgpu_next_gpuid.h 
Replace all usages of NVGPU_NEXT_GPUID and NVGPU_NEXT_DGPU_GPUID
with NVGPU_GPUID_GA10B and NVGPU_GPUID_GA100.

Remove nvgpu_next_gpuid.h and update yaml.

Jira NVGPU-4771

Change-Id: I3baf0de4eb5266b79aabd5c6ddf8442bf8f73419
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547735
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-06-27 05:03:09 -07:00
Antony Clince Alex
d2919409e9 gpu: nvgpu: rename/collpase nvgpu_next functions and structs 
Replace all nvgpu_next functions/structs either by 1) collapsing them
into nvgpu legacy functions/structs 2) renaming them as follows:
- nvgpu_next_*() => nvgpu_(ga10b/ga100)_*()
- nvgpu_next_*() => (ga10b/ga100)_*()
- nvgpu_next_*() => nvgpu_*() [only if this doesn't cause collision]
- nvgpu_next_*() = > nvgpu_*_extra()

Create hal.sim unit and move Ampere+ SIM code into it.

Jira NVGPU-4771

Change-Id: I215594a0d0df4bd663bd875a0d0db47bcb9ff6a2
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548056
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-06-27 05:02:58 -07:00
Antony Clince Alex
c7d43f5292 gpu: nvgpu: remove usage of CONFIG_NVGPU_NEXT 
The CONFIG_NVGPU_NEXT config is no longer required now that ga10b and
ga100 sources have been collapsed. However, the ga100, ga10b sources
are not safety certified, so mark them as NON_FUSA by replacing
CONFIG_NVGPU_NEXT with CONFIG_NVGPU_NON_FUSA.

Move CONFIG_NVGPU_MIG to Makefile.linux.config and enable MIG support
by default on standard build.

Jira NVGPU-4771

Change-Id: Idc5861fe71d9d510766cf242c6858e2faf97d7d0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547092
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-06-27 05:02:47 -07:00
Sagar Kadamati
3e43f92f21 gpu: nvgpu: add ga10b & ga100 sources 
Mass copy ga10b & ga100 sources from nvgpu-next repo.
TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1

Jira NVGPU-4771

Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-06-17 12:56:16 -07:00
Divya Singhatwaria
a1d0957a9b gpu: nvgpu: Update GP10B FW version 
Updated PMU ucode taken from P4 CL#30066529 for t18x igpu.
The ucode resolves the ELPG_DISALLOW_ACK timeout failure

P4 CL link for this PMU ucode changes:
https://p4sw-swarm.nvidia.com/changes/30066529

Bug 200588696

Change-Id: Ic45c37c75924c581d6ef91ffd754da287d63f4c6
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2544140
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-06-14 12:58:06 -07:00
mkumbar
d2349b32ec gpu: nvgpu: update SSMD array size 
-Update SSMD array size to hold all supported super-surface
members
-Handle the error and report if invalid SSMD ID is found.

issue: At present SSMD array size set to 32 but overall
33 super-surface members are supported, when 33rd member
accessed system crash happened due to overflow access,
so fixing it by setting the SSMD array size to actual
number of super-surface members supported

Bug 200721968
Bug 200721966

Change-Id: I5ba1084a661d7497056f13a053d2fc79d50f595c
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2528569
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-05-17 12:56:39 -07:00
mkumbar
e06eca9b17 gpu: nvgpu: FALCON/FALCON2 core selection based on fuse 
-Read the PMU and GSP fuse to select the FALCON/FALCON2 core
-FUSE read based on FALCON id is done in FUSE unit
-Core selection and info dump based on fuse is done in FALCON unit

JIRA NVGPU-6369

Change-Id: I0747f7383c60f546bbce94eb89c0a8bd41fa7471
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2465808
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-05-11 08:25:11 -07:00
Ramesh Mylavarapu
a0b1b3f2be gpu: nvgpu: add priv lockdown release check for NVRISCV pmu 
IRQ register access will cause priv errors if they
are accessed before priv lockdown is released.
This change adds a polling loop to check priv lockdown
before proceeding further while booting NVRISCV pmu.

Bug 200709761

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I44b8ce4c59b5a9f20901e5ce08610d17725da779
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2512351
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-05-04 18:04:25 -07:00
Ramesh Mylavarapu
4d3a935b1a gpu: nvgpu: enable lazy bootstrap support for NVRISCV pmu 
Lazy bootstrap is a secure iGPU feature where LS falcons(FECS and
GPCCS) are bootstrapped by LSPMU in both cold boot and recovery boot.
As there is no ACR running after boot, we need LSPMU to bootstrap LS
falcons to support recovery.
In absence of LSPMU, ACR will bootstrap LS falcons but recovery is
not supported.
This CL will enable Low secure falcon manager(lsfm) to support
Lazy bootstrap feature. This will allow nvgpu to send cmds
to lspmu to bootstrap LS falcons.

Bug 200709761

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I65d17cf5e07a45c040a9bb75f75cf18eb509cd4f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2506162
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-05-04 18:04:19 -07:00
Sagar Kamble
ecfd675d9b gpu: nvgpu: free pmu variables allocated in early_init on error in rtos_init 
On error in pmu_rtos_init, pmu state was freed partly. That lead to
invalid access on subsequent nvgpu poweron. Free all pmu state in
such case.

Bug 200575409

Change-Id: I11166b55dbe00a225e811425d21500c3143a354c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2503577
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-03-24 14:47:44 -07:00
Divya Singhatwaria
4d02580df0 gpu: nvgpu: remove ZBC save/restore by PMU 
- ZBC save/restore registers are removed in GP10B PMU ucode.
- These registers are saved/restored from CTXSW ucode during
  ELPG entry/exit.
- Accessing the ZBC registers will cause PMU EXTERR error.
- To resolve this, ZBC functionality is removed from GP10B
  feature list in PMU ucode.
- From NvGPU driver, set NVGPU_PMU_ZBC_SAVE bit to false
  for GP10B
- Updated the GP10B PMU app version for the ucode:
  https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2476260

P4 CL link related to this PMU ucode change:
https://p4sw-swarm.nvidia.com/changes/29594520

Bug 3233071
Bug 200696431

Change-Id: If3f1707b79699e7e2e65367418b25ac71b09cf0b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
(cherry picked from commit 9170f2b77c)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2500641
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2021-03-24 03:36:40 -07:00
Divya Singhatwaria
cc34df76f9 gpu: nvgpu: Add support for ELPG_MS feature 
- To enable ELPG_MS feature, add identifier for
  MS_LTC engine.
- The identifier is then passed
  as pg_engine_id to enable the MS_LTC engine.
- Add enable flag NVGPU_ELPG_MS_ENABLED for
  enabling/disabling ELPG_MS feature at init.

JIRA NVGPU-6430

Change-Id: Ie1f477918332d85ec98b3bd4d05b8e773d74eab8
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480750
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-03-18 15:29:06 -07:00
ajesh
0030dc3eb4 gpu: nvgpu: fix MISRA violations in Posix unit 
Fix violations of MISRA rule 5.4 in Posix unit.

JIRA NVGPU-6534

Change-Id: I9471e5fca913ca8cc19403998fdbe5450fb49879
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488184
(cherry picked from commit f9bc21ca8d96e9c531a1b0077cfe1e78502e7ee5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491855
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2021-03-04 00:37:15 -08:00
mkumbar
65111b64f2 gpu: nvgpu: Add RISCV LS PMU support 
-Add RISCV LS PMU support by adding RISCV LS PMU ucode to the blob.
-Modify the PMU RTOS sequence based on NEXT CORE enable flag.

JIRA NVGPU-6303

Change-Id: I4e2b989f9903b72a6327c931eb3c02f8cef2aa75
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2447388
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 2020-12-17 18:36:44 -06:00
Ramesh Mylavarapu
5c08fd5801 gpu: nvgpu: update pmu ucode version for next pmu 
Update pmu ucode version for next pmu to 29323513.
This version is taken from P4 CL#29323216.
Changes:
- Enabled ACR task support
- Disabled few features/code for commands to work
- ELPG fifo preemption hals fixed
- Halt functions in ELPG save and restore functions
  are commented as bloaded flag is not getting set. This
  is not significant as this change will not have any impact
  in elpg functionality.

P4 ToT CL on which above change was made: P4 CL#29322732
P4 CL link: https://p4sw-swarm.nvidia.com/changes/29323216

Bug 200666202

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I34581cc15889463fa363cffb369485171c603247
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2447234
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 2020-12-15 14:13:48 -06:00
mkumbar
8c402095db gpu: nvgpu: PMU NS bootstrap on next core 
PMU NEXT profile NS ucode load and bootstrap on next core

JIRA NVGPU-5215

Change-Id: I0d8f2ae7695d1d2fc830c4f6b324490d844adabe
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2411320
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 2020-12-15 14:13:28 -06:00
Deepak Nibade
3b746dce0c gpu: nvgpu: use a falcon flag instead of enabled bit 
common.gr unit right now makes use of a capability bit
NVGPU_PMU_FECS_BOOTSTRAP_DONE to ensure the recovery path hits a
different routine. This is actually needless and a common check
cannot be used for all GR instances anyways.

Delete this capability bit. Add and use a new flag
coldboot_bootstrap_done added under struct nvgpu_gr_falcon

Jira NVGPU-5648

Change-Id: I46faea6f07cf054f17a3215d4cbbe0fc8a6382ae
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2409533
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 2020-12-15 14:13:28 -06:00
rmylavarapu
d0c01fc14c gpu: nvgpu: Support ELPG feature on nvgpu-next 
Changes:
 -Implemented pg init_send ops for legacy chips.
 -Implemented RPC response handler.
 -Added pg rpc function call macros for nvgpu-next.

NVGPU-5192
NVGPU-5195
NVGPU-5196

Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: I4e99d3929d7db796434aaeaa6f5773e9aac9fd32
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2391029
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 2020-12-15 14:13:28 -06:00
rmylavarapu
4787220ffe gpu: nvgpu: Create ELPG cmd functions 
In nvgpu-next ELPG unit support RPC calls and no
longer support command calls to communicate to PMU.
This change will create separate ELPG command
functions which can be called for legacy chips and
can be replaced by RPC functions for nvgpu-next chip.

NVGPU-5195

Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: Iddea0f46eb3506a4f2d44d664f610215b8f1b666
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2386923
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 2020-12-15 14:13:28 -06:00
rmylavarapu
641cc6a59c gpu: nvgpu: Support Perfmon events for nvgpu-next 
Created Perfmon events handling for nvgpu-next.
Nvgpu-next pmu send perfmon events in the form of
rpc events. Events are:
- Change event: This gives information of whether
  it is increase/decrease event.
- Init event: This gives information of perfmon init
  done in PMU.

NVGPU-5202
NVGPU-5205
NVGPU-5206

Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: Ida7e77dbaf70d2b594a0801c91a168dcb4a860bd
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2395358
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 2020-12-15 14:13:28 -06:00
rmylavarapu
1aa64ba899 gpu: nvgpu: Check for pmu dmem alloc/free 
On nvgpu-next all cmd/msg communication happens on
fbq and pmu dmem allocation is not needed. An extra
conditional check for pmu dmem alloc/free which will
avoid null pointer handling error.

NVGPU-5185

Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: I003a754ee7e91cc5d18a73576dd775a444b72d6d
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2395747
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 2020-12-15 14:13:28 -06:00
mkumbar
07bed63377 gpu: nvgpu: PMU ucode version update for nvgpu-next 
Updating PMU ucode version for nvgpu-next
Made below changes to PMU ucode on top P4 CL #28892402

-Enabled ACR task support
-Enabled PERFMON task support
-Disabled some features/code to build and commands work correctly
-Enabled INIT_APERTURE_SETTINGS feature
-ACRLib changes for ACR task

JIRA NVGPU-5180

Change-Id: Idc6975e2b7f3501fd377d7e99d8fb47adcb78a52
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2396641
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 2020-12-15 14:13:28 -06:00
mkumbar
3cc0dec8e7 gpu: nvgpu: update pmu init ack to support new unit id 
Added new command management unit id which will be received
as INIT ack from PMU ucode upon boot,
For legacy chips its called as INIT id, now changed to command
management id to initialize the command/message setup.

JIRA NVGPU-5185

Change-Id: I85203b373cef032f75b053b903d8b6763585be1f
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2396450
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 2020-12-15 14:13:28 -06:00
mkumbar
880a639a86 gpu: nvgpu: skip simulation check for pmu-lsfm unit 
skip simulation check for pmu-lsfm unit as lsfm unit execution
is required on simulation to support secure boot of ctxsw.

JIRA NVPU-5200

Change-Id: I85b8896643551e782b59663b13c52df36169754c
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2396449
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 2020-12-15 14:13:28 -06:00
mkumbar
b9ce3d50fc gpu: nvgpu: pmu: Add new command line args for nvgpu-next 
Added new command line args for nvgpu-next and made
required changes to support new args

JIRA NVGPU-5185

Change-Id: I26faa3b8498387421b798b7abf9e757ed188f7f4
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2396494
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 2020-12-15 14:13:28 -06:00
mkumbar
e6c9c30b32 gpu: nvgpu: Add PMU ucode version for nvgpu-next 
Adding PMU ucode version for nvgpu-next
chips_a P4 CL#: 28820694

JIRA NVGPU-5183

Change-Id: Id70bec5ad1422cce5fc0b0081f4d5924a4a15e09
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2378149
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 2020-12-15 14:13:28 -06:00
mkumbar
72e2f2e064 gpu: nvgpu: PMU NS ucode blob update 
Created PMU fw ops to support mutliple version of PMU NS
boot blob creation as there is a pmu_ucode_desc interface
change between legacy and new interface.
Added pmu_ucode_desc_v1 interface to support igpu PMU on
nvgpu-next

JIRA NVGPU-5183

Change-Id: I9f132aa84681d78b05b03913c71a30dda08053f8
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2377832
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 2020-12-15 14:13:28 -06:00
mkumbar
918fa1a658 gpu: nvgpu: PMU NS ucode boot update 
Removed gpmu_ucode.bin usage by fetching PMU ucode descriptor
and image from respective files for NS boot.

JIRA NVGPU-5183

Change-Id: I597c5dd17b4a58603f550b32980d7d0ca9624aed
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2376448
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 2020-12-15 14:13:28 -06:00
mkumbar
3f75e62c26 gpu: nvgpu: update super surface for igpu 
Add supper surface gpu_va details to super surface header member
as needed by PMU ucode to process.
This is required for iGPU PMU ucode on nvgpu-next to process command
line args and ACK back with INIT message, without this PMU ucode ends
up in hang due to DMA wait.
Update super-surface details to cmd line args for PMU ucode to
know the starting address of super-surface in SYSMEM.

JIRA NVGPU-5186

Change-Id: I56d7d3e28527e46707663c97bc8e2a58000c7f5a
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2376364
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 2020-12-15 14:13:28 -06:00
mkumbar
e6a3540ec1 gpu: nvgpu: support nvgpu-next for PMU on iGPU 
Support lsfm, perfmon and PG for iGPU PMU on nvgpu-next

JIRA NVGPU-5183

Change-Id: Idbe1125c2a8f347de3f59c4ec824df9600573e7a
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2376321
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 2020-12-15 14:13:28 -06:00
Shashank Singh
71c8d998d4 gpu: nvgpu: return error if therm is uninitialized 
If therm is not initialized then return error for getting temperature
API.

Bug 200638833
Jira NVGPU-5832

Change-Id: Iebe44218d76d39d5bf765e8de6fd74c3b64c8b68
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2382905
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 2020-12-15 14:13:28 -06:00
mkumbar
59230fe64a gpu: nvgpu: disable PMU PSTATE support if LS PMU disabled 
disable PMU PSTATE support if LS PMU support is disabled.

JIRA NVGPU-5474

Change-Id: Idc2d9d802473f0b3d898fddbdf4aead9d68285c9
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2365591
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 2020-12-15 14:13:28 -06:00
Abdul Salam
d339d9ed33 gpu: nvgpu: segregate clk_mon from clk unit. 
As a part of refactoring this CL removes clk_mon unit from
clk unit.
Clk_mon is used for monitoring of clk and it is an independent unit.
This patch does the following.
*Move the clk_mon struct from clk.h to clk_mon_tu104.h
*create a new clk_mon gpu_ops and assign clk_mon specific ops there.
*Move all the function to clk_mon_tu104.c
*Update the yaml file

NVGPU-4689

Change-Id: Ia72bf28a93ce9a7936c277076f365c4b6593b032
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336230
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 2020-12-15 14:13:28 -06:00
Abdul Salam
97de1ba74d gpu: nvgpu: Use unified struct to store slave freq 
Instead of using multiple struct use a single nvgpu_clk_slave_freq
to store the slave freq of gpcclk.
With this patch single struct can be used by both clk_arb and clk_domain.
This will remove nvgpu_set_fll_clk struct as nvgpu_clk_slave_freq serves
the purpose.

NVGPU-4692

Change-Id: Ie45d63e4376b83e153a9aa75e2c4631c6dad857b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339213
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 2020-12-15 14:13:28 -06:00
rmylavarapu
700bd83b41 gpu: nvgpu: Rename/clean boardobj unit 
-Removed unwanded boardobj includes
-Renamed functions as struct as per usage

NVGPU-4484

Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: I792a4b64075d5e87f911c1073717dbe7107227a1
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335991
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 2020-12-15 14:13:28 -06:00
rmylavarapu
8e545ef04b gpu: nvgpu: Fix boardobj allocation size 
In current implementation we are allocating boardobj
in nvgpu_boardobj_construct_super for all units and assigning
that pointer to boardobj type, as the size differe for different
units assigning the boardobj pointer to a common type will
give violations. Fixing them by allocating mem a head
and later call construct_super for elements initialization.

NVGPU-4484

Change-Id: I9b5ed1a6d8418fec48a29eee38d55fc7d83fcfab
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335989
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 2020-12-15 14:13:28 -06:00
rmylavarapu
0115c26f1b gpu: nvgpu: Boardobj lite unit refactor 
As boardobj unit is used only in PMU, the plan is to move
all the boardobj related functions/structures and Macros
to boardobj specific folders. This will remove unnecessary
usage of boardobj outside PMU.

NVGPU-4484

Change-Id: I9f0fda32e6affd1fce218eb0ac638a9dfc8b99c3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335986
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 2020-12-15 14:13:28 -06:00
Abdul Salam
076c85f813 gpu: nvgpu: Move clk_pmu struct from public include to unit include 
As a part of refactoring move nvgpu_clk_pmupstate from public to
private include.
Also remove all function pointers from the struct and use functions
as only single pstate is supported.
This function pointers were created to address multiple pstate support
which no more needed now.

NVGPU-4690

Change-Id: Iee556feed4a25902faba87a606418861185e4089
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2334826
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 2020-12-15 14:13:28 -06:00
Abdul Salam
88d3640bc5 gpu: nvgpu: Refacotor clk_domain Unit 
As a part of refactoring this patch does the following
*Move local struct to unit specific header file
*Move nvgpu_pmu_clk_domain_freq_to_volt from clk.c to
clk_domain.c
*Move PMU specific struct to ucode_clk_inf.h
*Merge content from nvgpu/clk.h to pmu/clk/clk.h
*Update yaml file
This will help to have arch consistency across all units.

Change-Id: Ied5c6ee637e7fd5bbdee3f5bc3f6cf216454428a
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333366
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 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
c060e754fc gpu: nvgpu: ELPG dump stats at shutdown 
ELPG_DISALLOW command fails during gk20a shutdown.
It was due to nvgpu_can_busy() which was returning
0 before without acknowledging the ELPG_DISALLOW
command.

Since the system is shutting down so fix this issue
by setting the ACK for disallow command without
waiting for actual ACK from PMU.
In doing so the state machine is also maintained
properly and the driver does not dump fail stats.

BUG 200588696

Change-Id: I943d8e6108fa0f9c418ccb1a7f061307823f1ec6
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308557
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Abdul Salam
af3311ddea gpu: nvgpu: Refactor clock_domain unit 
As a part of refactoring move nvgpu_clk_domain struct from public
to private.
This will help to have arch consistency across all units.
Use public functions to fetch the data across other units.
The following functions are added to access data in clk_domain unit.
*nvgpu_pmu_clk_domain_get_f_points()--> To get freq points
*nvgpu_pmu_clk_domain_update_clk_info() --> To update change seq script
with clock domain data

NVGPU-4689

Change-Id: Idc85e3cf5bbe1b80766ce6c9f07b3305ef04cbdc
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332185
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
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 2020-12-15 14:13:28 -06:00