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Author SHA1 Message Date
Philip Elcan
8f25fe41e2 gpu: nvgpu: mm: fix CERT-C STR30 violation in mmu_fault 
Fix CERT-C Rule STR30 violation for assigning string literal to
non-const pointer by changing the declaration.

JIRA NVGPU-3628

Change-Id: I804cf2e02c40b934a1575faa68a0cc3849927699
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133798
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 14:16:50 -07:00
Adeel Raza
f2dea4e8fc gpu: nvgpu: unit: add VM batch subtest 
Add a subtest to exercise the VM unit's batch mode. Batch mode is used
to optimize cache flushes.

JIRA NVGPU-3626

Change-Id: I4873d65f3fab48b11e998158669a26ad2e530dd1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 12:14:37 -07:00
Thomas Fleury
4d6aafe280 gpu: nvgpu: unit: stub l2_flush for channel setup bind 
Stub g->ops.mm.l2_flush for channel setup bind, as calling HALs
is failing in GVS. This does not affect branch coverage for
this unit test.

Bug 2621189

Change-Id: I3a286f8d09456fe94c661d4be7140791a5ddca61
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134652
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 09:45:41 -07:00
Seshendra Gadagottu
bf68ff68f0 gpu: nvgpu: fix CERT-C errors in hal.ltc.intr driver 
Fixed CERT-C issues in hal ltc intr driver by replacing
arithmetic operations with nvgpu safe ops.

JIRA NVGPU-3623

Change-Id: I80c3dd9e42dd20bb853db6e60d6a1fd36415ab36
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134686
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 05:08:29 -07:00
Seshendra Gadagottu
330bf3ac2a gpu: nvgpu: fix CERT-C errors in hal ltc driver 
Fixed CERT-C issues in hal ltc driver by replacing
arithmetic operations with nvgpu safe ops.

JIRA NVGPU-3623

Change-Id: I05c9cf202b46c39997e77d006ac5930f5cee9cd7
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134685
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 05:08:19 -07:00
rmylavarapu
ebc0b3b381 gpu: nvgpu: Remove hardcoding related to Psate objs 
In P4 #25076323, we have done many hard codings in PMU
which are related to Pstate board objs. As we are sending
Pstate objs now we can remove those hardcoding in NVGPU.

NVGPU-3597

Change-Id: I8b35e6b34c71721bb84fde9ffc280cf748232dbf
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131350
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 00:46:42 -07:00
Petlozu Pravareshwar
cebf5ea159 gpu: nvgpu: release nvgpu endpt minion fw 
Release nvgpu nvlink endpt minion fw after minion
has loaded and booted successfully. This fixes
the kernel memory leak.

Bug 200448597

Change-Id: Ia15a0941275101a9713ad5c4210e0e316a080c2e
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130388
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 00:46:26 -07:00
rmylavarapu
b38f261981 gpu: nvgpu: Implement Pstate Board objs 
Implemented parsing and sending performance table to pmu in
form of Pstate board objs under Perf_pstate unit.

NVGPU-3472

Change-Id: If8cc6373d1a03dd8f40a93a36203fa3d7127913f
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115564
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 00:45:43 -07:00
Divya Singhatwaria
5eab914e34 gpu: nvgpu: Fix MISRA violation in ACR safety code 
- Fix directive 4.7 violation
  Test the return value "err" of the function.

- Fix Rule 16.1 and 16.3 MISRA violations
  Add break-statement in "default" case.

JIRA NVGPU-3571

Change-Id: I57b098361ecefe6b69061063d1f52cda88fced18
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134182
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 22:28:24 -07:00
ajesh
a6cbfca58c gpu: nvgpu: fix MISRA violations in bitops unit 
Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset.  OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.

Jira NVGPU-3545

Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 22:26:41 -07:00
Alex Waterman
57cee55ce7 Revert "gpu: nvgpu: fix CERT-C errors in hal ltc driver" 
This reverts commit 98f27acf08.

Second part of the series of changes that went in and caused problems
for GVS.

Change-Id: I47e65195d2f4dcbc07f429db77a5c45190693adf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134478
 2019-06-11 10:50:18 -07:00
Alex Waterman
9d00bea358 Revert "gpu: nvgpu: fix CERT-C errors in hal.ltc.intr driver" 
This reverts commit bf861813b7.

This seems to cause a unit test failure in GVS due to a missing channel
test run.

Change-Id: I8609ebf8862a9641b015a7a2c0693e58312ef31d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134477
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
 2019-06-11 10:50:00 -07:00
Vinod G
a6b1725b04 gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.intr unit 
Fix CERT INT30-C erros in hal.gr.intr unit.
Unsigned integer operation may wrap. Use safe_ops macro to fix
the wrap errors.

Jira NVGPU-3585

Change-Id: If806b0e9e54c118dba6808a9c73ff107797d3ee0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134074
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 09:48:04 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags 
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 09:46:24 -07:00
Antony Clince Alex
cc3b0467db gpu: nvgpu: add missing type cast's to safe_ops.h 
Add the following type cast operations.
- nvgpu_safe_cast_u64_to_s32
- nvgpu_safe_cast_u64_to_s64
- nvgpu_safe_cast_s64_to_s32

JIRA NVGPU-3485

Change-Id: I454bace8d65f6c0e65adfc722eae66fa55c6dc8f
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128466
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 09:46:09 -07:00
Vinod G
1daaf83dce gpu: nvgpu: Fix CERT ARR37-C errors in common.gr.ctx unit 
Cert_arr37_c_violation: Using arithmetic operator on address which
points to non-array object.
Assign all pointer operands to array's 0th index address.

Jira NVGPU-3585

Change-Id: I59c213ed6d17d2bfb6f58c649a1ec151fba2c72b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133863
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 05:06:06 -07:00
Vinod G
c3c541b1af gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.ecc unit 
Fix CERT INT30-C erros in hal.gr.ecc units.
Unsigned integer operation may wrap. Use safe_ops macro to fix
the wrap errors.

Jira NVGPU-3585

Change-Id: I3811bfe0c542e7960ab8dbc2877465f7a72d1761
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133803
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 05:05:57 -07:00
Vinod G
fb0e627a25 gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.config unit 
Fix CERT INT30-C erros in hal.gr.config units.
Unsigned integer operation may wrap. Use safe_ops macro to fix
the wrap errors.

Jira NVGPU-3585

Change-Id: I67f4df491194f1c5fdb369956f8238cd64cb85f1
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132651
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 05:05:30 -07:00
Seshendra Gadagottu
bf861813b7 gpu: nvgpu: fix CERT-C errors in hal.ltc.intr driver 
Fixed CERT-C issues in hal ltc intr driver by replacing
arithmetic operations with nvgpu safe ops.

JIRA NVGPU-3623

Change-Id: I4203e7bdd02c41578cad8446f02247749c8cef5c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133291
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 03:55:33 -07:00
Seshendra Gadagottu
98f27acf08 gpu: nvgpu: fix CERT-C errors in hal ltc driver 
Fixed CERT-C issues in hal ltc driver by replacing
arithmetic operations with nvgpu safe ops.

JIRA NVGPU-3623

Change-Id: I0c6840ac1ee174c509e14e18e89cbacb0fdb650b
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133290
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 03:55:25 -07:00
Thomas Fleury
7bb278454f gpu: nvgpu: unit: use 'ret' for return code 
Use 'ret' for return code, as 'rc' somehow maps to recovery

Jira NVGPU-3480

Change-Id: I31e0f3f30a9d6e4036a15e400acd71cb3a9bdfa7
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132495
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 19:46:43 -07:00
Thomas Fleury
3136ad6a5b gpu: nvgpu: unit: add channel enable/disable tsg test 
Add unit test for the following functions:
- nvgpu_channel_enable_tsg
- nvgpu_channel_disable_tsg

Jira NVGPU-3480

Change-Id: I99dc24cb2089da8105cd66f3172984c49861a2e9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129728
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 19:46:24 -07:00
Thomas Fleury
9f9909fba8 gpu: nvgpu: unit: add channel ref from inst test 
Add unit test for the following functions:
- nvgpu_channel_refch_from_inst_ptr
- nvgpu_channel_from_id
- nvgpu_channel_from_id__func

Jira NVGPU-3480

Change-Id: I04bffff7edc006ff5d822aa433684f93d5613a83
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129727
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 19:46:09 -07:00
Thomas Fleury
99db6a6d3f gpu: nvgpu: unit: add channel alloc/free inst tests 
Add coverage for the following functions:
- nvgpu_channel_alloc_inst
- nvgpu_channel_free_inst

Jira NVGPU-3480

Change-Id: I754dccee69dfe04d5ae5607ad1deb6dd8c8de79f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129726
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 19:45:54 -07:00
Thomas Fleury
5dbf0675f4 gpu: nvgpu: unit: add channel setup_bind tests 
Add coverage for the following functions:
- nvgpu_channel_setup_bind
- nvgpu_channel_setup_usermode

Jira NVGPU-3480

Change-Id: I0814928851bb42a05402d3e99a66d30bd44cb0e6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129725
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 19:45:40 -07:00
Thomas Fleury
0624d908cd gpu: nvgpu: unit: add channel close tests 
Add branch coverage for:
- nvgpu_channel_kill
- nvgpu_channel_close

Also, modified gk20a_free_channel as follows:
- use nvgpu_assert to check ch->g (so that it can be tested)
- make sure g is non-NULL before calling nvgpu_get_poll_timeout

Jira NVGPU-3480

Change-Id: Ie1fa231b022da47b9ef9022ae67a6b3d73c28a8b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129724
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 19:45:17 -07:00
Thomas Fleury
1eef4eaae5 gpu: nvgpu: unit: add channel open tests 
Add unit test for:
- gk20a_channel_open_new

Jira NVGPU-3480

Change-Id: I50d8cef746aa532712c94a3806822f5f0c7f435f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129723
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 19:45:03 -07:00
Thomas Fleury
d2d7922411 gpu: nvgpu: unit: add channel setup_sw/cleanup_sw 
Add unit test for:
- nvgpu_channel_setup_sw
- nvgpu_channel_cleanup_sw

Jira NVGPU-3480

Change-Id: Ic691b7fa17f97022fd7d4905377f9a348d8ecae8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129722
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 19:44:53 -07:00
Vinod G
f4b8feccf5 gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.init unit 
Fix CERT INT30-C erros in hal.gr.init units.
Unsigned integer operation may wrap. Use safe_ops macro to fix
the wrap errors.

Jira NVGPU-3585

Change-Id: I1c825decfbfba52136aef55c791e3d328a3470a2
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132617
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 11:34:47 -07:00
Vinod G
0c13e9e8ad gpu: nvgpu: Fix CERT INT30-C errors in common.gr 
Fix CERT INT30-C erros in common.gr units

Unsigned integer operation may wrap. Use safe_ops macro
to fix the wrap errors.

Jira NVGPU-3585

Change-Id: I76127d8d58e1b5516370e78432754a7e7091e7be
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132588
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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 2019-06-10 07:48:58 -07:00
Thomas Fleury
7e890f4285 gpu: nvgpu: unit: use 'ret' for return code 
Use 'ret' for return code, as 'rc' somehow maps to recovery

Jira NVGPU-3476

Change-Id: Ife862ca5b049044adee69384ee805cd2271c0679
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132490
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2019-06-09 22:56:42 -07:00
Thomas Fleury
7ccf26b92c gpu: nvgpu: unit: update required tests 
Update required tests with tsg tests.

Jira NVGPU-3476

Change-Id: I116e43bb8b5b2ac3701a638352993ca8dddeeeb0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131757
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2019-06-09 22:56:06 -07:00
Thomas Fleury
f980c859e9 gpu: nvgpu: unit: cover more tsg open branches 
Add branch coverage for:
- nvgpu_tsg_alloc_sm_error_states_mem

Jira NVGPU-3476

Change-Id: Ifca5b5f512536c609c11fc317d28704380a73a58
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124514
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2019-06-09 22:55:27 -07:00
Thomas Fleury
6602baaf41 gpu: nvgpu: unit: add tsg setup_sw/cleanup_sw coverage 
Add unit test for:
- nvgpu_setup_sw
- nvgpu_cleanup_sw

Made nvgpu_tsg_init_support return void, since it cannot fail.

Jira NVGPU-3476

Change-Id: Ifff115e98c097375d7920b79ae9e13657d54a357
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124512
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2019-06-09 22:55:18 -07:00
Vinod G
8db47e6f51 gpu: nvgpu: Add utils.h to YAML arch 
Move all definitions and functions other than type defines from types.h
to new header utils.h for posix.
Update files that use functions and defintions from utils.h

Jira NVGPU-3411

Change-Id: I6d9b165f882282450d4b35f4d6a0200effe76791
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130529
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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 2019-06-07 17:05:41 -07:00
Vinod G
4201f58e1e gpu: nvgpu: Add utils header for posix 
Move all definitions and functions other than type defines from types.h
to new header utils.h for posix.
Update files that use functions and defintions from utils.h

DIV_ROUND_UP macro is updated to use safe_ops.h calls to handle
the CERT-C wrap issues.

Jira NVGPU-3411

Change-Id: I9da3e9f255f39949287c615519f062fd8816aa04
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130453
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2019-06-07 17:05:23 -07:00
Philip Elcan
60c3be3ca9 gpu: nvgpu: mm: fix CERT-C INT32 violations in page_allocator 
CERT-C Rule INT32 requires checking that signed values do not wrap when
doing arithmetic operations. The INT32 violations in page_allocator were
actually unsigned values, so change them to u32 and use safe ops.

JIRA NVGPU-3586

Change-Id: I7c7fbf52c2f55a9d47d86c2b01be0ab222d3d65e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131160
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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 2019-06-07 09:06:04 -07:00
Philip Elcan
fbbfc9717f gpu: nvgpu: mm: fix CERT-C INT31 violations in page_allocator 
CERT-C Rule INT31 requires checking that no data is lost when doing
casts, so use the safe cast operations in page_allocator.c

JIRA NVGPU-3586

Change-Id: I0cf0de7eda0c117a65a08930dbc70f9c699a0219
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131159
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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 2019-06-07 09:05:55 -07:00
Philip Elcan
0a645e66ee gpu: nvgpu: mm: fix CERT-C violations in page_allocator 
CERT-C Rule INT30 requires checking for values wrapping when doing
arithmetic operations on unsigned values. Use the safe ops or asserts to
ensure unsigned arithmetic operations will no wrap.

JIRA NVGPU-3586

Change-Id: Ia1fc05711520135e788023e0614c70778c076f6a
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131158
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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 2019-06-07 09:05:46 -07:00
Philip Elcan
be7c7aa040 gpu: nvgpu: posix: make round*_pow_of_two CERT-C friendly 
CERT-C Rule INT30 requires checking unsigned arithmetic for potential
wrap. The macros roundup_pow_of_two and rounddown_pow_of_two could
potentially wrap if the passed parameter were 0.

JIRA NVGPU-3586

Change-Id: I9eba4c197b74db555055e1199ce72131b071062c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131157
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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 2019-06-07 09:05:37 -07:00
Thomas Fleury
7eb8ea9764 gpu: nvgpu: unit: add tsg abort coverage 
Add unit test for:
- nvgpu_tsg_abort

Jira NVGPU-3476

Change-Id: Ie1d93647e8ab239ad0604b04a3d36464b2bedb5b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124515
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-07 03:27:32 -07:00
Thomas Fleury
2b3f005313 gpu: nvgpu: unit: add tsg unbind branch coverage 
Updated test to cover test where:
- update runlist fails during unbind
- tsg is aborted
- updated runlist fails during abort

Modified update runlist stub to return -EINVAL depending
on branch combinations.

Added custom pruning function to skip some impossible
combinations of non-final branches.

Jira NVGPU-3476

Change-Id: I23a64085239b4003b73873a984a301476d73d962
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124513
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2019-06-07 03:27:23 -07:00
Thomas Fleury
32aa15f9d4 gpu: nvgpu: unit: add tsg enable/disable coverage 
Add unit tests for
- g->ops.tsg.enable (gv11b_tsg_enable)
- g->ops.tsg_disable (nvgpu_tsg_disable)

Use an array to allow multiple stubs to store data.

Jira NVGPU-3476

Change-Id: I2afaef6d1ec4d74a05ec6e7952e5ead86c432f3d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123886
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2019-06-07 03:27:13 -07:00
Thomas Fleury
04cf2f1ba6 gpu: nvgpu: unit: add unit_assert helper 
Add unit_assert helper to check condition.
In case of failure, the macro reports failed condition as well as
line number, then runs bail out code.

Jira NVGPU-3476

Change-Id: I9971e7fa0337661d46a06dfa05b67a98e3c46eee
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129675
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-07 03:27:04 -07:00
Thomas Fleury
eb380fcbdb gpu: nvgpu: unit: tmake userspace build for tsg 
Added tmake userspace build for tsg
Added missing exports for libnvgpu-drv
Added tsg tests to required tests
Re-use fifo init/remove support

Jira NVGPU-3476

Change-Id: I5bcbbf5a9b58e825e1cad6aa5896de7e91fe7400
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128160
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2019-06-07 03:26:54 -07:00
Lakshmanan M
57170db65a gpu: nvgpu: fifo: Call os specific channel open only for kernel mode submit 
Restricted the os specific channel open only for kernel mode submit.
For linux, g->os_channel.open is just noop.
For QNX, nvgpu creates the sync point notifier thread for
job tracking. This job completion tracking is only required
for kernel mode submit. This sync point notifier thread
is not required for user mode submit.

JIRA NVGPU-2944

Change-Id: Ie37824aac3609090ef9da378202dbc211a2eb0b3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131386
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 2019-06-06 16:29:50 -07:00
Deepak Nibade
649a2b57a8 gpu: nvgpu: add debugger flag for hal.gr.gr unit 
Add NVGPU_DEBUGGER flag for common.hal.gr.gr unit and corresponding
hals.

Also add this flag for deferred reset functionality

Jira NVGPU-3506

Change-Id: Iee4fbc1305346bb4d779cd69e8fd5539cb07206b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130149
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 2019-06-06 16:28:44 -07:00
Deepak Nibade
d315f2a7e2 gpu: nvgpu: add debugger flag for perf units 
Add NVGPU_DEBUGGER flag for common.gr.perfbuf and common.hal.gr.perf
units

Jira NVGPU-3505

Change-Id: Ic01324304114e3fbaf018fd3bd892ccaa655b9ae
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130148
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 2019-06-06 16:28:29 -07:00
Deepak Nibade
c5f5eb896c gpu: nvgpu: add debugger flag for hwpm_map units 
Add NVGPU_DEBUGGER flag for common.gr.hwpm_map and
common.hal.gr.hwpm_map units

Jira NVGPU-3505

Change-Id: I5c9b6f98c7a8f536f5a8492febaa6140ef2adb6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130147
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 2019-06-06 16:28:14 -07:00
Deepak Nibade
455b0da253 gpu: nvgpu: add debugger flag for regops support 
Add NVGPU_DEBUGGER flag for regops API and hals

Jira NVGPU-3505

Change-Id: I9f2b850c881bf05f8ba5b6ef1f59f0d73a948cde
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130146
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-06 16:27:58 -07:00