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831 Commits

Author SHA1 Message Date
Konsta Hölttä
2077df9b1a gpu: nvgpu: use set_syncpt only with nvhost 
nvgpu_channel_set_syncpt() is not useful if nvhost and thus syncpts are
missing and semaphores are used for synchronization. Require
CONFIG_TEGRA_GK20A_NVHOST to be set for the set_syncpt hal.

Jira NVGPU-5496

Change-Id: Ief8b4a0fb29af631817aba55c04181b1a360ce56
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2344064
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 2020-12-15 14:13:28 -06:00
Seema Khowala
681077d578 gpu: nvgpu: volta+: convert SM broadcast to SM unicast 
Starting volta, multiple SMs are supported. Ctxsw regops
require SM broadcast registers to be converted to unicast registers.

Bug 2960720
JIRA NVGPU-5502

Change-Id: Id6e87fcc993587317bcd9b6958233e39d6b41fa7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340921
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 2020-12-15 14:13:28 -06:00
Seema Khowala
98886cd28e gpu: nvgpu: volta+: add litter value for SM UNIQUE_BASE & SHARED_BASE 
Starting volta, multiple SMs are supported. In order to convert
SM broadcast registers to unicast registers, sm_unique_base
and sm_shared_base are required.

Bug 2960720
JIRA NVGPU-5502

Change-Id: Ie9ebc0ab814cf551801f6cac1298a791d184f894
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340792
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
a039261724 gpu: nvgpu: add gr.process_context_buffer_priv_segment gops 
1. Add below gr gops to process context buffer's priv segment.
int (*process_context_buffer_priv_segment)(struct gk20a *g,
					 enum ctxsw_addr_type addr_type,
					 u32 pri_addr,
					 u32 gpc_num, u32 num_tpcs,
					 u32 num_ppcs, u32 ppc_mask,
					 u32 *priv_offset);
Update all chips to use gr_gk20a_process_context_buffer_priv_segment()
as new gr hal.
2. Add and use ppc, tpc and etpc count functions to retrieve total count.

Bug 2960720
JIRA NVGPU-5502

Change-Id: I6cec36c323ff49ded853cd5cbfd9e0a28602b8ed
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
d03883d09d gpu: nvgpu: do not use nvgpu_writel_check in gm20b_flush_ltc 
Replace nvgpu_wriel_check with nvgpu_writel to issue clean
and invalidate in gm20b_flush_ltc.

JIRA NVGPU-5490

Change-Id: I6e1e73136e93ff06396894e5ba855f30bc3403b0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
ee216bc941 gpu: nvgpu: add NVGPU_SUPPORT_COMPRESSION flag 
Add NVGPU_SUPPORT_COMPRESSION to indicate if compression feature is
supported in nvgpu. If not, set cbc.init, cbc.ctrl and
cbc.alloc_comptags hals to NULL.
Add corresponding GPU characteristics flag and IOCTL mapping to sync
compression support status with nvrm_gpu.

JIRA NVGPU-4666

Change-Id: I2e685688ddac592b3bb918ee70c82ea5524d695a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2338926
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
068e00749b gpu: nvgpu: update config_userd_writeback_enable 
Field value of pbdma_config_userd_writeback_enable is changing from
0x1 to 0x0 for nvgpu-next. So,
- Update config_userd_writeback_enable() hal to accept u32 value.
- Update config_userd_writeback_enable() hal to return modified
  value after setting pbdma_config_userd_writeback_enable field.

Jira NVGPU-5162

Change-Id: I94efa20c34bb867f185778c973bd52b86902b32c
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2330160
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
cd7194cbc0 gpu: nvgpu: modify gmmu page table entry functions 
Move below chip agnostic gmmu pte functions to common/mm/gmmu/pte.c.
- gmmu_aperture_mask()
- pte_dbg_print()

Default big page size for all chips is 64K. So, move
gp10b_mm_get_default_big_page_size() to common file and rename as
nvgpu_gmmu_default_big_page_size().

Modify gv11b_gpu_phys_addr() to use get_iommu_bit() hal.

JIRA NVGPU-4666

Change-Id: I512c42723faf2d03e5b367879c9c385dcf52cdc2
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
05df07945a gpu: nvgpu: avoid channel dependency in priv cmdbuf 
The priv cmdbuf queue needs only the vm_gk20a of the channel that owns
it. Pass the vm to the queue constructor and have the channel code store
the queue to itself instead of poking at the channel from the queue
code. Adjust the cmdbuf queue api to take the queue, not the channel.

Move the inflight job fallback calculation to the channel code. The size
of the channel gpfifo isn't needed in the queue; just the job count is.

[not part of the cherry-pick: a bunch of MISRA mitigations.]

Jira NVGPU-4548

Change-Id: I4277dc67bb50380cb157f3aa3c5d57b162a8f0ba
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329659
(cherry picked from commit 83b2276f7bea563602eee20ce24b70ce70c8475a)
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
b436877190 gpu: nvgpu: replace nvgpu_log with nvgpu_err for CE stall interrupts 
Replace nvgpu_log with nvgpu_err for ce stall interrupt messages.

Jira: NVGPU-5034

Change-Id: I794461431ec6fadc322fe05a4f53f619c5370052
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335702
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 2020-12-15 14:13:28 -06:00
Abdul Salam
88d3640bc5 gpu: nvgpu: Refacotor clk_domain Unit 
As a part of refactoring this patch does the following
*Move local struct to unit specific header file
*Move nvgpu_pmu_clk_domain_freq_to_volt from clk.c to
clk_domain.c
*Move PMU specific struct to ucode_clk_inf.h
*Merge content from nvgpu/clk.h to pmu/clk/clk.h
*Update yaml file
This will help to have arch consistency across all units.

Change-Id: Ied5c6ee637e7fd5bbdee3f5bc3f6cf216454428a
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333366
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 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
f0896f94e1 gpu: nvgpu: Add falcon gops 
Add falcon gops for accessing below constants. This is
required for nvgpu-next.

falcon_falcon_dmemc_blk_m
falcon_falcon_imemc_blk_f

JIRA NVGPU-4834

Change-Id: I1a60f473470a7a03fb31dceecfccd91fcc690de9
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
85b9c98eba gpu: nvgpu: init hal for nvgpu-next dgpu 
Add hooks for nvgpu-next dgpu init hal.

Jira NVGPU-5382

Change-Id: I5395a32ceda21b43b186756ba6dd5937251c3548
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
68caee196a gpu: nvgpu: add mm.mmu_fault.parse_mmu_fault_info gops 
Add mm.mmu_fault.parse_mmu_fault_info gops. This is required
for nvgpu-next.
Also add mmu_engine_id type in mmu_fault structure. This variable
will be set in parse_mmu_fault_info hal so that
gv11b_mm_mmu_fault_handle_other_fault_notify does not depend
upon any chip specific h/w header. This is needed because
BAR2 mmu engine id has changed in nvgpu-next.

JIRA NVGPU-5032

Change-Id: I0c5e9ef607aff5b105f59582013cbfb31396290a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Abdul Salam
af3311ddea gpu: nvgpu: Refactor clock_domain unit 
As a part of refactoring move nvgpu_clk_domain struct from public
to private.
This will help to have arch consistency across all units.
Use public functions to fetch the data across other units.
The following functions are added to access data in clk_domain unit.
*nvgpu_pmu_clk_domain_get_f_points()--> To get freq points
*nvgpu_pmu_clk_domain_update_clk_info() --> To update change seq script
with clock domain data

NVGPU-4689

Change-Id: Idc85e3cf5bbe1b80766ce6c9f07b3305ef04cbdc
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332185
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 2020-12-15 14:13:28 -06:00
Seema Khowala
aff5497907 gpu: nvgpu: add intr_unit_bitmask i/p param for fb.intr.isr 
tu104 onwards, fb interrupt status/enable/disable moved from
fb_niso_intr_* reg to fb_*vector* registers.
At the top level, fb interrupt status/enable/disable is done
using hub_intr bit in mc_intr registers.

Starting nvgpu-next, this has changed.

JIRA NVGPU-5032

Change-Id: Ib54170b055b83e2696312c811c2e3ba678749359
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
091e4b9396 gpu: nvgpu: detect enabled ecc units in hal init 
ECC scrubbing can start before GPU characteristics
are initialized. Detect enabled ECC units in HAL
init functions so that scrubbing is started properly.

Bug 2919887

Change-Id: Ic20b4223504a947eed78418779531e26c2116d41
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2330101
(cherry picked from commit e8d380d7bba91b895033ebb5ab0d281be6d3db30)
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 2020-12-15 14:13:28 -06:00
Tejal Kudav
25461c7621 gpu: nvgpu: Move nvlink HAL code to /hal 
Remove the nvlink register read/write code from /common.
Move the register handling code to /hal and add
HALs to to expose this functionality to common code.

JIRA NVGPU-2964

Change-Id: Iafba9f4e29cc0f1130dbf5dd14fbbf8b6b5bb8ec
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vinod G
bb93223a21 gpu: nvgpu: add check_warp_esr_error hal 
Set check_warp_esr_error hal pointer to
gv11b_gr_check_warp_esr_error hal function.

Jira NVGPU-4867

Signed-off-by: Vinod G <vinodg@nvidia.com>
Change-Id: Ib014c5ff2456836af2fe89f849f37991fe52844e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2331804
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Vinod G
8f3a0f4486 gpu: nvgpu: add sm rams ecc enabled flag 
Add sm rams ecc enabled flag.

Move ecc scrubbing timeout defines to
gr_init_gv11b.h

Jira NVGPU-4871

Signed-off-by: Vinod G <vinodg@nvidia.com>
Change-Id: Ie43f5947c53be697d0b2fd064d308612856d823a
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
4acf78dff3 gpu: nvgpu: guard sync cmd hals properly 
Make the syncpt and sema wait and incr command HAL ops consistent. Add
CONFIG_NVGPU_SW_SEMAPHORE guards for the semaphore ops. The syncpoint
ops already have CONFIG_TEGRA_GK20A_NVHOST around them.

Delete the dummy syncpt ops. They are not used; the ops are only needed
when the real versions exist.

Jira NVGPU-4548

Change-Id: I30315a67169b31b1d63a0a1a0a4492688db4a2bc
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325100
(cherry picked from commit ed13b286c5fbdbc008ec59172d98ac79e9f2e733)
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
39844fb27c gpu: nvgpu: hide priv cmdbuf mem writes 
Add an API to append data to a priv cmdbuf entry. Hold the write pointer
offset internally in the entry instead of having the user keep track of
where those words are written to.

This helps in eventually hiding struct priv_cmd_entry from users and
provides a more consistent interface in general. The wait and incr
commands are now slightly easier to read as well when they're just
arrays of data.

A syncfd-backed prefence may be composed of several individual fences.
Some of those (or even a fence backed by just one) may be already
expired, and currently the syncfd export design releases and nulls
semaphores when expired (see gk20a_sync_pt_has_signaled()) so for those
the wait cmdbuf is appended with zeros; the specific function is for
this purpose.

Jira NVGPU-4548

Change-Id: I1057f98c1b5b407460aa6e1dcba917da9c9aa9c9
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325099
(cherry picked from commit 6a00a65a86d8249cfeb06a05682abb4771949f19)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2331336
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 2020-12-15 14:13:28 -06:00
Tejal Kudav
5af8cedf05 gpu: nvgpu: Nvlink interrupt handling 
Enable logging and error reporting for MIF, DLPL, and TLC blocks.
Configure the NVLIPT and IOCTRL interrupt registers to rollup
the MIF and TLC errors on the link-specific fatal line and the
DLPL interrupts on link-specific intr_a(fatal) line. Both
link_err_fatal and link_intr_a are rolled up to stall interrupt line.
In the handling ISR, clear the interrupt status registers and print
an error.
Move the interrupt handling HAL code to /common/hal.

JIRA NVGPU-4350
JIRA NVGPU-4351
JIRA NVGPU-5231
JIRA NVGPU-4354
JIRA NVGPU-4355
JIRA NVGPU-4356

Change-Id: I14812499caf506592f3ae84d6681d857730d31ff
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313221
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
6202ead057 gpu: nvgpu: split sema sync hal to wait and incr 
Instead of one HAL op with a boolean flag to decide whether to do one
thing or another entirely different thing, use two separate HAL ops for
filling priv cmd bufs with semaphore wait and semaphore increment
commands. It's already two ops for syncpoints, and explicit commands are
more readable than boolean flags.

Change offset into cmdbuf in sem wait HAL to be relative to the cmdbuf,
so the HAL adds the cmdbuf internal offset to it.

While at it, modify the syncpoint cmdbuf HAL ops' prototypes to be
consistent.

Jira NVGPU-4548

Change-Id: Ibac1fc5fe2ef113e4e16b56358ecfa8904464c82
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323319
(cherry picked from commit 08c1fa38c0fe4effe6ff7a992af55f46e03e77d0)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328409
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 2020-12-15 14:13:28 -06:00
Vinod G
6a7bf6cdc0 gpu: nvgpu: update sm ecc_status_error handling 
Use gv11b_gr_intr_handle_tpc_sm_ecc_exception
function for future chip to avoid code replication.

Add sm_ecc_status_errors hal to read
the ecc_status_errors

Jira NVGPU-5033

Signed-off-by: Vinod G <vinodg@nvidia.com>
Change-Id: I4a25837d9b833a48307b9353b82ff6597f985e41
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325537
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
b3d16b23d5 gpu: nvgpu: extract priv cmdbuf from channel.c 
Move private command buffer related functionality to priv_cmdbuf.c. This
is used only for kernel mode submits, so it makes sense to group it out,
and the priv cmdbuf stuff is used also by things that don't care about
channels.

Jira NVGPU-4548

Change-Id: Idbb42e3ed3984e16c654bb9aa2b7564b780048a4
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323146
(cherry picked from commit bb67bfc7ab8e87236f31bc4f6c80dab042609f21)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328406
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
c6908922e5 gpu: nvgpu: move generic preempt hals to common 
- Move fifo.preempt_runlists_for_rc and fifo.preempt_tsg hals to common
source file as nvgpu_fifo_preempt_runlists_for_rc and
nvgpu_fifo_preempt_tsg.

Jira NVGPU-4881

Change-Id: I31f7973276c075130d8a0ac684c6c99e35be6017
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323866
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
5555b6db87 gpu: nvgpu: add isr_handle_0/1 priv_ring gops 
Add below hals to priv_ring gops. These hals are used from gp10b onwards.
- isr_handle_0
- isr_handle_1

Jira: NVGPU-4669

Change-Id: I95aaebfd4c9c292b7b0da98cd34ac2a8472a5e1d
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318245
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 2020-12-15 14:13:28 -06:00
Vinod G
0e0b966f0c gpu: nvgpu: update gr exception hal 
Make generic gr exception static functions
to public functions.

Jira NVGPU-5033

Signed-off-by: Vinod G <vinodg@nvidia.com>
Change-Id: I9ac4cbc728edda813a487f80af622559a798b319
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2324676
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 2020-12-15 14:13:28 -06:00
Vinod G
340ea241cb gpu: nvgpu: remove channel debug_dump hal 
Channel debug_dump hal function does not involve
any register related code.

Move gv11b_channel_debug_dump hal function to
common code nvgpu_channel_info_debug_dump function.

Check gpu hw version to limit instance variables
dump that differs between socs.

Add new hal pointer syncpt_debug_dump for pbdma.

Jira NVGPU-5109

Signed-off-by: Vinod G <vinodg@nvidia.com>
Change-Id: Icfca837ce8e4117387cffa6fadf6c094c7da5946
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321016
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 2020-12-15 14:13:28 -06:00
Debarshi Dutta
f483304238 gpu: nvgpu: add prerequisite for syncpoint-shim support 
add check for nvgpu_has_syncpoints() before enabling syncpoint-shim and
usermode_syncpoint support. Syncpoint shim cannot exist without
syncpoint support in the first place.

Bug 200551105

Change-Id: I2a9c6d23c72a25bcac4a2a8737ed0bad14cd4d8f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323208
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
675fb39ca0 gpu: nvgpu: add runlist.init_enginfo hal 
Add runlist.init_enginfo hal to initialize
runlist's engine info. nvgpu-next has it's own
implementation for init_enginfo hal, so removed
NVGPU_NEXT_INIT_RUNLIST_ENGINFO from nvgpu hals.

JIRA NVGPU-4979

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Ie35a88c6ba3c7c741124386f7c643b36b42d4143
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319103
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
2f6be2735e gpu: nvgpu: remove nvgpu-next gr init 
nvgpu-next gr init is handled within nvgpu-next
hals. So remove references to NVGPU_NEXT_INIT_GR_INFO from
nvgpu hals.

JIRA NVGPU-4979

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I2e493220f855a7ff2f940cf07b1fc0b876601df5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319102
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Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
44f12288ad gpu: nvgpu: add mc.reset_engine hal for nvgpu-next 
Engine reset process has changed for nvgpu-next. Add mc.reset_engine
gops for nvgpu-next.
Modify engine reset functions to use mc.reset_engine hal.

Jira NVGPU-5145

Change-Id: I176800212042eaef71c8cbd4bc499805c5af0e60
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2312485
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
d0ffb335dc gpu: nvgpu: move nvgpu_has_syncpoints 
nvgpu_has_syncpoints is more general than a channel synchronization
related, so move it to nvhost.c from channel_sync.c. Move the
declaration from gk20a.h to nvhost.h.

As the debugfs knob is Linux related, move it from struct gk20a to
struct nvgpu_os_linux.

Jira NVGPU-4548

Change-Id: I4236086744993c3daac042f164de30939c01ee77
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318814
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
db9c1b1f97 gpu: nvgpu: don't build sw semas for dgpu 
Make tu104's sema cmd HAL ops depend on CONFIG_NVGPU_SW_SEMAPHORE
in addition to the kernel mode submit flag.

Drop CONFIG_NVGPU_SW_SEMAPHORE from NVGPU_FORCE_DGPU_SAFETY_PROFILE.
Semaphore-based synchronization is not actually needed for dgpu.

Jira NVGPU-4548

Change-Id: I3fe066dbeb68295dfc4bbe09256ff6a20c892c2f
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318737
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
88c774e5d1 gpu: nvgpu: enable clk_arb for dGPU safety 
Enable CONFIG_NVGPU_CLK_ARB for dGPU safety build.

Use CONFIG_NVGPU_NON_FUSA for invocation of non-safe functions:
- nvgpu_hr_timestamp
- nvgpu_hr_timestamp_us

Jira NVGPU-4661
Jira NVGPU-5235 (for addressing usage of above functions).

Change-Id: I271fdbc45c1e4d01cb70d50dcf63d15b9df33c76
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317842
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
25edcc1353 gpu: nvgpu: cta preemption mode HAL for tu104 
Use gp10b_ctxsw_prog_set_compute_preemption_mode_cta instead
of gm20b_ctxsw_prog_set_compute_preemption_mode_cta for tu104.

Jira NVGPU-4661

Change-Id: I7b85cbcc139e6843c8b7bd89e0afb6030160362f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316206
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
28ccd63f69 gpu: nvgpu: enable CONFIG_NVGPU_LS_PMU for safety 
Enable CONFIG_NVGPU_LS_PMU for dGPU safety build.
Add missing #ifdefs for CONFIG_NVGPU_POWER_PG and
CONFIG_NVGPU_CLK_ARB which are not defined for safety build.

Moved gm20b_mc_is_enabled to fusa code.

NVGPU_UNIT_PWR is only defined when CONFIG_NVGPU_HAL_NON_FUSA
is defined. Added #ifdefs to compile out gk20a_pmu functions
that are using it.

Jira NVGPU-4661

Change-Id: Ieb552f9374bad6f3dad777322f118931e0bc94ec
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317085
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
da8ee8d615 gpu: nvgpu: add therm_max_fpdiv_factor gops.therm 
Use therm_max_fpdiv_factor gops.therm for nvgpu-next to get the maximum
fp_div_factor.

Jira NVGPU-4860

Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Change-Id: If0e9b82f5b61289e226ceeff386fc88763af66e2
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313336
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 2020-12-15 14:13:28 -06:00
Abdul Salam
4f5bd9e633 gpu: nvgpu: Implement clk_good and pll_lock check 
Add clk_good and pll_lock check as a part of fmon polling.
This will poll for any clock related faults at FTTI interval.
Add new function to poll for vbios init completion.

NVGPU-4967
Bug 2849506
Bug 200564937

Change-Id: I5bc885329981e07376824e148edabe9be4120e1c
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2305782
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 2020-12-15 14:13:28 -06:00
sagar
b8a3e54dda gpu: nvgpu: add invalid ctxsw method 
* For ctxsw negative testing, nvgpu need to send and invalid method
 * Sending 0xFFFF method will result in triggering ctxsw error intr.

JIRA NVGPU-5080

Change-Id: I6c16137d86ee2ddb25f1508161d9d6befcbcbefe
Signed-off-by: sagar <skadamati@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
f43d5df83a gpu: nvgpu: build dGPU in safety 
Enable build flags for dGPU in safety, when
NVGPU_FORCE_DGPU_SAFETY_PROFILE is set.

Use libnvgpu-dgpu_safe.exports for dGPU safety build.

Add build flags for tu104 HAL initialization (to solve
undefined symbols in safety build).

Temporarily add non-fusa files needed to build dGPU in safety.
related functions will have to move to fusa files.

Jira NVGPU-4611

Change-Id: I41db0c039c7f15d9191cdb811b4906e779d5cc88
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310276
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 2020-12-15 14:13:28 -06:00
vinodg
a9d8fc96a7 gpu: nvgpu: hal correction for class error handling 
Add new hal function
gp10b_gr_intr_handle_class_error.

Update handle_class_error hal function for
gp10b, gv11b and tu104 to
gp10b_gr_intr_handle_class_error from
gm20b_gr_intr_handle_class_error.
gr_trapped_data_mme_pc uses 12 bits from gp10b.

Move gm20b_gr_intr_handle_class_error hal function
to non-fusa section.

Jira NVGPU-4913

Signed-off-by: vinodg <vinodg@nvidia.com>
Change-Id: Ic93013ba43d4bf409527109f2f2d43db11c4238e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2314249
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
ebb91f0b4d gpu: nvgpu: gv11b: use read_engine_status_info gops for preempt poll 
Use read_engine_status_info hal to read engine status and use
NVGPU_CTX_STATUS_* for engine ctxsw_status check instead of
directly reading h/w registers and field defs. This will make
gv11b preempt driver usable for nvgpu-next.

JIRA NVGPU-4982

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Id063f9791f38715aed3a9c7999fd253b1bc2bc87
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
0c23bf57ea gpu: nvgpu: build flag for secure boot 
Use CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT build flag for
gm20b_gr_falcon_fecs_host_int_enable.

Jira NVGPU-4661

Change-Id: Id7d991b81206d00e38049556b42b4e9a4abd1708
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313620
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
d980bd2781 gpu: nvgpu: build flag for fb mmu debug mode 
Use CONFIG_NVGPU_DEBUGGER for the following function:
- gv100_fb_set_mmu_debug_mode

Jira NVGPU-4661

Change-Id: Ia074fcab6695ba20b3cf1ef86f08d1b1735fcefe
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
8ec4395e82 gpu: nvgpu: build flag for deterministic channel 
Add CONFIG_NVGPU_DETERMINISTIC_CHANNELS and fix
preprocessor #ifdefs to allow compiling kernel mode
submit without deterministic feature enabled.

Jira NVGPU-4661

Change-Id: I4aa678715824e8981d39bd8db0c5ae61ef3a675c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
cc043e1506 gpu: nvgpu: cond. compilation of tegra dvfs code 
Protect the code dependent on tegra dvfs and bpmp dvfs code under the
config flags CONFIG_TEGRA_DVFS and CONFIG_NV_TEGRA_BPMP.

Also, update clk_config_dvfs and clk_program_na_gpc_pll to handle the
error value returned from g->ops.clk.predict_mv_at_hz_cur_tfloor.

Bug 2834141

Change-Id: I124d29f22e59fd6af7801ca859c4470483c8f7d8
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Abdul Salam
53bd199e30 gpu: nvgpu: Seperate clk monitor from clk unit 
Clock monitor is for monitoring clk status.
This is separated from clk unit which manages the clk.

NVGPU-4491

Change-Id: If83434db7970f1b024f545672a6f1e92ee66dbbc
Signed-off-by: Abdul Salam <absalam@nvidia.com>
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 2020-12-15 14:13:28 -06:00