Delete the struct nvgpu_engine_info as it's essentially identical to
struct nvgpu_device. Duplicating data structures is not ideal as it's
terribly confusing what does what.
Update all uses of nvgpu_engine_info to use struct nvgpu_device. This
is often a fairly straight forward replacement. Couple of places though
where things got interesting:
- The enum_type that engine_info uses is defined in engines.h and
has a bit of SW abstraction - in particular the GRCE type. The only
place this seemed to be actually relevant (the IOCTL providing device
info to userspace) the GRCE engines can be worked out by comparing
runlist ID.
- Addition of masks based on intr_id and reset_id; those can be
computed easily enough using BIT32() but this is an area that
could be improved on.
This reaches into a lot of extraneous code that traverses the fifo
active engines list and dramtically simplifies this. Now, instead of
having to go through a table of engine IDs that point to the list of
all host engines, the active engine list is just a list of pointers to
valid engines. It's now trivial to do a for-all-active-engines type
loop. This could even be turned into a generic macro or otherwise
abstracted in the future.
JIRA NVGPU-5421
Change-Id: I3a810deb55a7dd8c09836fd2dae85d3e28eb23cf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319895
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This adds a new device management unit in the common code responsible
for facilitating the parsing of the GPU top device list and providing
that info to other units in nvgpu.
The basic idea is to read this list once from HW and store it in a
set of lists corresponding to each device type (graphics, LCE, etc).
Many of the HALs in top can be deleted and instead implemented using
common code parsing the SW representation.
Every time the driver queries the device list it does so using a
device type and instance ID. This is common code. The HAL is responsible
for populating the device list in such a way that the driver can
query it in a chip agnostic manner.
Also delete some of the unit tests for functions that no longer
exist. This code will require new unit tests in time; those should be
quite simple to write once unit testing is needed.
JIRA NVGPU-5421
Change-Id: Ie41cd255404b90ae0376098a2d6e9f9abdd3f5ea
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319649
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Error logging bits within the nvlink blocks like TLC and MIF are
persistent through reset, to enable them to be polled following
a reset event. That means that they are in an unknown state at
cold reset, and may contain error state after a warm reset event.
Software is expected to reset them, either by writing ones to the
status bits or by writing to the DEBUG_RESET register at the IOCTRL
top level, to clear the state out before enabling error reporting.
JIRA NVGPU-4352
Change-Id: Iab4e96388fd827c0d694eada61b20f24bbddd1ff
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317683
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Enable logging and error reporting for MIF, DLPL, and TLC blocks.
Configure the NVLIPT and IOCTRL interrupt registers to rollup
the MIF and TLC errors on the link-specific fatal line and the
DLPL interrupts on link-specific intr_a(fatal) line. Both
link_err_fatal and link_intr_a are rolled up to stall interrupt line.
In the handling ISR, clear the interrupt status registers and print
an error.
Move the interrupt handling HAL code to /common/hal.
JIRA NVGPU-4350
JIRA NVGPU-4351
JIRA NVGPU-5231
JIRA NVGPU-4354
JIRA NVGPU-4355
JIRA NVGPU-4356
Change-Id: I14812499caf506592f3ae84d6681d857730d31ff
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313221
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Xavier Chip Product POR was updated to 20G only. No more qual work
happening for 16G. So we do not plan to support 16G. Now that we have
a single speed left, remove the code added to support nvlink speed from
VBIOS as it is redundant.
JIRA NVGPU-2964
Change-Id: Icd71ebb8271240818e36d40bf73c60f0c5beb6bf
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284175
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Minion Ucode is enabling HS Ucode Encyrption. Minion Ucode builds
will put out separate Debug-signed and Prod-signed Encrypted image
files. The driver will load prod image or debug image depending
on the setting of DEBUG fuse setting.
Add support to read the SCP_CTL_STAT register to differentiate
debug and prod boards and load correct binary accordingly.
Update the binary name to support two minion ucodes binaries in
the build.
JIRA NVLINK-283
Bug 2701677
Change-Id: I5348e9705708eeab4ce639b0721f10882d8970a7
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258097
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.
For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.
JIRA NVGPU-4336
Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
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gk20a.h will include gops_mc.h to contain the mc ops definitions. Add
doxygen comments for the HAL functions that are called directly.
Also move mc_gp10b_intr_pmu_unit_config to non-fusa HAL file.
JIRA NVGPU-2524
Change-Id: I4f326332d7842211b004b372d79fac9fe6ed40e7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226017
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This change switches nvgpu_timeout_peek_expired() to return a bool
instead of an int to remove advisory rule MISRA 10.5 violations.
MISRA 10.5 states that the value of an expression should not be
cast to an inappropriate essential type.
JIRA NVGPU-3798
Change-Id: I5cf9badaf07493e11a639e47ae4cf221700134ff
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155617
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- Create nvlink_bios.c/.h files to separate out nvlink
related bios code.
- Create bios_sw_<chip speciific>.c/.h files to separate
out chips specific bios code.
- Create hal files for bios under hal/bios/ and move
hardware specific code there.
- Move hardware accessing hal files from common/top
to hal/top
JIRA NVGPU-2071
Change-Id: Ia466f1cd8947540b07b237e891312123df2c6b46
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107371
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Move code used for transitioning between link and sublink modes
into a separate unit called 'link_mode_transition' under subelement
'nvlink'.
Also aggregate all the link/sublink mode related ops under
g->ops.nvlink.link_mode_transitions.
JIRA NVGPU-2862
Change-Id: I289faa10fd1c83b6b8d028b44fe244531ca42b15
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2035794
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This struct was earlier moved to falcon_priv.h to give exclusive access
to only falcon unit. However with HAL unit needing access to this we
need to move it public header nvgpu/falcon.h.
JIRA NVGPU-1993
Change-Id: Ia3b211798009107f64828c9765040d628448812a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069688
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Move the code involved in dealing with minion into a separate unit
called "nvlink_minion". This unit includes minion HW access, ucode
handling, exposing state of minion and also dealing with minion
interrupts. The interfaces to this unit are partially exposed using
g->ops.nvlink.minion ops and rest are part of nvlink_minion.h public
header.
JIRA NVGPU-2860
Change-Id: Iea9288ea5f0b26688540b1eb8ab64afd756941a4
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030103
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MISRA rule 10.6 does not allow assigning of composite expression
to an object with wider essential type. Fix 10.6 violations in nvlink
code by changing the data-type or by type-casting.
JIRA NVGPU-1921
Change-Id: I2d661ca7960e49ebc062c4eb8817004f73297cf5
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022881
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MISRA rule 14.4 allows only boolean type to be used as controlling
expression in "if" and iteration statement. Replace all non-boolean
expressions with boolean ones in "if" and "while" statements in
nvlink code.
JIRA NVGPU-1921
Change-Id: I8e8b96283c1cadf2c64fc7b8168cf44a6ceb8be5
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029073
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MISRA Rule 10.3 does not allow value of expression to be assigned to
an object with a narrower essential type or to a different essential
type category.
Fix such 10.3 violations in nvlink code by type-casting (when sure
there will be no overflows) or by changing the data-type of variables
JIRA NVGPU-1921
Change-Id: Iab103a7f0c23cf2a047152cbd76c0b55b3cc947c
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012811
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes calls to nvgpu_falcon_bootstrap to handle
error codes.
JIRA NVGPU-677
Change-Id: I1d9df6053c727e7eb3d99682ff7bb06267608a54
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008797
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Move code involved in nvlink interrupt and error handling and
initialization into a separate unit under subelement 'nvlink'.
Add g->ops.nvlink.intr_err ops to allow other units to access
the APIs exposed by this unit.
JIRA NVGPU-1813
Change-Id: I2d90cf1394faa0692630514b6a3cea15f5e105ae
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1997732
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Move the code involved in nvlink register initialization into a
separate unit called "nvlink_device_reginit".
Nvlink device_reginit will be an unit under component nvlink_init.
TLC buffer credit initialization is done by this unit.
JIRA NVGPU-1784
Change-Id: I9dd4238d0288b33867eb8a8993e56287a67a907f
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994665
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1. The nvlink code in common/ is clean from any external API usage.
There should not be any compilation issues with POSIX build if we
include nvlink.c to it.
2. Rename the nvlink file in POSIX build to avoid the tmake
duplicate filename issue.
3. Set CONFIG_TEGRA_NVLINK for POSIX to enable reporting of MISRA
violations in nvlink code by the MISRA scanner.
4. To fix the build issues:
a. Add stubs in POSIX
b. Return the 'err' variable set during dev_shutdown() as 'err'
is set but not used.
JIRA NVGPU-1921
JIRA NVGPU-1319
Change-Id: Ifdd6574d772167856782bafa74994507b3cedf4c
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2005622
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move the code involved in nvlink probe sequence into a separate
unit called "nvlink_probe"
nvlink probe code is spread over both the common and OS specific
nvlink files.
Nvlink Probe unit would encompass code needed to initialize the
nvlink software state. Nvlink software initialization involves:
1. Allocate memory for nvlink_device and nvlink_link structs
2. Read the device tree pci node to know about nvlink topology
3. Initialize nvlink function pointers needed by Tegra nvlink
core-driver
4. Register nvlink_device and nvlink_link with the core-driver.
nvlink probe returns -ENODEV when nvlink is not supported.
Nvlink is not supported in two cases:
1. There is no nvlink IP on the Tegra SoC which is denoted by
CONFIG_TEGRA_NVLINK or
2. The pci device tree node does not have "nvidia,nvlink" child
node needed to describe nvlink topology.
Any negative return value other than -ENODEV denotes failure in
execution of nvlink probe.
JIRA NVGPU-1783
Change-Id: I50011b25d88d8cc01569caac7895abe32ee38215
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994619
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The Tegra SOC nvlink driver and dGPU nvlink driver depend on
struct definitions, macros and functions exposed by nvlink-core
driver. The nvlink-core driver is not part of the nvgpu driver,
hence we should not be directly accessing any core driver
APIs/macros/structs from the /common/nvlink code. Common code can
only use nvgpu internal APIs. We wrap all calls from common/nvlink.c
to other drivers in nvgpu wrappers, and define the implementation of
wrappers in os/linux and os/nvgpu_rmos, and stub them in os/posix.
Also, we remove the implicit inclusion of OS specific nvlink header
file via common nvgpu/nvlink.h. So the OS specific code needs to
explicitly add OS specific header file.
JIRA NVGPU-966
Change-Id: I65c67e247ee74088bb1253f6ae4c8d0c49420a98
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990071
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Rename __nvgpu_set_enabled() to nvgpu_set_enabled(). The original
double underscore was present to indicate that this function is a
function with potentially unintended side effects (enabling a feature
has wide ranging impact).
To not lose this documentation a comment was added to convey that this
function must be used with care.
JIRA NVGPU-1029
Change-Id: I8bfc6fa4c17743f9f8056cb6a7a0f66229ca2583
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989434
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With intention to make falcon header free of private data we are making
all falcon struct members (pmu.flcn, sec2.flcn, fecs_flcn, gpccs_flcn,
nvdec_flcn, minion_flcn, gsp_flcn) in the gk20a, pointers to struct
nvgpu_falcon. Falcon structures are allocated/deallocated by
falcon_sw_init & _free respectively.
While at it, remove duplicate gk20a.pmu_flcn and gk20a.sec2_flcn,
refactor flcn_id assignment and introduce falcon_hal_sw_free.
JIRA NVGPU-1594
Change-Id: I222086cf28215ea8ecf9a6166284d5cc506bb0c5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968242
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Move the nvlink HAL code to unit specific directory as part
of nvgpu restructing.
This move is done after removing usage of other unit's hardware
headers from nvlink. Also confirmed that no other unit files are
including nvlink hardware headers.
JIRA NVGPU-966
Change-Id: I301e3f8de37c5792a3e1e799b97e5fdfc131f058
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975259
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