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For legacy chips (gm20b, gp10b and gv11b), incorrect register offset is used for global access register list: incorrect: 0x418300, /* gr_pri_gpcs_rasterarb_line_class */ correct: 0x418380, /* gr_pri_gpcs_rasterarb_line_class */ Fix this issue by updating global access register list by using correct register offset value. NVGPU-5108 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Change-Id: Id6722039f8d874dbcb79732dffd727d2ff2a1a72 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306642 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>