Move g->ops.fecs_trace.*() HAL operations under gr operations as
g->ops.gr.fecs_trace.*()
Also rename gk20a_ctxsw_*() functions used in common code to the
format nvgpu_gr_fecs_trace_*()
Jira NVGPU-1880
Change-Id: Idf2f8fb3d7ba2832bf1837fd97b70b3cee412123
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070767
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We have 3 header files for FECS tracing support
include/nvgpu/gr/fecs_trace.h : common header
include/nvgpu/ctxsw_trace.h : header that includes both common and
os-specific functions
os/linux/ctxsw_trace.h : linux specific header
Remove the second header since it is not needed.
Move all structures that are needed in common code to
include/nvgpu/gr/fecs_trace.h
Move all function declarations that are needed in common code to
include/nvgpu/gr/fecs_trace.h
Move all linux specific declarations in os/linux/ctxsw_trace.h and
rename this file as os/linux/fecs_trace_linux.h
Also rename os/linux/ctxsw_trace.c to os/linux/fecs_trace_linux.c
Jira NVGPU-1880
Change-Id: I05cc4489c4b6a64880b7d59c02b22cd2244d5e22
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070766
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Access to falcon's EMEM has to be synchronized to ensure atomic access
to EMEM control and data registers. Add this locking.
Not all falcons support EMEM hence handle mutex based on the enabled
flag emem_supported that is set only for TU104 currently.
JIRA NVGPU-1993
Change-Id: Idaedfb564ea0068d4690a2717d7983eb2384a69f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030618
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Earlier falcon HAL ops were embedded in the falcon structure. For clear
separation of common and HAL these ops will have to be accessed through
g->ops.falcon interfaces.
With these changes nvgpu_falcon_* functions directly call falcon gpu
ops functions for falcon. Falcon registers and HAL functions are
exported from falcon_gk20a.h. HAL files per platform are now
updated with base falcon functions.
Falcon software state such as is_falcon_supported, is_interrupt_enabled
and flcn_base are set from software init functions defined per chip.
JIRA NVGPU-2038
Change-Id: Ib1729d2833cd2c6c7b2c8ed7cbc17d4d6daeba73
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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This struct was earlier moved to falcon_priv.h to give exclusive access
to only falcon unit. However with HAL unit needing access to this we
need to move it public header nvgpu/falcon.h.
JIRA NVGPU-1993
Change-Id: Ia3b211798009107f64828c9765040d628448812a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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Add fifo sub-unit to common.fifo to handle init/deinit code
and global support functions.
Split init into:
- nvgpu_channel_setup_sw
- nvgpu_tsg_setup_sw
- nvgpu_fifo_setup_sw
- nvgpu_runlist_setup_sw
- nvgpu_engine_setup_sw
- nvgpu_userd_setup_sw
- nvgpu_pbdma_setup_sw
Split de-init into
- nvgpu_channel_cleanup_sw
- nvgpu_tsg_cleanup_sw
- nvgpu_fifo_cleanup_sw
- nvgpu_runlist_cleanup_sw
- nvgpu_engine_cleanup_sw
- nvgpu_userd_cleanup_sw
- nvgpu_pbdma_cleanup_sw
Added the following HALs
- runlist.length_max
- fifo.init_pbdma_info
- fifo.userd_entry_size
Last 2 HALs should be moved resp. to pbdma and userd sub-units,
when available.
Added vgpu implementation of above hals
- vgpu_runlist_length_max
- vgpu_userd_entry_size
- vgpu_channel_count
Use hals in vgpu_fifo_setup_sw.
Jira NVGPU-1306
Change-Id: I954f56be724eee280d7b5f171b1790d33c810470
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029620
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In the commit "gpu: nvgpu: unit: update misc atomics to use gcc
builtins" the cmpxchg macro used by the "POSIX" build changed and
introduced a MISRA 17.3 violation for a macro parameter that needed
parentheses. This updates the macro to resolve this violation.
Change-Id: I16927ecaa751964f8c397c95086c663a683f8241
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070064
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Register write from gr_gk20a_init_fs_state function are moved to hal.
New hal added for setting the pd_tpc_per_gpc, pd_skip_table_gpc and
cwd_gpcs_tpcs_num.
pd_tpc_per_gpc helps to describe the number of tpcs in each logical
gpc.
pd_skip_table helps to skip certain TPCs during distribution.
cwd_gpcs_tpcs_num helps to set number of tpcs and gpcs in CWD.
remove write for depreciated NV_PBE_PRI_ZROP_SETTING_NUM_ACTIVE_FBPS
and NV_PBE_PRI_CROP_SETTINS_NUM_ACTIVE_FBPS fields from
BES_ZROP_SETTINGS and BES_CROP_SETTINGS registers. Both these fields
changed to NUM_ACTIVE_LTCS from gm20b onwards and those are being
set in existing hal functions.
JIRA NVGPU-2951
Change-Id: I905b98356e8eadaf7e2481850de841c050ea50c5
Signed-off-by: Vinod G <vinodg@nvidia.com>
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create new hals for wait_idle and wait_fe_idle under gr.init.
modify functions to following hals and use same hals for all chips.
gr_gk20a_wait_idle -> gm20b_gr_init_wait_idle
gr_gk20a_wait_fe_idle -> gm20b_gr_init_wait_fe_idle
JIRA NVGPU-2951
Change-Id: Ie60675a08cba12e31557711b6f05f06879de8965
Signed-off-by: Vinod G <vinodg@nvidia.com>
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Add VM unit tests for the following requirements:
- NVGPU-RQCD-45.C1: A valid GPU virtual address is/is not generated
for the buffer passed into nvgpu_vm_map().
- NVGPU-RQCD-45.C2: When a GPU virtual address is passed into the
nvgpu_vm_map() function the resulting GPU virtual address of the
map does/does not match the requested GPU virtual address.
JIRA NVGPU-1927
Change-Id: I7c9f7204772a611ff7baa56b6434a70d5b70cd27
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2036213
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Some chips bypass the IOMMU on tegra. Essentially any chip using
nvlink will fall into this category.
This imposes certain oddities in the memory management for these
chips. For these chips we do not want nor need IOMMU mappings
and the overhead that comes with doing that. Instead nvgpu can
manage allocation of pages itself.
For contiguous memory nvgpu still does need to rely on the CMA.
As such this flag can be used for determining whether to use the
special nvgpu managed page allocation (for normal allocs) or the
DMA API (and therefor the CMA) for contiguous allocs.
Bug 200444660
Change-Id: I3dc4ba6ea9523f2a59966b13527d5a416aaa761a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
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The latest GPU uses nvlink and its own MMU to access memory,
instead of SMMU like others. So it doesn't go through IOMMU
framework to allocate physically non-contiguous memory. The
DMA API had a pair of downstream functions to allocate the
memory for this situation, but it is removed since it's not
likely acceptable for upstream kernel.
In order not to hack the dma-direct ops that by its meaning
is supposed to provide contiguous memory, this patch adds a
pair of memory-allocation functions inside the gpu driver,
since nvgpu is the only user.
This pair of functions are only used when GPU driver doesn't
go through either dma-direct (FORCE_CONTIGUOUS) or iommu. It
also requires GPU driver to map the non-contiguous pages.
Bug 200444660
Change-Id: I26678a3f8d63bba340872beeecbb7b0e1e7a35fa
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029680
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The flag NVGPU_DMA_FORCE_CONTIGUOUS simply means that the memory
or the pages should be forced contiguous. Meanwhile, the other
flag NVGPU_DMA_PHYSICALLY_ADDRESSED means that the memory should
be contiguous from GPU perspective, either physically contiguous
when IOMMU is not used, or virtually contiguous by IOMMU.
Thus the NVGPU_DMA_FORCE_CONTIGUOUS flag is now redundant.
This patch cleans up the NVGPU_DMA_FORCE_CONTIGUOUS flag.
Bug 200444660
Change-Id: I63bb06fea728b34ec2c6f831504392d42c426d55
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2035403
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The original free routine has three options:
if (NVGPU_DMA_NO_KERNEL_MAPPING)
dma_free_attrs(d, mem->aligned_size, mem->priv.pages,
else if (other flags)
dma_free_attrs(d, mem->aligned_size, mem->cpu_va,
else /* No flags */
dma_free_coherent(d, mem->aligned_size, mem->cpu_va,
The last dma_free_coherent() can be unwrapped to dma_free_attrs
with its dma_attrs=0, while the former two are identical except
cpu_addr. So this patch merges these three into one single call
but differentiate the cpu_addr and dma_attrs parameters.
Note that the dma_free_attrs returns 0 when flags is not set.
Bug 200444660
Change-Id: I92ec0390138c79c5109973e476ea0ea719d4e2b9
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029679
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vgpu_vm_init and vgpu_vm_remove are called directly from
common code if virtualization is supported. Introduce mm
HAL ops vm_as_alloc_share and vm_as_free_share and call
these functions through these HAL ops. Also rename these functions
from vgpu_vm_init to vgpu_vm_as_alloc_share and vgpu_vm_remove to
vgpu_vm_as_free_share as these function names are too generic and
rename to reflect their actual functionality.
For now these HAL ops are initialized only for vgpu.
Jira GVSCI-517
Change-Id: I7c5af1ab5a64ce562092f75b1488524e93e8f53f
Signed-off-by: Aparna Das <aparnad@nvidia.com>
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gr_gk20a_init_golden_ctx_image() right now resets sys/gpc/be units by
directly accessing gr_fecs_ctxsw_reset_ctl_r() register
Move this register write/read sequence to common.hal.gr.init unit
through HAL operation g->ops.gr.init.override_context_reset()
Use new HAL in gr_gk20a_init_golden_ctx_image()
Also fix the delay() operations. delay() should be added before we read
back gr_fecs_ctxsw_reset_ctl_r() register and not after
Jira NVGPU-2961
Change-Id: I70d3a61b5aa60846815dee52ecac544066542695
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070608
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Add new HAL unit common.hal.gr.init with below source files
hal/gr/init/gr_init_gm20b.c
hal/gr/init/gr_init_gm20b.h
In gr_gk20a_init_golden_ctx_image() we force FE power mode on and also
disable it. Extract out this sequence into new unit and expose new HAL
operation that takes a boolean flag to enable/disable power mode
g->ops.gr.init.fe_pwr_mode_force_on()
Use new HAL operation in gr_gk20a_init_golden_ctx_image()
Set this HAL for all the chips
Jira NVGPU-2961
Change-Id: I1dd35d94fda5e5296af67c0abc944e200fb752ea
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070607
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Semantics of the engine bootloader bootstrap are to set falcon mailbox0
register to non-zero value and verify that it is cleared to ascertain
successful completion of bootstrap.
Read was done in the engine bl_bootstrap related functions. Hence move
the write as well to those functions.
JIRA NVGPU-1993
Change-Id: I6d04148fbf1d517f0af8b4cfc2ee144d38704647
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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To validate the imem & dmem port being accessed by nvgpu, allowed ports
need to be known from hwcfg1 register. Update the hw header with these
to use for checking the valid ports in later patch.
JIRA NVGPU-1993
Change-Id: I1146a85d452d02fefcc75065a0cd546fff688fd2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030622
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Rename gr_reset_mutex to engines_reset_mutex and acquire it
before initiating recovery. Recovery running in parallel with
engine reset is not recommended.
On hitting engine reset, h/w drops the ctxsw_status to INVALID in
fifo_engine_status register. Also while the engine is held in reset
h/w passes busy/idle straight through. fifo_engine_status registers
are correct in that there is no context switch outstanding
as the CTXSW is aborted when reset is asserted.
Use deferred_reset_mutex to protect deferred_reset_pending variable
If deferred_reset_pending is true then acquire engines_reset_mutex
and call gk20a_fifo_deferred_reset.
gk20a_fifo_deferred_reset would also check the value of
deferred_reset_pending before initiating reset process
Bug 2092051
Bug 2429295
Bug 2484211
Bug 1890287
Change-Id: I47de669a6203e0b2e9a8237ec4e4747339b9837c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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set gr.initialized to false in the beginning of gk20a_gr_reset() and
set it to true at the end of successful execution of gk20a_gr_reset.
Use gk20a_gr_wait_initialized() to enable/disable cg/pg
functions to make sure engine is out of reset and initialized.
Bug 2092051
Bug 2429295
Bug 2484211
Bug 1890287
Change-Id: Ic7b0b71382c6d852a625c603dad8609c43b7f20f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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if fecs is sent stop_ctxsw method, elpg entry/exit cannot happen
and may timeout. It could manifest as different error signatures
depending on when stop_ctxsw fecs method gets sent with respect
to pmu elpg sequence. It could come as pmu halt or abort or
maybe ext error too.
If ctxsw failed to disable, do not read engine info and just abort tsg.
Bug 2092051
Bug 2429295
Bug 2484211
Bug 1890287
Change-Id: I5f3ba07663bcafd3f0083d44c603420b0ccf6945
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014914
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For handle_sched_error, change err to info print for failing eng
id returned as -1 i.e. FIFO_INVAL_ENGINE_ID as no engine is found
busy doing ctxsw. May be ctxsw already finished for the context
for which ctxsw timeout intr was triggered.
Possible Causes:
a)
On hitting engine reset, h/w drops the ctxsw_status to INVALID in
fifo_engine_status register. Also while the engine is held in reset
h/w passes busy/idle straight through. fifo_engine_status registers
are correct in that there is no context switch outstanding
as the CTXSW is aborted when reset is asserted.
This is just a side effect of how gv100 and earlier versions of
ctxsw_timeout behave.
With gv10b and later, h/w snaps the context at the point of error
so that s/w can see the tsg_id which caused the HW timeout.
b)
If engines are not busy and ctxsw state is valid then intr occurred
in the past and if the ctxsw state has moved on to VALID from LOAD
or SAVE, it means that whatever timed out eventually finished
anyways. The problem with this is that s/w cannot conclude which
context caused the problem as maybe more switches occurred before
intr is handled.
Bug 2092051
Bug 2429295
Bug 2484211
Bug 1890287
Change-Id: Ia79bee6e860fb179ee39024c963671d4f8245227
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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ACR HS ucode self-load & bootstrap functionality was part of FB
unit to support FB mem-unlock HS ucode & this needs to access
some ACR structs which will be part of ACR private headers &
adding constraints to implement ACR unit private header support.
JIRA NVGPU-2907
Change-Id: I6c6c7504ffe55426b377e9bcf911d4005813bb31
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069724
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struct wpr_carveout_info is used to fetch WPR info by passing
as parameter to FB HAL, changed to pass multiple params to get
WPR base & size individually from FB HAL which removes dependency
between ACR & FB.
JIRA NVGPU-2907
Change-Id: I03af1a5358fcab5dc8237899d16a0b51a6779b1f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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Currenlty struct hs_acr passed to engine falcon bootstrap function
to pass falcon info to the falcon unit to execute the ACR HS bin
using engine falcon, as engine already cached the falcon info as
part its structure so removed struct hs_acr parameter pass.
JIRA NVGPU-2907
Change-Id: I0b647b2763c52e97de0c17cfdd273486138ee404
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069593
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The functions gk20a_dump_eng_status and gv11b_dump_eng_status belongs
to engine_status HAL unit.
1) The corresponding declaration and definitions of the above functions
are moved from fifo_{arch} files to engine_status_{arch} files.
2) The corresponding HAL pointer .dump_eng_status is moved from
fifo to engine_status HAL unit.
3) gv11b_dump_eng_status is now based to gv100b_dump_eng_status
4) Small changes in the files for ENGINE_STATUS such as correction of
HEADER DEFINES etc
Jira NVGPU-1315
Change-Id: I7fc06eab97206bc3b78c6f5c7aa30fa2c034961c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
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The corresponding HAL pointer for gk20a_fifo_wait_engine_idle is not
being invoked anywhere and hence they are removed from the code.
The function gk20a_fifo_wait_engine_idle belongs to engine unit and is
only called in a non-safe build, hence its moved to engine unit and is
restricted by a non-safe build flag NVGPU_ENGINE
Also, gk20a_fifo_wait_engine_idle is renamed to nvgpu_engine_wait_for_idle
Jira NVGPU-1315
Change-Id: Ie550c7e46a4284dfe368859d828b1994df34185f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
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The following functions belong to engine unit and are moved
gk20a_fifo_enable_engine_activity
gk20a_fifo_enable_all_engine_activity
gk20a_fifo_disable_engine_activity
gk20a_fifo_disable_all_engine_activity
These are renamed by replacing gk20a_fifo with nvgpu_engine as prefix.
These functions are only invoked by linux build and not required for
safety build and hence they are defined when
-DNVGPU_ENGINE is enabled.
Jira NVGPU-1315
Change-Id: I39d820879bb55b40e754526c657d794930a4b6a1
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2032606
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
common.fifo.engine unit has both safe as well as non-safe functions.
The build flag NVGPU_ENGINE is used to restrict the use of
non-safe functions of the engine unit in safety builds.
Jira NVGPU-1315
Change-Id: Ic363ad547e07136024a254c078fdf0194fafc265
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2032605
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
