Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.
This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.
Jira NVGPU-3476
Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
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Since dGPU support is not required for initial safety release, compile
out dGPU sw and hal implementations except below files that are used
by gv11b currently: acr_sw_gv100.c, engine_status_gv100.c, gr_gv100.c
gr_config_gv100.c and hwpm_map_gv100.c.
JIRA NVGPU-3062
Change-Id: I8a6bc8b235e7e5eac5b0e76147b8bd12f9abbd2d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119586
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Access to falcon's EMEM has to be synchronized to ensure atomic access
to EMEM control and data registers. Add this locking.
Not all falcons support EMEM hence handle mutex based on the enabled
flag emem_supported that is set only for TU104 currently.
JIRA NVGPU-1993
Change-Id: Idaedfb564ea0068d4690a2717d7983eb2384a69f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030618
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Earlier falcon HAL ops were embedded in the falcon structure. For clear
separation of common and HAL these ops will have to be accessed through
g->ops.falcon interfaces.
With these changes nvgpu_falcon_* functions directly call falcon gpu
ops functions for falcon. Falcon registers and HAL functions are
exported from falcon_gk20a.h. HAL files per platform are now
updated with base falcon functions.
Falcon software state such as is_falcon_supported, is_interrupt_enabled
and flcn_base are set from software init functions defined per chip.
JIRA NVGPU-2038
Change-Id: Ib1729d2833cd2c6c7b2c8ed7cbc17d4d6daeba73
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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This struct was earlier moved to falcon_priv.h to give exclusive access
to only falcon unit. However with HAL unit needing access to this we
need to move it public header nvgpu/falcon.h.
JIRA NVGPU-1993
Change-Id: Ia3b211798009107f64828c9765040d628448812a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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Semantics of the engine bootloader bootstrap are to set falcon mailbox0
register to non-zero value and verify that it is cleared to ascertain
successful completion of bootstrap.
Read was done in the engine bl_bootstrap related functions. Hence move
the write as well to those functions.
JIRA NVGPU-1993
Change-Id: I6d04148fbf1d517f0af8b4cfc2ee144d38704647
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034511
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Add common/falcon/falcon_priv.h file that will contain declarations
private to Falcon unit. Clean up the falcon header files inclusion.
Rules followed:
1. Remove unneeded header file includes.
2. Falcon unit source files will only include falcon_priv.h.
3. Base architecture Falcon source (falcon_gk20a.c) will only
include hw_falcon_*.h file.
4. Derived architecture source will include hw headers if needed.
5. Other units should not include hw headers for Falcon.
6. HAL source will include the Falcon unit header if needed.
JIRA NVGPU-1459
Change-Id: Ia9f03f7b577fe10b8c0f417e6302fa7ebd4131cc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1961634
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With intention to make falcon header free of private data we are making
all falcon struct members (pmu.flcn, sec2.flcn, fecs_flcn, gpccs_flcn,
nvdec_flcn, minion_flcn, gsp_flcn) in the gk20a, pointers to struct
nvgpu_falcon. Falcon structures are allocated/deallocated by
falcon_sw_init & _free respectively.
While at it, remove duplicate gk20a.pmu_flcn and gk20a.sec2_flcn,
refactor flcn_id assignment and introduce falcon_hal_sw_free.
JIRA NVGPU-1594
Change-Id: I222086cf28215ea8ecf9a6166284d5cc506bb0c5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968242
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pmu.g & sec2.g were set in nvgpu_falcon_sw_init. They are now set
in nvgpu_early_init_pmu_sw & nvgpu_init_sec2_setup_sw. Pass gk20a
& pmu struct to nvgpu_init_pmu_fw_support like sec2.
pmu_fw_support & sec2_setup_sw are separated from respective init
sequence and now are called earlier since we need ->g member earlier
and most of the setup is sw only.
nvgpu_init_pmu_fw_ver_ops is now being exported.
JIRA NVGPU-1594
Change-Id: I6c71c6730ce06dad190159269e2cc60301f0237b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968241
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals or casting operands
to have same type of operands when an arithmetic operation is
performed.
This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I27e3e59c3559c377b4bd3cbcfced90fdf90350f2
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921459
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.
Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.
JIRA NVGPU-1022
Change-Id: I61a2d24830428ffc2655bd9c45bb5403c7f22c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943058
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MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.
Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.
JIRA NVGPU-1022
Change-Id: I957f8ca1fa0eb00928c476960da1e6e420781c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941002
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.
JIRA NVGPU-1019
Change-Id: I9e18ffc961d485225732c34d3ca561e84d182d07
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921370
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MISRA rule-14.4 doesn't allow the usage of function pointers & integer
types as booleans in the controlling expression of an if statement or
an iteration statement.
Fix violations where a function pointer or a function whose return
value is an integer, is used as a boolean in the controlling expression
of if and loop statements.
JIRA NVGPU-1021
Change-Id: Ic5336268394ba4396ce80744c25930d2fb44dc42
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1932147
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-Created struct nvgpu_sec2 to hold members
related to SEC2-RTOS ucode support in header file
sec2.h
-Created nvgpu_sec2 variable under struct gk20a.
-Created NVGPU_SUPPORT_SEC2_RTOS enable flag
to enable SEC2 RTOS support.
-Defined method nvgpu_init_sec2_support() to
init SEC2 RTOS support by performing s/w setup like
mutex-init, sequence-init & add support
for remove_support.
-Defined method nvgpu_sec2_destroy() to deinit
SEC2 RTOS support.
-Added nvgpu_init_sec2_support()/nvgpu_sec2_destroy()
as part gk20a_finalize_poweron()/gk20a_prepare_poweroff()
sequence based on NVGPU_SUPPORT_SEC2_RTOS enable flag
-Assigned g->sec2->flcn to point to g->sec2_flcn to access
falcon.
-Made Makefile changes to include sec2.c to build
JIRA NVGPUT-80
Change-Id: Icdc8c25994e305427ad465a5a20e9ce533759a9e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1791955
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-Added HAL copy_from_emem & copy_to_emem to struct
nvgpu_falcon_engine_dependency_ops data struct to point to
engine specific EMEM access functions.
-Added function nvgpu_flcn_copy_from_emem() &
nvgpu_flcn_copy_to_emem() at interface layer to
access EMEM using flacon engine EMEM HAL's.
JIRA NVGPU-1161
Change-Id: Ifb72a617277e73f25f1772c969791b642585e7fb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807336
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- Defined FALCON_ID_GSPLITE for GSP falcon.
- Created variable gsp_flcn of struct nvgpu_falcon
for GSP falcon & registered to falcon module to access
falcon functions.
- Created HAL file gsp_gv100.c/h for GSP.
- Modified Makefile & Makefile.sources files to include
gsp_gv100 HAL file.
- Enabled GSP falcon support for GV100 by registering
to common falcon module.
- Defined function gv100_gsp_reset() & assigned to
falcon reset as GSP engine reset.
- Updated falcon HAL init code not to return error
if requested falcon is not supported, instead log
the info and return non-error.
JIRA NVGPU-1160
Change-Id: Ice032cf443ae87254375265628b3c022f41544cd
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for calls to nvgpu_mutex_init and
improves related error handling.
JIRA NVGPU-677
Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805598
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-Created common falcon function nvgpu_flcn_bl_bootstrap() to
bootstrap falcon bootloader
-Created HAL gk20a_falcon_bl_bootstrap() which does actual
bootloader bootstrap by fetching parameters and loading
code/parameters as needed.
-Created HAL ops bl_bootstrap under nvgpu_falcon_ops.
-Created struct nvgpu_falcon_bl_info to hold info required
for bootloader to pass to common function
-Removed falcons bootstrap code in multiple file & made
changes to fill struct nvgpu_falcon_bl_info & call
nvgpu_flcn_bl_bootstrap().
Change-Id: Iee275233915ff11f9afb5207ac0c3338ca9dacc1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756104
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Adds the skeleton and integration of the GV100 endpoint driver to NVGPU
(1) Adds a OS abstraction layer for the internal nvlink structure.
(2) Adds linux specific integration with Nvlink core driver.
(3) Adds function pointers for nvlink api, initialization and isr process.
(4) Adds initial support for minion.
(5) Adds new GPU enable properties to handle NVLINK presence
(6) Adds new GPU enable properties for SG_PHY bypass (required for NVLINK over
PCI)
(7) Adds parsing of nvlink vbios structures.
(8) Adds logging defines for NVGPU
JIRA: EVLR-2328
Change-Id: I0720a165a15c7187892c8c1a0662ec598354ac06
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
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-Added nvgpu_flcn_mem_scrub_wait() to
falcon interface layer to poll imem/dmem
scrubbing status complete check for 1msec
with status check interval of 10usec.
-Called nvgpu_flcn_mem_scrub_wait() in
falcon reset interface to check scrubbing
status upon falcon/engine reset.
-Replaced mem scrubbing wait check code in
pmu_enable_hw() by calling
nvgpu_flcn_mem_scrub_wait()
Bug 200346134
Change-Id: Iac68e24dea466f6dd5facc371947269db64d238d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1598644
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- Add methods to read/write falcon mailbox
at interface layer
- Created falcon mailbox read/write HAL
- Added HAL methods to read/write mailbox
- Added macro to get next block based on address
- Added macro to get IMEM tag using IMEM address
- Added ucode header format
Change-Id: I879b1df4538d403cac40fd4ed6e723190f62922c
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
(cherry picked from commit 30e8b76a7be9d9e6d8225bdc08e441f408692f63)
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