Konsta Hölttä
4acf78dff3
gpu: nvgpu: guard sync cmd hals properly
...
Make the syncpt and sema wait and incr command HAL ops consistent. Add
CONFIG_NVGPU_SW_SEMAPHORE guards for the semaphore ops. The syncpoint
ops already have CONFIG_TEGRA_GK20A_NVHOST around them.
Delete the dummy syncpt ops. They are not used; the ops are only needed
when the real versions exist.
Jira NVGPU-4548
Change-Id: I30315a67169b31b1d63a0a1a0a4492688db4a2bc
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325100
(cherry picked from commit ed13b286c5fbdbc008ec59172d98ac79e9f2e733)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2331337
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
39844fb27c
gpu: nvgpu: hide priv cmdbuf mem writes
...
Add an API to append data to a priv cmdbuf entry. Hold the write pointer
offset internally in the entry instead of having the user keep track of
where those words are written to.
This helps in eventually hiding struct priv_cmd_entry from users and
provides a more consistent interface in general. The wait and incr
commands are now slightly easier to read as well when they're just
arrays of data.
A syncfd-backed prefence may be composed of several individual fences.
Some of those (or even a fence backed by just one) may be already
expired, and currently the syncfd export design releases and nulls
semaphores when expired (see gk20a_sync_pt_has_signaled()) so for those
the wait cmdbuf is appended with zeros; the specific function is for
this purpose.
Jira NVGPU-4548
Change-Id: I1057f98c1b5b407460aa6e1dcba917da9c9aa9c9
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325099
(cherry picked from commit 6a00a65a86d8249cfeb06a05682abb4771949f19)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2331336
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2020-12-15 14:13:28 -06:00
Tejal Kudav
5af8cedf05
gpu: nvgpu: Nvlink interrupt handling
...
Enable logging and error reporting for MIF, DLPL, and TLC blocks.
Configure the NVLIPT and IOCTRL interrupt registers to rollup
the MIF and TLC errors on the link-specific fatal line and the
DLPL interrupts on link-specific intr_a(fatal) line. Both
link_err_fatal and link_intr_a are rolled up to stall interrupt line.
In the handling ISR, clear the interrupt status registers and print
an error.
Move the interrupt handling HAL code to /common/hal.
JIRA NVGPU-4350
JIRA NVGPU-4351
JIRA NVGPU-5231
JIRA NVGPU-4354
JIRA NVGPU-4355
JIRA NVGPU-4356
Change-Id: I14812499caf506592f3ae84d6681d857730d31ff
Signed-off-by: Tejal Kudav <tkudav@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313221
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
6202ead057
gpu: nvgpu: split sema sync hal to wait and incr
...
Instead of one HAL op with a boolean flag to decide whether to do one
thing or another entirely different thing, use two separate HAL ops for
filling priv cmd bufs with semaphore wait and semaphore increment
commands. It's already two ops for syncpoints, and explicit commands are
more readable than boolean flags.
Change offset into cmdbuf in sem wait HAL to be relative to the cmdbuf,
so the HAL adds the cmdbuf internal offset to it.
While at it, modify the syncpoint cmdbuf HAL ops' prototypes to be
consistent.
Jira NVGPU-4548
Change-Id: Ibac1fc5fe2ef113e4e16b56358ecfa8904464c82
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323319
(cherry picked from commit 08c1fa38c0fe4effe6ff7a992af55f46e03e77d0)
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2020-12-15 14:13:28 -06:00
Vinod G
6a7bf6cdc0
gpu: nvgpu: update sm ecc_status_error handling
...
Use gv11b_gr_intr_handle_tpc_sm_ecc_exception
function for future chip to avoid code replication.
Add sm_ecc_status_errors hal to read
the ecc_status_errors
Jira NVGPU-5033
Signed-off-by: Vinod G <vinodg@nvidia.com >
Change-Id: I4a25837d9b833a48307b9353b82ff6597f985e41
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
b3d16b23d5
gpu: nvgpu: extract priv cmdbuf from channel.c
...
Move private command buffer related functionality to priv_cmdbuf.c. This
is used only for kernel mode submits, so it makes sense to group it out,
and the priv cmdbuf stuff is used also by things that don't care about
channels.
Jira NVGPU-4548
Change-Id: Idbb42e3ed3984e16c654bb9aa2b7564b780048a4
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323146
(cherry picked from commit bb67bfc7ab8e87236f31bc4f6c80dab042609f21)
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
c6908922e5
gpu: nvgpu: move generic preempt hals to common
...
- Move fifo.preempt_runlists_for_rc and fifo.preempt_tsg hals to common
source file as nvgpu_fifo_preempt_runlists_for_rc and
nvgpu_fifo_preempt_tsg.
Jira NVGPU-4881
Change-Id: I31f7973276c075130d8a0ac684c6c99e35be6017
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
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2020-12-15 14:13:28 -06:00
Antony Clince Alex
5555b6db87
gpu: nvgpu: add isr_handle_0/1 priv_ring gops
...
Add below hals to priv_ring gops. These hals are used from gp10b onwards.
- isr_handle_0
- isr_handle_1
Jira: NVGPU-4669
Change-Id: I95aaebfd4c9c292b7b0da98cd34ac2a8472a5e1d
Signed-off-by: Antony Clince Alex <aalex@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318245
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2020-12-15 14:13:28 -06:00
Vinod G
0e0b966f0c
gpu: nvgpu: update gr exception hal
...
Make generic gr exception static functions
to public functions.
Jira NVGPU-5033
Signed-off-by: Vinod G <vinodg@nvidia.com >
Change-Id: I9ac4cbc728edda813a487f80af622559a798b319
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2324676
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2020-12-15 14:13:28 -06:00
Vinod G
340ea241cb
gpu: nvgpu: remove channel debug_dump hal
...
Channel debug_dump hal function does not involve
any register related code.
Move gv11b_channel_debug_dump hal function to
common code nvgpu_channel_info_debug_dump function.
Check gpu hw version to limit instance variables
dump that differs between socs.
Add new hal pointer syncpt_debug_dump for pbdma.
Jira NVGPU-5109
Signed-off-by: Vinod G <vinodg@nvidia.com >
Change-Id: Icfca837ce8e4117387cffa6fadf6c094c7da5946
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321016
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2020-12-15 14:13:28 -06:00
Debarshi Dutta
f483304238
gpu: nvgpu: add prerequisite for syncpoint-shim support
...
add check for nvgpu_has_syncpoints() before enabling syncpoint-shim and
usermode_syncpoint support. Syncpoint shim cannot exist without
syncpoint support in the first place.
Bug 200551105
Change-Id: I2a9c6d23c72a25bcac4a2a8737ed0bad14cd4d8f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323208
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2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
675fb39ca0
gpu: nvgpu: add runlist.init_enginfo hal
...
Add runlist.init_enginfo hal to initialize
runlist's engine info. nvgpu-next has it's own
implementation for init_enginfo hal, so removed
NVGPU_NEXT_INIT_RUNLIST_ENGINFO from nvgpu hals.
JIRA NVGPU-4979
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com >
Change-Id: Ie35a88c6ba3c7c741124386f7c643b36b42d4143
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2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
2f6be2735e
gpu: nvgpu: remove nvgpu-next gr init
...
nvgpu-next gr init is handled within nvgpu-next
hals. So remove references to NVGPU_NEXT_INIT_GR_INFO from
nvgpu hals.
JIRA NVGPU-4979
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com >
Change-Id: I2e493220f855a7ff2f940cf07b1fc0b876601df5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319102
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
44f12288ad
gpu: nvgpu: add mc.reset_engine hal for nvgpu-next
...
Engine reset process has changed for nvgpu-next. Add mc.reset_engine
gops for nvgpu-next.
Modify engine reset functions to use mc.reset_engine hal.
Jira NVGPU-5145
Change-Id: I176800212042eaef71c8cbd4bc499805c5af0e60
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2312485
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
d0ffb335dc
gpu: nvgpu: move nvgpu_has_syncpoints
...
nvgpu_has_syncpoints is more general than a channel synchronization
related, so move it to nvhost.c from channel_sync.c. Move the
declaration from gk20a.h to nvhost.h.
As the debugfs knob is Linux related, move it from struct gk20a to
struct nvgpu_os_linux.
Jira NVGPU-4548
Change-Id: I4236086744993c3daac042f164de30939c01ee77
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318814
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
db9c1b1f97
gpu: nvgpu: don't build sw semas for dgpu
...
Make tu104's sema cmd HAL ops depend on CONFIG_NVGPU_SW_SEMAPHORE
in addition to the kernel mode submit flag.
Drop CONFIG_NVGPU_SW_SEMAPHORE from NVGPU_FORCE_DGPU_SAFETY_PROFILE.
Semaphore-based synchronization is not actually needed for dgpu.
Jira NVGPU-4548
Change-Id: I3fe066dbeb68295dfc4bbe09256ff6a20c892c2f
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318737
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2020-12-15 14:13:28 -06:00
Thomas Fleury
88c774e5d1
gpu: nvgpu: enable clk_arb for dGPU safety
...
Enable CONFIG_NVGPU_CLK_ARB for dGPU safety build.
Use CONFIG_NVGPU_NON_FUSA for invocation of non-safe functions:
- nvgpu_hr_timestamp
- nvgpu_hr_timestamp_us
Jira NVGPU-4661
Jira NVGPU-5235 (for addressing usage of above functions).
Change-Id: I271fdbc45c1e4d01cb70d50dcf63d15b9df33c76
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317842
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2020-12-15 14:13:28 -06:00
Thomas Fleury
25edcc1353
gpu: nvgpu: cta preemption mode HAL for tu104
...
Use gp10b_ctxsw_prog_set_compute_preemption_mode_cta instead
of gm20b_ctxsw_prog_set_compute_preemption_mode_cta for tu104.
Jira NVGPU-4661
Change-Id: I7b85cbcc139e6843c8b7bd89e0afb6030160362f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
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2020-12-15 14:13:28 -06:00
Thomas Fleury
28ccd63f69
gpu: nvgpu: enable CONFIG_NVGPU_LS_PMU for safety
...
Enable CONFIG_NVGPU_LS_PMU for dGPU safety build.
Add missing #ifdefs for CONFIG_NVGPU_POWER_PG and
CONFIG_NVGPU_CLK_ARB which are not defined for safety build.
Moved gm20b_mc_is_enabled to fusa code.
NVGPU_UNIT_PWR is only defined when CONFIG_NVGPU_HAL_NON_FUSA
is defined. Added #ifdefs to compile out gk20a_pmu functions
that are using it.
Jira NVGPU-4661
Change-Id: Ieb552f9374bad6f3dad777322f118931e0bc94ec
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
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2020-12-15 14:13:28 -06:00
Antony Clince Alex
da8ee8d615
gpu: nvgpu: add therm_max_fpdiv_factor gops.therm
...
Use therm_max_fpdiv_factor gops.therm for nvgpu-next to get the maximum
fp_div_factor.
Jira NVGPU-4860
Signed-off-by: Antony Clince Alex <aalex@nvidia.com >
Change-Id: If0e9b82f5b61289e226ceeff386fc88763af66e2
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313336
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2020-12-15 14:13:28 -06:00
Abdul Salam
4f5bd9e633
gpu: nvgpu: Implement clk_good and pll_lock check
...
Add clk_good and pll_lock check as a part of fmon polling.
This will poll for any clock related faults at FTTI interval.
Add new function to poll for vbios init completion.
NVGPU-4967
Bug 2849506
Bug 200564937
Change-Id: I5bc885329981e07376824e148edabe9be4120e1c
Signed-off-by: Abdul Salam <absalam@nvidia.com >
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2020-12-15 14:13:28 -06:00
sagar
b8a3e54dda
gpu: nvgpu: add invalid ctxsw method
...
* For ctxsw negative testing, nvgpu need to send and invalid method
* Sending 0xFFFF method will result in triggering ctxsw error intr.
JIRA NVGPU-5080
Change-Id: I6c16137d86ee2ddb25f1508161d9d6befcbcbefe
Signed-off-by: sagar <skadamati@nvidia.com >
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2020-12-15 14:13:28 -06:00
Thomas Fleury
f43d5df83a
gpu: nvgpu: build dGPU in safety
...
Enable build flags for dGPU in safety, when
NVGPU_FORCE_DGPU_SAFETY_PROFILE is set.
Use libnvgpu-dgpu_safe.exports for dGPU safety build.
Add build flags for tu104 HAL initialization (to solve
undefined symbols in safety build).
Temporarily add non-fusa files needed to build dGPU in safety.
related functions will have to move to fusa files.
Jira NVGPU-4611
Change-Id: I41db0c039c7f15d9191cdb811b4906e779d5cc88
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310276
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2020-12-15 14:13:28 -06:00
vinodg
a9d8fc96a7
gpu: nvgpu: hal correction for class error handling
...
Add new hal function
gp10b_gr_intr_handle_class_error.
Update handle_class_error hal function for
gp10b, gv11b and tu104 to
gp10b_gr_intr_handle_class_error from
gm20b_gr_intr_handle_class_error.
gr_trapped_data_mme_pc uses 12 bits from gp10b.
Move gm20b_gr_intr_handle_class_error hal function
to non-fusa section.
Jira NVGPU-4913
Signed-off-by: vinodg <vinodg@nvidia.com >
Change-Id: Ic93013ba43d4bf409527109f2f2d43db11c4238e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2314249
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2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
ebb91f0b4d
gpu: nvgpu: gv11b: use read_engine_status_info gops for preempt poll
...
Use read_engine_status_info hal to read engine status and use
NVGPU_CTX_STATUS_* for engine ctxsw_status check instead of
directly reading h/w registers and field defs. This will make
gv11b preempt driver usable for nvgpu-next.
JIRA NVGPU-4982
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com >
Change-Id: Id063f9791f38715aed3a9c7999fd253b1bc2bc87
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2311276
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2020-12-15 14:13:28 -06:00
Thomas Fleury
0c23bf57ea
gpu: nvgpu: build flag for secure boot
...
Use CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT build flag for
gm20b_gr_falcon_fecs_host_int_enable.
Jira NVGPU-4661
Change-Id: Id7d991b81206d00e38049556b42b4e9a4abd1708
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313620
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2020-12-15 14:13:28 -06:00
Thomas Fleury
d980bd2781
gpu: nvgpu: build flag for fb mmu debug mode
...
Use CONFIG_NVGPU_DEBUGGER for the following function:
- gv100_fb_set_mmu_debug_mode
Jira NVGPU-4661
Change-Id: Ia074fcab6695ba20b3cf1ef86f08d1b1735fcefe
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313590
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2020-12-15 14:13:28 -06:00
Thomas Fleury
8ec4395e82
gpu: nvgpu: build flag for deterministic channel
...
Add CONFIG_NVGPU_DETERMINISTIC_CHANNELS and fix
preprocessor #ifdefs to allow compiling kernel mode
submit without deterministic feature enabled.
Jira NVGPU-4661
Change-Id: I4aa678715824e8981d39bd8db0c5ae61ef3a675c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310325
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2020-12-15 14:13:28 -06:00
Sagar Kamble
cc043e1506
gpu: nvgpu: cond. compilation of tegra dvfs code
...
Protect the code dependent on tegra dvfs and bpmp dvfs code under the
config flags CONFIG_TEGRA_DVFS and CONFIG_NV_TEGRA_BPMP.
Also, update clk_config_dvfs and clk_program_na_gpc_pll to handle the
error value returned from g->ops.clk.predict_mv_at_hz_cur_tfloor.
Bug 2834141
Change-Id: I124d29f22e59fd6af7801ca859c4470483c8f7d8
Signed-off-by: Sagar Kamble <skamble@nvidia.com >
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2020-12-15 14:13:28 -06:00
Abdul Salam
53bd199e30
gpu: nvgpu: Seperate clk monitor from clk unit
...
Clock monitor is for monitoring clk status.
This is separated from clk unit which manages the clk.
NVGPU-4491
Change-Id: If83434db7970f1b024f545672a6f1e92ee66dbbc
Signed-off-by: Abdul Salam <absalam@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313201
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2020-12-15 14:13:28 -06:00
Sagar Kamble
59c6947fc6
gpu: nvgpu: add CONFIG_NVGPU_TEGRA_FUSE
...
Encapsulate the tegra fuse functionality under the config flag
CONFIG_NVGPU_TEGRA_FUSE.
Bug 2834141
Change-Id: I54c9e82360e8a24008ea14eb55af80f81d325cdc
Signed-off-by: Sagar Kamble <skamble@nvidia.com >
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
00eec69b3f
gpu: nvgpu: add hal to get_ctx_buffer_offsets
...
Currently, gr_gk20a_get_ctx_buffer_offsets is defined as a function.
However, this function is used in the common code. So, add new GR hal
to get_ctx_buffer_offsets.
Jira NVGPU-5047
Change-Id: I0cec6ff19194fa726722e6af3a2f11a188dc9087
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310352
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2020-12-15 14:13:28 -06:00
vinodg
4aff9bcd4e
gpu: nvgpu: fix for load imbalance across cta subpartitions
...
CTA_SUBPARTITION_SKEW load balancing is broken across
subpartitions. SW WAR to disable the CTA_SUBPARTITION_SKEW.
Jira NVGPU-5132
Bug 200593339
Signed-off-by: vinodg <vinodg@nvidia.com >
Change-Id: I3faae882a94fc6262cc287df44994cc04b4fd5d6
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308905
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Sagar Kamble
ea09ef92b5
gpu: nvgpu: conditional compilation of nvhost code
...
There were few more nvhost related references unprotected by the config
flag. Fix those.
Bug 2834141
Change-Id: Id7d94e3e6fa471f02697d121b557884c7287c26e
Signed-off-by: Sagar Kamble <skamble@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306437
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2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
feebc746ca
gpu: nvgpu: fix global register access list
...
For legacy chips (gm20b, gp10b and gv11b), incorrect register
offset is used for global access register list:
incorrect: 0x418300, /* gr_pri_gpcs_rasterarb_line_class */
correct: 0x418380, /* gr_pri_gpcs_rasterarb_line_class */
Fix this issue by updating global access register list by using
correct register offset value.
NVGPU-5108
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com >
Change-Id: Id6722039f8d874dbcb79732dffd727d2ff2a1a72
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306642
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2020-12-15 14:13:28 -06:00
rmylavarapu
e424e4791a
gpu: nvgpu: perf: Refactor Perf unit
...
-Renamed and moved nvgpu_pmu_perf struct from public
to unit specific
-Renamed all functions as per public/private format
NVGPU-5029
Change-Id: If3f479bb1443850a5c8a8714cd1c9da346cb566a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com >
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2020-12-15 14:13:28 -06:00
Seema Khowala
31b8ecbcee
gpu: nvgpu: gp10b: sim: handle priv ring interrupts
...
priv_ring interrupts are enabled for sim. Handle the
interrupt on sim too.
JIRA NVGPU-4864
JIRA NVGPU-5017
Change-Id: I2ff16c0a8ff152839765556dd3b117995f9de109
Signed-off-by: Seema Khowala <seemaj@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306040
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2020-12-15 14:13:28 -06:00
Sagar Kamble
98e84b8046
gpu: nvgpu: fix the includes in ce unit
...
As per the coding guidelines, absolute paths in header inclusion are
prohibited. Fix such instances in ce unit.
JIRA NVGPU-5075
Change-Id: I63ebc576e72a8a666a2c9d207dafc4e96473ea32
Signed-off-by: Sagar Kamble <skamble@nvidia.com >
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2020-12-15 14:13:28 -06:00
Divya Singhatwaria
7fb3410d72
gpu: nvgpu: Updated traceability in ACR and PMU
...
Updated unit test specifcation in ACR and PMU
unit and add traceability from test to design.
JIRA NVGPU-4319
JIRA NVGPU-2192
Change-Id: Iadffaf42f0844c556ba6d9b898d2896863ff0237
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com >
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2020-12-15 14:13:28 -06:00
Divya Singhatwaria
00b7ea7f13
gpu: nvgpu: Remove hard coded constants from PMU
...
During code inspection use of some hard coded
constants was found in some parts of the code.
Those constants are replaced by macros
JIRA NVGPU-5031
Change-Id: I50821839bc36c8d28b3e8678abdf82a856b9d8d2
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300562
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2020-12-15 14:13:28 -06:00
Divya Singhatwaria
ed4eb79ac1
gpu: nvgpu: SWUD Lite updates
...
Updated minor typo errors found during code inspection
JIRA NVGPU-4785
JIRA NVGPU-4789
Change-Id: I37384a852e9a2783e3033a6f12c21eafc00e5bcf
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300560
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2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
6669cbd7de
gpu: nvgpu: gv11b: fix veid bundle wait issue
...
For non go_idle bundles, check should be fe_idle
not gr_idle. fe_gi state will be busy until go_idle
bundle gets processed.
Bug 2804205
Change-Id: I12dd05f59d406aeac9476e0c85b6e457c6bd6bed
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299895
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2020-12-15 14:13:28 -06:00
Thomas Fleury
1f9f28df8c
gpu: nvgpu: remove barrier from gm20b_channel_bind
...
In gm20b_channel_bind an nvgpu_smp_wmb() was used presumably to
prevent MMIO writes from being re-ordered after the memory write
to 'ch->bound'. If that was to happen, then unbind routine could
observe the channel as bound and issue concurrent MMIO writes
to unbind the channel. Assuming, the barrier was to prevent
such race, it should have been an nvgpu_wmb(), since
nvgpu_smp_wmb() is for inner shareable domain only.
However, the race possibility between unbind called from close
path and bind from ALLOC_GPFIFO should be ruled out because
close will wait for any active devctl/ioctl to finish before
proceeding.
The race possibility between unbind called from
suspend_all_serviceable_ch path and bind from ALLOC_GPFIFO should
be ruled out because ALLOC_GPFIFO has power refcount at the start
of devctl/ioctl and suspend_all_serviceable_ch is called from
prepare_poweroff path which ensure that power refcount is 0.
Removed nvgpu_smp_wmb().
Jira NVGPU-4927
Change-Id: Ic4f072df364926c10be84e42b83394c13fc97fdc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298959
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2020-12-15 14:13:28 -06:00
tkudav
029da0437e
gpu: nvgpu: Correct SCP_CTL reg read command
...
The offsets in minion register manuals are relative to minion base
address. Update the read command to use minion read API instead of
nvgpu_readl().
Change-Id: I6c0e2c11992f69e2fdd9e16dde061c92a771eae0
Signed-off-by: tkudav <tkudav@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292959
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2020-12-15 14:13:28 -06:00
rmylavarapu
9508cc6f42
gpu: nvgpu: sbr: Load and execute PUB
...
Implmented functions to load and execute PUB which
is the safety POR.
PUB has following functionality:
1) Lower PLM
2) Reset PMU
3) FBPA register access to devtools
Secure Boot and Runtime (SBR) microcode comprises of
single PLM Update Binary (PUB) which will execute on
SEC2 Engine Falcon. NVGPU shall load and execute PUB
and wait for falcon halt. On successful halt NVGPU
shall proceed with ns ucode loading on respective
falcons.
NVGPU-4549
Change-Id: I8ea897a026bbe2b1714823aba51bfa51864dd68a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292330
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2020-12-15 14:13:28 -06:00
shashank singh
0b4ccc7247
gpu: nvgpu: ignore deterministic submit flag for safety
...
Safety only supports usermode submits so there is no need to process
DETERMINISTIC submit flag. For safety, while processing DETERMINISTIC
submit flag we are only setting deterministic field of struct
channel_gk20a and taking power reference with gk20a_busy(). On qnx
safety deterministic field is just used to check the syncpoint
allocation and taking power reference is a noop.
Jira NVGPU-4378
Change-Id: I1dc256db7d9fab93bef8fcc42bdb36f611b3ef40
Signed-off-by: shashank singh <shashsingh@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284644
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2020-12-15 14:13:28 -06:00
Abdul Salam
8e840a5af1
gpu: nvgpu: Segregate clk unit members based on their accessibility
...
Current clk unit has multiple header files under include folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within clk unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_clk_inf.h from include which only
clk can access.
All public items are moved into include/clk.h which other units can
access and removed the clk_xxx.h files
NVGPU-4689
Change-Id: I469270ae539e09a3f6fe6187207791732407863e
Signed-off-by: Abdul Salam <absalam@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298220
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2020-12-15 14:13:28 -06:00
Seema Khowala
9ca89fa97f
gpu: nvgpu: gm20b: enable priv_ring interrupts for sim
...
Simulation platform supports priv_ring interrupts.
JIRA NVGPU-4864
JIRA NVGPU-5017
Bug 2848340
Change-Id: Ia37e7f6aa6ce6ab654772d7688243c8fe931a80d
Signed-off-by: Seema Khowala <seemaj@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2293680
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com >
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com >
Reviewed-by: Deepak Nibade <dnibade@nvidia.com >
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
sagar
8c04d2f000
gpu: nvgpu: skip classes in obj_alloc
...
Currently, we are performing obj ctx alloction for bellow classes
1. VOLTA_COMPUTE_A
2. VOLTA_DMA_COPY_A
3. VOLTA_CHANNEL_GPFIFO_A
In safety, we use Async CE but not GRCE.
So allocating obj context only for COMPUTE_A and return success(0) for
all other valid classes, after setting class in the channel struct.
Jira NVGPU-4378
Change-Id: Ie99872e062cc66f9ddf699397a13df85c3d8d59e
Signed-off-by: sagar <skadamati@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287486
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com >
Reviewed-by: Deepak Nibade <dnibade@nvidia.com >
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Abdul Salam
17cc9b2b98
gpu: nvgpu: Refactor Clock unit.
...
Current clk unit has multiple header files under pmuif folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within clk unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_clk_inf.h from pmuif which only
clk can access.
All public items are moved into include/clk.h which other units can
access
This will help in documentation of items for public items.
NVGPU-4491
Change-Id: Iccb0571e05ecb3cb13363390bed8c7214409b543
Signed-off-by: Abdul Salam <absalam@nvidia.com >
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292318
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2020-12-15 14:13:28 -06:00
