- In GV11B, read fuse_status_opt_tpc_gpc register
to read which TPCs are floorswept.
- The driver will also read sysfs node: tpc_pg_mask
- Based on these two values "can_tpc_powergate" will
be set to true or false and mask will be used to write to
fuse_ctrl_opt_tpc_gpc register to powergate the TPC.
- can_tpc_powergate = true indicates that the mask value
sent from userspace is valid and can be used to power gate
the desired TPC
- can_tpc_powergate = false indicates that the mask value
sent from userspace is not valid and cannot be used to
power gate the desired TPC.
Bug 200532639
Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2170736
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Rule INT31-C requires that integer conversions do not result in lost or
misinterpreted data.
Rule INT32-C requires that operations on signed integers do not result
in overflow.
Rule EXP34-C requires that pointer dereferences never include NULL.
Fix violations of these types in nvgpu.common.utils.
JIRA NVGPU-3868
Change-Id: Ifcf4bc6536ca2df2adcb53b40b3e58316cc3e457
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168576
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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Some recovery functions are currently exported in libnvgpu_safe.export.
Once CONFIG_NVGPU_RECOVERY is permanently disabled for safety build,
we can remove those functions from the export file.
Until we can disable it, make sure that related functions do exist,
even when CONFIG_NVGPU_RECOVERY is disabled, by using #ifdefs inside
the functions, instead of redeclaring functions as static inline.
Jira NVGPU-3871
Change-Id: Ib682ae81268b35cd1050a55cc73653fb6637b87c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2170433
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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As a part of safety check, golden context is created twice
(back to back) and two golden context images are compared.
These two images should be identical for safety check.
Currently there is one hw deviation happening because of stats
counter idle clock increments. To avoid this, stats counter
clocks enable is disabled. To have a valid golden context(
avoid mismatch between fe and mpc), original stats counter
bundle is programmed through mme shadow register.
Before first golden context save, golden image is saved in
a local copy. Same copy is restored back after first golden
save. Second golden context save is done with this local copy
and two golden contexts are compared.
JIRA NVGPU-3558
Change-Id: I5b5a1c5ff177e866a91cfc23618b118c157c8e95
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2167213
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Added helper function to compare two golden context images:
bool nvgpu_gr_global_ctx_compare_golden_images(struct gk20a *g,
bool is_sysmem,
struct nvgpu_gr_global_ctx_local_golden_image *local_golden_image1,
struct nvgpu_gr_global_ctx_local_golden_image *local_golden_image2,
size_t size);
In case of sysmmem, direct mem comparison can be used and for vidmem.
only word by word comparison can be done.
Since this code is used only for safety, all implementation is under
NV_BUILD_CONFIGURATION_IS_SAFETY flag.
JIRA NVGPU-3558
Change-Id: Ie3d0ac19e561b19d44e90a9d6188eaade0cdec44
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2167209
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Rule 11.3 forbids pointer cast between two different object types.
Rule 13.5 doesn't allow right hand operand of a logical operator to have
persistent side effects.
This patch fixes mentioned rules in nvgpu.common.mm.
Jira NVGPU-3864
Change-Id: I08b7fb4d3fb623f14f8760a50648b39b3e53b233
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168522
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There was a header file circular dependency that was preventing
including some files. For example, for utils.h to include safe_ops.h
would include bug.h which included log.h which included bitops.h which
included utils.h. To break this loop, the macro nvgpu_do_assert_print()
into a function in a new file assert.c. With this change, log.h is no
longer required in bug.h.
This change also required adding a few includes in C files that were
picking up definitions through the chain above.
JIRA NVGPU-3868
Change-Id: Icf95677bb36e4aa034cba25594cf71f2d028c289
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168528
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nvgpu_rc_pbdma_fault just checks for the id and id_type from struct
nvgpu_pbdma_status_info. These contain invalid values during chsw_load
and chsw_switch. This patch corrects the above bug by checking for the
chsw status and then loading the values for id and type.
The current code reads the pbdma_status info after clearing the
interrupt. Other interrupts can cause enough delay between clearing the
interrupt and pbdma switching the channel leading to invalid channel/tsg
ID. Correct that by reading the pbdma_status info register before
clearing of the pbdma interrupt to correctly read the context
information before the pbdma can switch out the context.
Bug 2648298
Change-Id: Ic2f0682526e00d14ad58f0411472f34388183f2b
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165047
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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INT30-C requires that unsigned integer operations do not wrap.
INT31-C requires checking that data isn't misinterpreted after casting.
INT32-C requires that signed operations do not overflow.
Jira NVGPU-3882
Change-Id: I6b4c1769ec85919f8ec2aa183cba3b7c0ffa1e97
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2166124
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If CONFIG_NVGPU_CE is disabled, nvgpu right now does not even reset
the CE engines or initialize prod values.
This ultimately needs to be fixed by adding appropriate initialization
for CE engines even if CONFIG_NVGPU_CE is disabled.
For now, add the code to at least reset CE engines if CONFIG_NVGPU_CE
is disabled
Bug 2526212
Change-Id: Id0a6fbfe44ef7af62715bcee65bef056359f1c19
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165861
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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INT30-C requires that unsigned integer operations do not wrap.
INT32-C requires that operations on signed integers do not result in
overflow.
FIO47-C requires use of valid format strings.
Fix CERT-C violations of these types in nvgpu.common.ecc.
JIRA NVGPU-3868
Change-Id: I72e15ae2e6d6a4db4e7e9971e13e143cf58b6dc4
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2164602
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Rule 2.2 doesn't allow unused variable assignments. The reason is
presence of unused variable assignments may indicate error in program's
logic.
Rule 21.x doesn't allow reserved identifier or macro names starting with
'_' to be reused or defined.
Jira NVGPU-3864
Change-Id: I8ee31c0ee522cd4de00b317b0b4463868ac958ef
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2163723
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Reduce code complexity of following functions in gr.falcon unit
nvgpu_gr_falcon_load_secure_ctxsw_ucode(complexity : 14 to 5)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create three sub functions from nvgpu_gr_falcon_load_secure_ctxsw_ucode function
Sub functions to do bootstrap during recovery and cold boot
Generalize sec2 and ls_pmu bootstrap to a single function.
gr_falcon_sec2_or_ls_pmu_bootstrap(with complexity : 4)
gr_falcon_recovery_bootstrap(with complexity : 4)
gr_falcon_coldboot_bootstrap(with complexity : 5)
and reduce nvgpu_gr_falcon_load_secure_ctxsw_ucode complexity to 5
Jira NVGPU-3662
Change-Id: I290580572d6c6dac6aa9bbd93b06c84ec3b93637
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165255
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Compile-out non-secure gr falcon boot related code for safety build by
adding non-secure gr falcon related code under following flag:
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
Added nvgpu_gr_falcon_load_ctxsw_ucode and related functions under
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT flag and enabled this flag only
for non-safety builds.
JIRA NVGPU-3741
Change-Id: I817d8a7be6a675eee514faf7bb93f1382c6da5ce
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158935
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Add documentation for channel functions used in safety build.
Made nvgpu_channel_commit_va return void, as it can never fail.
Removed nvgpu_channel_recover prototype (function moved to rc unit).
Compile out refcount tracking definitions when
GK20A_CHANNEL_REFCOUNT_TRACKING is disabled.
Removed unused nvgpu_channel_set_ctx_mmu_error function.
Jira NVGPU-3588
Change-Id: Ia65a6c60ff30837230d81ca0e5f6dadafcc3af4e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159674
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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emem related handling is specific to DGPU hence compile it out.
falcon_sw_init for platforms other than gv11b is also compiled
out.
Restored the DGPU falcons handling as the falcon common sw
init handling has case for initialization of unsupported
falcons that needs to be covered.
JIRA NVGPU-898
Change-Id: I41e886aba2aead052f3ef00278309759dd410df3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2160233
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- Added version and reseved elements in
nv_pmu_clk_clk_vin_device_boardobjgrp_set_header struct.
- Added volt_rail_idx, por_override_mode and override_mode
elements are added in nv_pmu_clk_clk_vin_device_boardobj_set
struct.
- Implemented parsing the above elements from vbios table.
- Moved from cmd to rpc in vin_load function.
- Changed the global macros of clk domain which matches to
PMU firmware for easy reference.
NVGPU-3743
Change-Id: I0189548fce19d65193203fbf6317c4a04147bf5a
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2163135
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-dGPU PMU init message interface updated to support RPC style init
PMU init message changed to RPC event & made needed changes to
handle RPC event during init stage
-Added new RPC header PMU_RM_RPC_HEADER, header from PMU to NvGPU
which will be part of RPC events received from PMU.
-GID info moved to super-surface for dGPU, so removed GID info
fetch from DMEM for dGPU & kept support for iGPU only.
-PMU_UNIT_INIT value for dGPU init changed
JIRA NVGPU-3723
Change-Id: I016bd1150494007a56905db23b4769e693ecd5da
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153141
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-Message header is added as part of FB message queue to have
sequence number & checksum to perform sanity check on
received message.
-Made required changes in structs to read message correctly
from data member offset but skipped to handle sanity checks
in code as NvGPU not needed for current supported messages .
-Added support to handle cmd/msg queue element changes.
JIRA NVGPU-3724
Change-Id: I85dccfab8902cbf71752582666931f482c3ec408
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155165
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reduce code complexity of following functions in common.gr.intr
nvgpu_gr_intr_stall_isr(complexity : 33)
nvgpu_gr_intr_handle_sm_exception(complexity : 17)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create five sub functions from nvgpu_gr_intr_stall_isr function.
Four of the sub functions based interrupt types.
One sub function for getting the channel information from context
gr_intr_get_channel_from_ctx(complexity : 4)
gr_intr_handle_exception_interrupts(complexity : 11)
This function complexity will reduce with NVGPU_DEBUGGER disable
gr_intr_handle_illegal_interrupts(complexity : 5)
gr_intr_handle_error_interrupts(complexity : 7)
gr_intr_handle_pending_interrupts(complexity : 3)
and reduce nvgpu_gr_intr_stall_isr complexity to 9
Create one sub functions from nvgpu_gr_intr_handle_sm_exception function
One sub function to report back any warp error.
gr_intr_report_warp_error(with complexity : 3)
and reduce nvgpu_gr_intr_handle_sm_exception complexity to 15
This function complexity will reduce with NVGPU_DEBUGGER disable
Jira NVGPU-3662
Change-Id: Ib325d9d8bca6b48766bc8a75f428dceeac495850
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2160578
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This patch adds the support to handle and report graphics related
exceptions to 3LSS. Specifically, it adds the following exceptions:
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_CROP
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_ZROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZCULL
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_SETUP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES0
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES1
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_PE
JIRA NVGPU-3457
Change-Id: Ib24b67ed33ae139317ec85bba3fbb80ba51fd384
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158609
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This patch reverts the following commit 13a7ef2cc7
The bios devinit for tu104 encountered the unaligned buffer scenario.
However bios devinit functionality is now removed from nvgpu. Other
than that there are no firmwares where we expect the input/output
buffer addresses to be un-aligned, hence removing the logic added
to handle un-aligned addresses.
JIRA NVGPU-3271
Change-Id: Ifd24cc5b50b9d2548878436befb2220e7bf02ed4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161735
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