Commit Graph

337 Commits

Author SHA1 Message Date
Debarshi Dutta
6ff92bfb6e gpu: nvgpu: Add wrapper over atomic_t and atomic64_t
- added wrapper structs nvgpu_atomic_t and nvgpu_atomic64_t over
  atomic_t and atomic64_t
- added nvgpu_atomic_* and nvgpu_atomic64_* APIs to access the above
  wrappers.

JIRA NVGPU-121

Change-Id: I61667bb0a84c2fc475365abb79bffb42b8b4786a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533641
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-08-17 14:26:47 -07:00
Alexander Lewkowicz
bacbc73312 gpu: nvgpu: gv11b: Fix computation of offset
When reading NV_PGRAPH_PRI_GPC0_TPC1_SM1_DBGR_STATUS0, we are not
reading the expected value. The offset of the sm is not added to the
PRI.

JIRA GPUT19X-75

bug: ?

Change-Id: I2eeb24505e928044c3a3331fa5f493a3f118a3c8
Signed-off-by: Alexander Lewkowicz <alewkowicz@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533953
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-08-15 08:20:25 -07:00
Sunny He
8ab6445df5 gpu: nvgpu: Reorg mm HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
mm sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I5fd295c6473d5b4a6178c0c6be8fcf8f4c33f2e3
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537754
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-08-14 15:55:25 -07:00
Sunny He
4bb0896912 gpu: nvgpu: Reorg fb HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
fb sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I3fdbf6059ef664caf8d33797a8a5f3f8eb6485bf
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537748
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-08-14 15:55:19 -07:00
Sunny He
de232ceb4b gpu: nvgpu: remove kind map inheritance
Currently, the kind map initialization inherits from earlier
chips' kind map definitions and simply adds on newly supported
features. This is dangerous as changes in older architectures
may affect newer architectures in unpredictable ways.

This patch removes inheritance between subsequent architectures'
kind map initializations.

Jira NVGPU-74

Change-Id: Iab504d45b6ce2e625ed6788e62c1e7104e45c89a
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537747
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-14 15:55:13 -07:00
Sandarbh Jain
78f1dac924 gpu: nvgpu: gv11b: PPC_IN_GPC_SHARED_BASE litter
Adding missing GPU_LIT_PPC_IN_GPC_SHARED_BASE litter value

Bug 1971835

Change-Id: If8851971ebea685fd6b3515b740aba8b64cae067
Signed-off-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1536084
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-14 15:55:12 -07:00
Sunny He
545363e342 Revert "gpu: nvgpu: gv11b: remove kind map inheritance"
Conflicts with gv100 changes

This reverts commit 2660d1d881.

Change-Id: Id64e1353069aab2155fb0688b55cc7ce3b092516
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537672
Reviewed-by: Shu Zhong <shuz@nvidia.com>
Tested-by: Shu Zhong <shuz@nvidia.com>
2017-08-11 14:57:32 -07:00
Sunny He
6486d4b8f1 Revert "gpu: nvgpu: gv11b: Reorg fb HAL initialization"
Conflicts with gv100 changes

This reverts commit da8e67f042.

Change-Id: Ifd1a51debc0e92fc443e6ac0aad1b224821d6585
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537669
Reviewed-by: Shu Zhong <shuz@nvidia.com>
Tested-by: Shu Zhong <shuz@nvidia.com>
2017-08-11 14:57:21 -07:00
Sunny He
a4e095aa37 Revert "gpu: nvgpu: gv11b: Reorg mm HAL init"
This reverts commit 96615351ad, which
conflicts with gv100 changes.

Change-Id: I08797bb23dd9226f0228ce3235fce6feef8d82f3
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537667
Reviewed-by: Shu Zhong <shuz@nvidia.com>
Tested-by: Shu Zhong <shuz@nvidia.com>
2017-08-11 14:57:08 -07:00
Sunny He
96615351ad gpu: nvgpu: gv11b: Reorg mm HAL init
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
mm sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Ic2c7d56e552645f2125d9c60a817967be1e8e765
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533355
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-11 14:16:53 -07:00
Sunny He
da8e67f042 gpu: nvgpu: gv11b: Reorg fb HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
fb sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I896d90e0dcffc0e133e6902ff9c3eab39c53080d
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533354
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-11 14:16:53 -07:00
Sunny He
2660d1d881 gpu: nvgpu: gv11b: remove kind map inheritance
Currently, the kind map initialization inherits from earlier
chips' kind map definitions and simply adds on newly supported
features. This is dangerous as changes in older architectures
may affect newer architectures in unpredictable ways.

This patch removes inheritance between subsequent architectures'
kind map initializations.

Jira NVGPU-74

Change-Id: I894e08da9acd288a4ea36282a2c7dc0b03bf9161
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533353
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-11 14:16:52 -07:00
Richard Zhao
3197a918d5 gpu: nvgpu: gv11b: add max_subctx_count to g->fifo.t19x
- For better performance. It used to read register every time referencing
  max_subctx_count.
- Avoid reading registers for vgpu.

Jira VFND-3797

Change-Id: Id6e6b15a0d9a035795e8a9a2c6bb63524c5eb544
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537009
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-11 11:08:41 -07:00
David Nieto
de8e057f7e gpu: nvgpu: GV100 support
Adds support of GV100 up to devinit.

JIRA: EVLR-1693

Change-Id: Ic7aa5f1c20714e05954139f143abb6a3459858fc
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1532747
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-11 11:07:17 -07:00
Peter Daifuku
026d1f8efe gpu: nvgpu: update gv11b_get_litter_value
Update gv11b_get_litter_value:
  - add PPC_IN_GPC_BASE
  - set all FBPA values to 0, since gv11b does not have an FBPA unit
  - error/bug if we fall through to default, for easier debugging

JIRA EVLR-1712

Change-Id: I9a388d6f525e101d4742ade07f972410ec3b2591
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533192
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-08-06 23:14:13 -07:00
Alex Waterman
5a5792d911 gpu: nvgpu: Remove mm.get_iova_addr
Volta changes for equivalent change on nvgpu.

JIRA NVGPU-30

Change-Id: I78e84ce67468dfe3556232ddb25e824f6b84835c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530863
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-08-04 14:54:26 -07:00
Terje Bergstrom
3e3c192040 gpu: nvgpu: gv11b: Make LTC disabling common code
Refactor the sync_debugfs LTC HAL op so that the logic to enable
or disable LTC goes to common code nvgpu_ltc_sync_enabled() and
the LTC HAL set_enabled only performs the hardware register access.

Create a new common function nvgpu_init_ltc_support() to initialize
the LTC software variable, and move hardware initialization of LTC to
be called from it.

JIRA NVGPU-62

Change-Id: I7b73625bccd45aefa5694989adbf4a0bbac75fc4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1529054
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-08-04 09:24:08 -07:00
Sunny He
f87007829f gpu: nvgpu: gv11b: Reorg regops HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
regops sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Ibf9f64ca445691e252b72c2b8fc59edb84e226ce
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530136
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Tested-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-02 14:43:28 -07:00
Deepak Nibade
ea381959d9 gpu: nvgpu: fix L3 alloc bit
Last minute rebase of commit afa31cdd8c on
top of reworked memory infrastucture introduced a bug where we actually
need to set BIT(36) in physical address but we ended up ORing the
address by "36"

Fix this by by adding correct value BIT(36) instead of 36

Jira GPUT19X-10
Bug 200279508

Change-Id: Ib587849c75f57dda5ad802b8389b7563b8b690ed
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1529511
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-02 10:46:31 -07:00
Ashish Srivastava
7c2b4d70ec gpu: nvgpu: gv11b: fix get ptr update for mmu fault buffer
Skipping the last entry makes get ptr 0.
This causes HW to think that buffer overflow has happened,
but it really hasn't. Due to this issue no further progress
is possible as all FB entries beyond get ptr are invalid.

Bug 200300788

Change-Id: I7373dfa087cdb7c307aacacf62ef4ca8a0214cf2
Signed-off-by: Ashish Srivastava <assrivastava@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1528070
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-02 10:46:29 -07:00
Sandarbh Jain
b859393ffe gpu: nvgpu: gv11b: fix no_of_sm
Number of sm is being reported incorrectly. This is because
we are not taking into account that each TPC have 2 sm.

Bug  1951026

Change-Id: I7c666aa2a0470a14aad29ab1a80ae9d23958a743
Signed-off-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1527771
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Lewkowicz <alewkowicz@nvidia.com>
Tested-by: Alexander Lewkowicz <alewkowicz@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-28 05:14:04 -07:00
Sunny He
f457e808f0 gpu: nvgpu: gv11b: Reorg therm HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
therm sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Ic297792c4d47ffbe64cc0bd95a659a6b7f383743
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1527423
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-07-27 16:34:46 -07:00
Sunny He
8aa0370005 gpu: nvgpu: gv11b: Reorg fecs_trace HAL init
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
fecs_trace sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I43932a8eac2a9f791e967a8ed736f76350889a51
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1527420
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-07-27 16:34:44 -07:00
Sunny He
afa29933e4 gpu: nvgpu: gv11b: Reorg gr_ctx HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
gr_ctx sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Icc6b0f968f2e3209de190d445c878a4b20bfcf4a
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1527418
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-07-27 16:34:44 -07:00
Sunny He
3c556c5e95 gpu: nvgpu: gv11b: Reorg ce2 HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the ce2
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Ia2d715a471d7e23420691a461e9442780176ea13
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1509633
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-07-27 16:34:37 -07:00
Sunny He
2b98e1308d gpu: nvgpu: gv11b: Remove privsecurity from gpu_ops
Replace privsecurity boolean flag in gpu_ops with entry in
common flag system.

The new common flag is NVGPU_SEC_PRIVSECURITY

Jira NVGPU-74

Change-Id: I4c11e3a89a76abe137cf61b69ad0fbcd665554b7
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1525714
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-26 02:45:15 -07:00
Sunny He
a5d6970df7 gpu: nvgpu: gv11b: Remove securegpccs from gpu_ops
Replace securegpccs boolean flag in gpu_ops with entry in
common flag system.

The new common flag is NVGPU_SEC_SECUREGPCCS

Jira NVGPU-74

Change-Id: I487aa5e8545027a3b5bbe33ce68b2715cc2eb39a
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514096
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-26 02:44:23 -07:00
Sunny He
8140c51e6c gpu: nvgpu: gv11b: Reorg fifo HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the fifo
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I7c81edfa785a4ecafef41aae7b82d6b1707d294e
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1522554
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-23 23:35:06 -07:00
Sunny He
d9f906c1e0 gpu: nvgpu: gv11b: Reorg priv_ring HAL init
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
priv_ring sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Idee9e8a3a5bfa65b350f0e9fb14c4364c4d6f1d2
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514103
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-23 23:35:06 -07:00
Sunny He
e932982853 gpu: nvgpu: gv11b: Reorg bus HAL init
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
bus sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I469113b204cb693a6b1cbf34a9ca53b62e34ec20
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514661
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-23 23:35:05 -07:00
Sunny He
3b7d50ee12 gpu: nvgpu: gv11b: Reorg css HAL init
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
css sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Change-Id: I04177d6c9eb4f3c433d493c815ad15cf7b755910
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514206
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-23 23:35:05 -07:00
Seema Khowala
8b571de456 gpu: nvgpu: gv11b: implement init_gpc_mmu
- Created HAL to configure gpc mmu unit for gv11b.
- Earlier chips needs writes to NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS
  register to know supported number of LTCS by reading NUM_ACTIVE_LTCS
  but gv11b support auto update from fuse upon reset, so skipped
  LTCS update for GPCS & skipping helps to fix compression failure
  issue.

Bug 1950234

Change-Id: I628af7d1399e4fe3126895e3a703a19147f7a12f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1517733
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-20 00:20:56 -07:00
Seema Khowala
357e3d4d38 gpu: nvgpu: gv11b: fix for replay fault addr equal to 0
fault_addr "0" is not supposed to be fixed ever.
For the first time when prev = 0, next = 0 and
fault addr is also 0 then handle_mmu_fault_common will
not be called. Fix by checking fault_addr not equal to 0

Bug 200277163

Change-Id: I532bca54a85e540415b9f5f5e71daec9cf0e0619
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1522653
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-18 23:42:08 -07:00
Seema Khowala
7ab28a4184 gpu: nvgpu: gv11b: support egpc and etpc context regoptype
- implement is_egpc_addr, is_etpc_addr and get_egpc_etpc_num gr ops
- implement decode and create priv addr for egpc/etpc

JIRA GPUT19X-49
Bug 200311674

Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Change-Id: Ia0cef51b2064df28460711185cd90b60aac03e4f
Reviewed-on: https://git-master.nvidia.com/r/1522450
GVS: Gerrit_Virtual_Submit
Reviewed-by: Tushar Kashalikar <tkashalikar@nvidia.com>
Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-18 23:42:08 -07:00
Seema Khowala
c7d48710b0 gpu: nvgpu: gv11b: init access_smpc_reg gr ops
This is needed to support t19x smpc register addresses

JIRA GPUT19X-49
Bug 200311674

Change-Id: I67146d997d96eeca4344ed0fb4cabbc216461c6c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1508543
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-18 23:42:01 -07:00
Seema Khowala
4df5427c15 gpu: nvgpu: gv11b: init perf related gr ops
Implement gv11b specific perf gr ops

JIRA GPUT19X-49
Bug 200311674

Change-Id: Ia65fe84df6e38e25f87d2c1b21c04b518c334d42
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1497402
GVS: Gerrit_Virtual_Submit
Reviewed-by: Tushar Kashalikar <tkashalikar@nvidia.com>
Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-18 23:41:54 -07:00
Seema Khowala
68b65f642a gpu: nvgpu: gv11b: h/w header updated for CL 38810810
H/w header updates for FPGA SNAP_0617

Change-Id: I6d3fe0b5b36de5999b09b9aa65e6dde2817634b5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1515766
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-17 02:35:56 -07:00
Seema Khowala
81274038a4 gpu: nvgpu: gv11b: updated clock gating prod settings
Updated clock gating prod settings for HW CL 38810810

Change-Id: Ie0769edb41b46e323b042a654e6002a4f7044030
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1517514
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-17 02:35:53 -07:00
Lauri Peltonen
2272cedfba gpu: nvgu: Support SET_BES_CROP_DEBUG3 sw method
The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields
in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register.  The sw method is
used by the user space driver to disable enough ROP optimizations
to maintain ZBC state of target tiles.

Bug 1942454

Change-Id: I3109fb4120674b15db4998693d0aa65bf0c3c8b5
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1516205
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-07-14 02:54:35 -07:00
Sunny He
4074484f75 gpu: nvgpu: gv11b: Reorg debug HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch covers the debug
and dbg_session_ops sub-modules of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I23cda2fbb47fb41975a4a938e352a7427853be94
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514820
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-13 00:09:09 -07:00
Sunny He
2f0838af1b gpu: nvgpu: gv11b: Move gops.mc's non-fp members
Move non-function pointer members out of the mc substruct of
gpu_ops. Ideally gpu_ops will have only function ponters, better
matching its intended purpose and improving readability.

gops.mc.intr_mask_restore is now mc_intr_mask_restore

Jira NVGPU-74

Change-Id: I789087704fb5e6338f6010f18457948d0ee6c630
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1509604
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-13 00:09:09 -07:00
Sunny He
4e290320fd gpu: nvgpu: gv11b: Reorg mc HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the mc
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I1a5abde46bf079c206dfdf9f8ee35df048565c49
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1509603
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-13 00:09:09 -07:00
Sunny He
aade61eff9 gpu: nvgpu: gv11b: Reorg falcon HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
falcon sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: If980fcd2605a445bd623a5fcca8262826ce289c4
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514013
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-13 00:09:08 -07:00
Seema Khowala
df022d27dd gpu: nvgpu: gv11b: support SET_SKEDCHECK s/w methods
Support sw method NVC397_SET_SKEDCHECK and NVC3C0_SET_SKEDCHECK
data fields are
data:0 SKEDCHECK_18_DISABLE
data:1 SKEDCHECK_18_ENABLE

Bug 200315442

Change-Id: I0652434ab0b4d6e49dab94be329072861e99c38c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1515772
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-12 22:15:19 -07:00
Seema Khowala
66fb130bfd gpu: nvgpu: gv11b: recover from replay and ce mmu fault
Fix pte valid bit for replayable fault and ce fault

JIRA GPUT19X-12

Change-Id: I77a7a452d9b5b304f182e120e8d75959d46d4422
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1515538
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-12 07:44:49 -07:00
Seema Khowala
971c90e3b6 gpu: nvgpu: gv11b: set replay fault for tex and gcc
This is to enable replay fault from tex and gcc engines

JIRA GPUT19X-7
JIRA GPUT19X-12

Change-Id: I0cc8a59499da9eb056d19ee8d6cd33a94e3f0835
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1493407
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-12 07:44:46 -07:00
Seema Khowala
cdae0f1379 gpu: nvgpu: gv11b: check bar2 bind_status
This is needed as BAR1 support is removed and
there is no way to know if gpu successfully accessed memory.

JIRA GPUT19X-115

Change-Id: I5d18b6bf73e11b103d1951d2e28fb1f895e72c85
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1515813
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-11 12:15:05 -07:00
Seema Khowala
cc940da42f gpu: nvgpu: gv11b: enable and handle mpc exception
Implement gr ops to handle MPC exception triggered per TPC

JIRA GPUT19X-69

Change-Id: Ia92b1d51ad896116b25d71e07ed26f1539475be8
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1515915
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
2017-07-09 23:34:19 -07:00
Seema Khowala
d9ee7aff04 gpu: nvgpu: gv11b: fifo recovery for nonreplay fault
Host will no longer receive replayable or non-replayable fault requests.
MMU will handle both types of fault reporting. This means that Host will no
longer automatically disable scheduling or preempt a PBDMA when an engine
page faults. After fault happens, engine will stall on its own fault and
will not context switch until the fault is serviced

JIRA GPUT19X-7

Change-Id: I8039e6f50d87f43e101d1372faa5ca6fb739036e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1493417
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-07-08 11:35:48 -07:00
Seema Khowala
2f6d321390 gpu: nvgpu: gv11b: add mmu fault handling
HUB reports following memory sub-system interrupts:
a) ACCESS_COUNTER_NOTIFY:
   GET != PUT for access counter notify buffer
b) ACCESS_COUNTER_ERROR:
   HUB received a NACK (BAR2 fault) when writing the
   notify buffer out to memory
c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY:
   Uncorrected ECC error detected by HUB MMU
d) MMU_REPLAYABLE_FAULT_NOTIFY:
   GET != PUT for replayable fault buffer
e) MMU_REPLAYABLE_FAULT_OVERFLOW:
   Overflow when writing to the replayable fault buffer
f) MMU_NONREPLAYABLE_FAULT_NOTIFY:
   GET != PUT for non-replayable fault buffer
g) MMU_NONREPLAYABLE_FAULT_OVERFLOW:
   Overflow when writing to the non-replayable fault buffer
h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU

This change is to :
-Detect other fault notify
-Copy fault info from fault snap register for other fault notify
 interrupt
-Detect and handle nonreplay/replay fault notify and fault overflow
-Copy fault info from fault buffer for nonreplay/replay fault
-Print fault info

JIRA GPUT19X-7
JIRA GPUT19X-12

Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1493394
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-07-08 11:35:48 -07:00