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3031 Commits

Author SHA1 Message Date
Seshendra Gadagottu
002fb2431d gpu: nvgpu: nvgpu-next changes for fifo pbdma 
- Include nvgpu_next_pbdma.h in pbdma.h
- NULL check for fifo.init_pbdma_map hal before allocating
  memory for f->pbdma_map
- NULL check for f->pbdma_map before freeing memory for
  f->pbdma_map

JIRA NVGPU-4979

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I5eacc671b924c947620b2c49c8f82577c30ba1a3
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317804
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Seema Khowala
b7767a604f gpu: nvgpu: add intr_top_enable fifo gops 
This is required for enabling fifo interrupts for nvgpu-next.

JIRA NVGPU-4864

Change-Id: I5c09105296a01b82505023ecf576d71ce74f7a31
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313013
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
d0ffb335dc gpu: nvgpu: move nvgpu_has_syncpoints 
nvgpu_has_syncpoints is more general than a channel synchronization
related, so move it to nvhost.c from channel_sync.c. Move the
declaration from gk20a.h to nvhost.h.

As the debugfs knob is Linux related, move it from struct gk20a to
struct nvgpu_os_linux.

Jira NVGPU-4548

Change-Id: I4236086744993c3daac042f164de30939c01ee77
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318814
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
88c774e5d1 gpu: nvgpu: enable clk_arb for dGPU safety 
Enable CONFIG_NVGPU_CLK_ARB for dGPU safety build.

Use CONFIG_NVGPU_NON_FUSA for invocation of non-safe functions:
- nvgpu_hr_timestamp
- nvgpu_hr_timestamp_us

Jira NVGPU-4661
Jira NVGPU-5235 (for addressing usage of above functions).

Change-Id: I271fdbc45c1e4d01cb70d50dcf63d15b9df33c76
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317842
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
28ccd63f69 gpu: nvgpu: enable CONFIG_NVGPU_LS_PMU for safety 
Enable CONFIG_NVGPU_LS_PMU for dGPU safety build.
Add missing #ifdefs for CONFIG_NVGPU_POWER_PG and
CONFIG_NVGPU_CLK_ARB which are not defined for safety build.

Moved gm20b_mc_is_enabled to fusa code.

NVGPU_UNIT_PWR is only defined when CONFIG_NVGPU_HAL_NON_FUSA
is defined. Added #ifdefs to compile out gk20a_pmu functions
that are using it.

Jira NVGPU-4661

Change-Id: Ieb552f9374bad6f3dad777322f118931e0bc94ec
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317085
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
46761356e5 gpu: nvgpu: make channel sync ops const 
The function pointers for the syncpoint and semaphore implementations of
struct nvgpu_channel_sync do not change in runtime. Make this more
explicit by having the pointers in predefined private structures. Each
instance of a sync (which there are one per open channel) gets a pointer
to an ops structure instead of a list of all the individual ops.

Jira NVGPU-4548

Change-Id: I361b74bdfe32470203760d11c30e048cb4d20b77
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318242
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 2020-12-15 14:13:28 -06:00
Abdul Salam
4f5bd9e633 gpu: nvgpu: Implement clk_good and pll_lock check 
Add clk_good and pll_lock check as a part of fmon polling.
This will poll for any clock related faults at FTTI interval.
Add new function to poll for vbios init completion.

NVGPU-4967
Bug 2849506
Bug 200564937

Change-Id: I5bc885329981e07376824e148edabe9be4120e1c
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2305782
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 2020-12-15 14:13:28 -06:00
Seema Khowala
21e2214c3d gpu: nvgpu: support nvgpu-next intr config 
JIRA NVGPU-4864

Change-Id: I2fb5be3270c73ea891021161f539a7f731e05f63
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
a5b3170c6f gpu: nvgpu: Refactor allocator lite unit 
- Changed the names of structs as per private/public
  naming convention.
- Renamed allocator.c file

NVGPU-4487

Change-Id: I42ec5730f1cb0029a6bb6e6ddff151bd08d6bbd8
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316945
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
f43d5df83a gpu: nvgpu: build dGPU in safety 
Enable build flags for dGPU in safety, when
NVGPU_FORCE_DGPU_SAFETY_PROFILE is set.

Use libnvgpu-dgpu_safe.exports for dGPU safety build.

Add build flags for tu104 HAL initialization (to solve
undefined symbols in safety build).

Temporarily add non-fusa files needed to build dGPU in safety.
related functions will have to move to fusa files.

Jira NVGPU-4611

Change-Id: I41db0c039c7f15d9191cdb811b4906e779d5cc88
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310276
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 2020-12-15 14:13:28 -06:00
rmylavarapu
f5acc98db3 gpu: nvgpu: Refactor Super surface lite unit 
- Changed the names of structs as per private/public
  naming convention.
- Removed unwanted code in struct super_surface.

NVGPU-4486

Change-Id: I5834c2296ccbe1545bca6a608ad88817a9104fb8
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313989
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 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
1f6dfb54d1 gpu: nvgpu: Remove hard coded constants from ACR 
During code inspection use of some hard constants was
found in some parts of the code.
Those constants are replaced by macros

JIRA NVGPU-5030

Change-Id: I09212be40746317440218bc7ada9a578dde7c6ed
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
8ec4395e82 gpu: nvgpu: build flag for deterministic channel 
Add CONFIG_NVGPU_DETERMINISTIC_CHANNELS and fix
preprocessor #ifdefs to allow compiling kernel mode
submit without deterministic feature enabled.

Jira NVGPU-4661

Change-Id: I4aa678715824e8981d39bd8db0c5ae61ef3a675c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310325
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
bf353cea6c gpu: nvgpu: sim_pci: reconcile sim escape paths between RM and nvgpu 
SIM models are getting updated to have same escape read path
for RM and nvgpu. Updated nvgpu driver code to have same escape
read mechanism as RM for dgpu.

Required for dgpu to work on NET23.

Bug 2539889
Bug 200582707

Change-Id: Ied05dae00928d44249df695429fb5029331f1286
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2256665
Reviewed-by: Lakshmanan M <lm@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
7aa9e90bfc gpu: nvgpu: update gops.cg 
Update gops.cg to include following runlist level cg ops:
- blcg_runlist_load_gating_prod
- slcg_runlist_load_gating_prod

Jira NVGPU-5048

Change-Id: Ia2a3f887d5c2fd6f1dd35d606afd19d117468c2c
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300448
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
00eec69b3f gpu: nvgpu: add hal to get_ctx_buffer_offsets 
Currently, gr_gk20a_get_ctx_buffer_offsets is defined as a function.
However, this function is used in the common code. So, add new GR hal
to get_ctx_buffer_offsets.

Jira NVGPU-5047

Change-Id: I0cec6ff19194fa726722e6af3a2f11a188dc9087
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
a182be7b8d gpu: nvgpu: add ctxsw_reg bundles for nvgpu-next 
Add ctxsw_reg bundle programming for nvgpu-next.

Jira NVGPU-5047

Change-Id: I3df9d89a6615825d224ec5d46b550cd68623e7d7
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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Seshendra Gadagottu
3d5162f01c gpu: nvgpu: enable fe auto go idle for nvgpu-next 
Enable fe auto go idle feature for nvgpu-next.

JIRA NVGPU-5135

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I5afecea8e039be90424e1bee6e1fd20a2584576b
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 2020-12-15 14:13:28 -06:00
rmylavarapu
147564cbd5 gpu: nvgpu: NVGPU migration to support latest ucode 
Changes:
- Send down BOARDOBJGRP classId to the PMU. Assign each
  BOARDOBJ the classId of its parent group which is set
  to zero in current implementation. Changed in NVGPU to send
  board obj grp classid to PMU.
- Disable IPC VMIN support as pmu-tu10a profile doesn't support.
- Change in clk vf point enumeration types.
- Change in pstate type values.
- Updated ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info
  NVGPU-PMU interface struct with b_ver_expected_is_mask to send
  whether the expected version is single value or should be
  interpreted as a bit mask with bits corresponding to
  expected versions set.

NVBUG-200593676
NVGPU-5066

Change-Id: I17b172d88f8b74fbf78044caf7f64cd8811f9fb7
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
c79522d452 gpu: nvgpu: gr: enhance firmware method error message 
Dump set_falcon method, class and whitelist register
being accessed.

Bug 200594051

Change-Id: Ic7fe014ba917a23b1ca9474bf5bd1d231f7ed60f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
dc32307c13 gpu: nvgpu: Rename therm public struct 
Renamed therm public struct to match with the other
units.

NVGPU-4449

Change-Id: I675ce43b136139420b8cc1eecdc395d9165d9f30
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
2e4fb38870 gpu: nvgpu: add eng_config hal for nvgpu_next 
Add gr.eng_config hal for nvgpu_next.

Jira NVGPU-5049

Change-Id: Ieb342cb0416f965a3f80e3a6e3f0f43a853485ff
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
5fa0d7f994 gpu: nvgpu: add bundle programming for nvgpu_next 
Update bundle programming for nvgpu_next.

JIRA NVGPU-5004

Change-Id: I1c452a9e78cd018de86fb57de10291c4411e7d89
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
e424e4791a gpu: nvgpu: perf: Refactor Perf unit 
-Renamed and moved nvgpu_pmu_perf struct from public
to unit specific
-Renamed all functions as per public/private format

NVGPU-5029

Change-Id: If3f479bb1443850a5c8a8714cd1c9da346cb566a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300609
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
14f268563a gpu: nvgpu: add gr.zbc hal for nvgpu_next 
Add gr.zbc hal for nvgpu_next

Jira NVGPU-5084

Change-Id: I678dac83ea67818e1b657b22840f3f4a04584ba8
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2304195
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Seeta Rama Raju
551b3bebe8 gpu: nvgpu: Add 0x if falcon data is 0000000 
- When the falcon data is 00000000, the dump does not add 0x while printing.

Bug 200586923

Change-Id: I9fda75258290a85b0e4c38f426adc4474d88cdd8
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306485
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Philip Elcan
20a4080be0 gpu: nvgpu: quiesce: stop thread gracefully 
Previously, nvgpu_sw_quiesce_remove_support() stopped the quiesce
thread abruptly with nvgpu_thread_stop(), which could mean the thread
was killed while still waiting on the cond. Then when the cond was
destroyed, there may be an error since the underlying implementation may
think there is still a thread waiting (such as the Posix
implementation).

Change nvgpu_sw_quiesce_remove_support() to use
nvgpu_thread_stop_graceful() and signal the cond in the callback after
the thread is marked to be stopped. The quiesce thread will then wake up
from the cond wait and see the thread should stop.

JIRA NVGPU-4987

Change-Id: I29322d7867acc33a91092016c540e00bb1ae945a
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306024
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
sagar
88e27271eb gpu: nvgpu: fix static analysis issues 
coverity tool is not detecting the lenght validation done at caller.
moved length checks to appropriate functions.

used macro instead of hardcoded values.

Jira NVGPU-4780

Change-Id: Ie6b420a6e625eed5374715fd7ca5c87d3ba3d015
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2302335
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Sagar Kamble
630eaa46cb gpu: nvgpu: update the config options & makefile 
Added dependency between the Kconfig options as follows where
'->' indicates 'depends on' relation:

SUPPORT_CDE -> COMPRESSION -> DMABUF_HAS_DRVDATA
DGPU -> GK20A_PCI

Defined Kconfig option for VPR and for DGPU that is dependent GK20A_PCI
as well. DGPU related sources are now compiled under config flag DGPU.
Also update conditional compilation of the driver paths w.r.t DGPU,
VPR and COMPRESSION flags.

Bug 2834141

Change-Id: Ia0a39d6d4cf8b36e7f955b7355a5ab41783f821c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299627
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
rmylavarapu
a23d0c1c19 gpu: nvgpu: Check for timeout and indicate error 
For every copy_back enabled PMU cmd sent by NVGPU
we are waiting for PMU response but not checking
for timeout error. This will result in copying invalid
data which causes errors. Implemented timeout check
and return error if timedout.

NVBUG-200530426

Change-Id: I32eba16eeb6f7a56724329ab6d85fae062c6fa3f
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2258947
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
ed33c465d5 gpu: nvgpu: Check for ACK from PMU before timeout 
At present in NVGPU for every get_status cmd we wait
for a response from PMU else timeout. In present code
we look for the ACK very early then after processing
the interrupts, this may result in timeout with valid
response from PMU. To avoid this timeout a check for
ACK is implemented before every timeout check.

NVBUG-200530426

Change-Id: I6f8df51ab73066953ef7c9c05c61aaf543e53b52
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2258899
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Abdul Salam
29d4831780 gpu: nvgpu: Segregate volt unit members based on their accessibility 
Currently all unit specific private members are inside ucode_volt_inf.h.
This patch moves the members specific to pmuif to ucode_volt_inf.h and
local to volt.h.
Append all unit specific local functions with volt/nvgpu.
Move volt specific rpc handler from g->pmu to g->pmu->volt.

NVGPU-4492

Change-Id: I626e002b3876c6c5330dec4396b7661b986c6119
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299555
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
43324f7b1b gpu: nvgpu: Reconcile sim escape paths between RM and nvgpu 
SIM models are getting updated to have same escape read path
for RM and nvgpu. Updated nvgpu driver code to have same escape
read mechanism as RM.

This is required for igpu to pass on NET21.

Bug 2539889

Change-Id: I5d37ceb799cafb7fc7dec611fda5f5caac7d7f17
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2130414
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Lakshmanan M <lm@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Rajesh Devaraj
50d71f7c56 gpu: nvgpu: report fecs ctxsw init error 
This patch adds callback to report fecs ctxsw init error to 3LSS.
It also moves the related wrapper function to nvgpu_err header
file and adds doxygen documentation.

JIRA NVGPU-5042

Change-Id: I2a051cf19c2940859169799a4dd51adf8870eff4
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300003
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
d0d8ef79d1 gpu: nvgpu: use READ_ONCE/WRITE_ONCE 
In the upstream kernel ACCESS_ONCE is now deprecated with reason as
given in the following related commit:

    commit 381f20fceba8e ("security: use READ_ONCE instead of deprecated
    ACCESS_ONCE")

    ACCESS_ONCE() does not work reliably on non-scalar types. For
    example gcc 4.6 and 4.7 might remove the volatile tag for such
    accesses during the SRA (scalar replacement of aggregates) step.

Replace usages of ACCESS_ONCE with READ_ONCE and WRITE_ONCE in nvgpu.

Bug 2834141

Change-Id: I9904c49e1a4d7b17ed2fe54360051d08595a2982
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294096
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
rmylavarapu
9508cc6f42 gpu: nvgpu: sbr: Load and execute PUB 
Implmented functions to load and execute PUB which
is the safety POR.
PUB has following functionality:
1) Lower PLM
2) Reset PMU
3) FBPA register access to devtools

Secure Boot and Runtime (SBR) microcode comprises of
single PLM Update Binary (PUB) which will execute on
SEC2 Engine Falcon. NVGPU shall load and execute PUB
and wait for falcon halt. On successful halt NVGPU
shall proceed with ns ucode loading on respective
falcons.

NVGPU-4549

Change-Id: I8ea897a026bbe2b1714823aba51bfa51864dd68a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292330
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Abdul Salam
77c220c1ae gpu: nvgpu: Convert define to funtions in clk unit 
As a part of refactoring this patch does the following
*Convert #define to functions, This will help in unit testing
*Remove #define which are not needed
*Merge all clk subunits to single clock unit in yaml

NVGPU-4492

Change-Id: If3f3dbd714e710398c0f860f4d5022675136db8c
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298874
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
shashank singh
0b4ccc7247 gpu: nvgpu: ignore deterministic submit flag for safety 
Safety only supports usermode submits so there is no need to process
DETERMINISTIC submit flag. For safety, while processing DETERMINISTIC
submit flag we are only setting deterministic field of struct
channel_gk20a and taking power reference with gk20a_busy(). On qnx
safety deterministic field is just used to check the syncpoint
allocation and taking power reference is a noop.

Jira NVGPU-4378

Change-Id: I1dc256db7d9fab93bef8fcc42bdb36f611b3ef40
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284644
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Abdul Salam
8e840a5af1 gpu: nvgpu: Segregate clk unit members based on their accessibility 
Current clk unit has multiple header files under include folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within clk unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_clk_inf.h from include which only
clk can access.
All public items are moved into include/clk.h which other units can
access and removed the clk_xxx.h files

NVGPU-4689

Change-Id: I469270ae539e09a3f6fe6187207791732407863e
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298220
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Nitin Kumbhar
9770723639 gpu: nvgpu: add checks for kzalloc() allocations 
Check kzalloc() allocations for failures and return
an error if an allocation fails.

Bug 2279948

Change-Id: I8a2c3b84904da897ad6118900c11489c8656c20f
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2020123
(cherry picked from commit fadd0014da)
(cherry picked from commit 73254fc51281370b2bcce06b3e890d8da725d8d5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298097
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
sagar
8c04d2f000 gpu: nvgpu: skip classes in obj_alloc 
Currently, we are performing obj ctx alloction for bellow classes

 1. VOLTA_COMPUTE_A
 2. VOLTA_DMA_COPY_A
 3. VOLTA_CHANNEL_GPFIFO_A

In safety, we use Async CE but not GRCE.
So allocating obj context only for COMPUTE_A and return success(0) for
all other valid classes, after setting class in the channel struct.

Jira NVGPU-4378

Change-Id: Ie99872e062cc66f9ddf699397a13df85c3d8d59e
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287486
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Abdul Salam
17cc9b2b98 gpu: nvgpu: Refactor Clock unit. 
Current clk unit has multiple header files under pmuif folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within clk unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_clk_inf.h from pmuif which only
clk can access.
All public items are moved into include/clk.h which other units can
access
This will help in documentation of items for public items.

NVGPU-4491

Change-Id: Iccb0571e05ecb3cb13363390bed8c7214409b543
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292318
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
406913dc42 gpu: nvgpu: gr: zbc: add hal for zbc_table_size 
Currently, size of zbc index table is defined as a macro. This macro is
independent of the number of address bits in the ltc zbc index register.
Adding below hal will update zbc index table size as per number of
address bits.

Add hal to get gr_zbc_index_table_size:
u32 (*zbc_table_size)(struct gk20a *g);

ZBC index table address 0 is reserved. Logic to start zbc table index
from 1 is moved to corresponding hals.

JIRA NVGPU-4838

Change-Id: I700cadfdd1f3dc5f323055b8f44d769d6627920a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2288479
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
ec34e87573 gpu: nvgpu: extend runlist_info for nvgpu-next 
Extend runlist_info for nvgpu-next.

JIRA NVGPU-4971

Change-Id: I0043eff4df688c4131a0919500fef0dff3419a58
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292686
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
31ba194a85 gpu: nvgpu: extend engine_info for nvgpu-next 
Extend engine_info for nvgpu-next.

JIRA NVGPU-4970

Change-Id: I0e8e5ae9361776a48972ae6d0cee84ece19d7590
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2291811
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Nicolas Benech
30755fef04 gpu: nvgpu: mm: use constants for string lengths 
For VM and allocator names, hardcoded constants were used which
can be a weakness. This patch uses proper defines in headers
instead.

JIRA NVGPU-4946

Change-Id: I1cc100a558d0c44c208a7e579cc36b71a0d4eeec
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2291069
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Nicolas Benech
e8c02f121b gpu: nvgpu: vm: plausibility check for nvgpu_vm_bind_channel 
Ensure that the channel pointer passed to nvgpu_vm_bind_channel
is not NULL.
Update unit test accordingly.

JIRA NVGPU-4947.

Change-Id: I3f987ee9042066df83cc6101b20b4add3661fae8
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2291034
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Nicolas Benech
16b80d2c5c gpu: nvgpu: pd_cache: add BUG_ON to guard divide by 0 
In the unlikely event of a corruption of pentry->pd_size this new
BUG_ON prevents a potential divide by 0. This change is mostly to
increase safety as it is unlikely for a divide by 0 to occur in this
instance.

JIRA NVGPU-4949

Change-Id: Ibdf80670f35a63dd20d06082cde23fb424931933
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2291022
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Lakshmanan M
e445d08022 gpu :nvgpu : Add waiter index in syncpt_wait_ext 
Allocated the following two waiter objects for sync point waith path:
Job tracking and CE threads.
 2. QNX channel specific job tracking thread.
The above implementation is only available for QNX.
For Linux, waiter index is skipped.

JIRA NVGPU-3009

Change-Id: If12ad1dc90a24a7b922b205829ca335805c02c3d
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292080
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
14ce94df43 gpu: nvgpu: divide functions to reduce complexity 
This patch divides nvgpu_init_mm_setup_sw() and
nvgpu_vm_init_vma_allocators() functions to reduce code complexity.

Jira NVGPU-4780

Change-Id: I3d94cf44aee2e5e43471b97055c51fa2b0f83d52
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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