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2272 Commits

Author SHA1 Message Date
Sagar Kamble
705dd2ad77 gpu: nvgpu: use timespec64 
Due to y2038 problem, where timestamps will overflow if logged in 32bit
values, upstream linux kernel has removed timespec and friends.

Correpsonding jiffies conversion functions are also obsolete. Update
the notifier timestamp setup code to comply with this.

Bug 2925664

Change-Id: I5266e3d748e536175af8eff5111fcc54556332a8
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2326514
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Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Vinod G
4ffcc14e90 gpu: nvgpu: support gr_exception_mme_fe1 error 
Add GPU_PGRAPH_MME_FE1_EXCEPTION definition to
report the gr_exception_mme_fe1 error.

Jira NVGPU-5226

Signed-off-by: Vinod G <vinodg@nvidia.com>
Change-Id: I963586f8335ea99159e379b260679f060c2cf3c9
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2326228
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Dinesh
8a94781aa9 gpu: nvgpu: Change pramin lock to mutex 
As spinlock contention will eat cpu cycle, the pramin lock
can be changed to mutex.
Vidmem allocation is fully protected and vidmem pending is
an atomic variable. So the lock acquisition is removed.


JIRA NVGPU-4550

Change-Id: I0cecb8f4ee7e840fd698311572aedebbc8f49177
Signed-off-by: Dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321251
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
ad503f60fd gpu: nvgpu: gv11b: add missing hw macros 
Add following missing hw macros for gv11b:
- pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v
- pri_ringstation_gpc_gpc0_priv_error_info_subid_v
- pri_ringstation_sys_priv_error_info_priv_level_v
- pri_ringstation_sys_priv_error_info_subid_v

Bug 200604892

Change-Id: I37fa33580b689a496ed0a74855a58291d626e341
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325347
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
2d9b839f21 gpu: nvgpu: remove user sync related apis 
Set safe state and get syncpt address in the kernel submission tracking
syncs was implemented for userspace syncs. Now that it's clear that the
user sync object provides them, there are no users left for these APIs.
Remove them.

Jira NVGPU-4548

Change-Id: I58e04162dee55bb8d8547c9252033f40ed908144
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321950
(cherry picked from commit a95c8f7ace562a11ca235d71496d3a7ce150bc7d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2324251
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
60e1cf334a gpu: nvgpu: include linux/mm.h in utils 
Linux's mm.h defines at least PAGE_ALIGN which nvgpu uses and provides
via utils.h. It's defined internally in posix/utils.h, but in Linux the
OS version is relied upon. However, the macro definition has spilled in
via the trace events that includes linux/ktime.h. If nvgpu/trace.h isn't
included, we wouldn't get that.

Jira NVGPU-4548

Change-Id: I9c27cc9db15231714d38d7c623957c8f5fe52789
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321362
(cherry picked from commit 84762ce74847a3b0983901b6cf3f5d3110abd6cc)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2324246
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
4f80c6b8a9 gpu: nvgpu: add channel_user_syncpt 
Refactor user managed syncpoints out of the channel sync infrastructure
that deals with jobs submitted via the kernel api. The user syncpt only
needs to expose the id and gpu address of the reserved syncpoint. None
of the rest (fences, priv cmdbufs) is needed for that, so it hasn't been
ideal to couple with the user-allocated syncpts.

With user syncpts now provided by channel_user_syncpt, remove the
user_managed flag from the kernel sync api.

This allows moving all the kernel submit sync code to be conditionally
compiled in only when needed, and separates the user sync functionality
in a more clear way from the rest with a minimal API.

[this is squashed with commit 5111caea601a (gpu: nvgpu: guard user
syncpt with nvhost config) from
https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325009]

Jira NVGPU-4548

Change-Id: I99259fc9cbd30bbd478ed86acffcce12768502d3
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321768
(cherry picked from commit 1095ad353f5f1cf7ca180d0701bc02a607404f5e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319629
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 2020-12-15 14:13:28 -06:00
vinodg
df896cd3c7 gpu: nvgpu: support feature_override for nvgpu-next 
Jira NVGPU-4667

Signed-off-by: vinodg <vinodg@nvidia.com>
Change-Id: I5dc64b874acf691c6a77dcda6c66c119dbc0092c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2324880
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 2020-12-15 14:13:28 -06:00
Vinod G
340ea241cb gpu: nvgpu: remove channel debug_dump hal 
Channel debug_dump hal function does not involve
any register related code.

Move gv11b_channel_debug_dump hal function to
common code nvgpu_channel_info_debug_dump function.

Check gpu hw version to limit instance variables
dump that differs between socs.

Add new hal pointer syncpt_debug_dump for pbdma.

Jira NVGPU-5109

Signed-off-by: Vinod G <vinodg@nvidia.com>
Change-Id: Icfca837ce8e4117387cffa6fadf6c094c7da5946
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321016
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
62c06723dd gpu: nvgpu: sim: defer sim buffers allocation 
Allocate sim buffers only after chip specific
memory properties are enabled.

JIRA NVGPU-5281

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I7b64b3a51b8cd66dbefd22a09216b2caaeccacbf
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2324083
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
675fb39ca0 gpu: nvgpu: add runlist.init_enginfo hal 
Add runlist.init_enginfo hal to initialize
runlist's engine info. nvgpu-next has it's own
implementation for init_enginfo hal, so removed
NVGPU_NEXT_INIT_RUNLIST_ENGINFO from nvgpu hals.

JIRA NVGPU-4979

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Ie35a88c6ba3c7c741124386f7c643b36b42d4143
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319103
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Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
44f12288ad gpu: nvgpu: add mc.reset_engine hal for nvgpu-next 
Engine reset process has changed for nvgpu-next. Add mc.reset_engine
gops for nvgpu-next.
Modify engine reset functions to use mc.reset_engine hal.

Jira NVGPU-5145

Change-Id: I176800212042eaef71c8cbd4bc499805c5af0e60
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2312485
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Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
002fb2431d gpu: nvgpu: nvgpu-next changes for fifo pbdma 
- Include nvgpu_next_pbdma.h in pbdma.h
- NULL check for fifo.init_pbdma_map hal before allocating
  memory for f->pbdma_map
- NULL check for f->pbdma_map before freeing memory for
  f->pbdma_map

JIRA NVGPU-4979

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I5eacc671b924c947620b2c49c8f82577c30ba1a3
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317804
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 2020-12-15 14:13:28 -06:00
Seema Khowala
b7767a604f gpu: nvgpu: add intr_top_enable fifo gops 
This is required for enabling fifo interrupts for nvgpu-next.

JIRA NVGPU-4864

Change-Id: I5c09105296a01b82505023ecf576d71ce74f7a31
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313013
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
d0ffb335dc gpu: nvgpu: move nvgpu_has_syncpoints 
nvgpu_has_syncpoints is more general than a channel synchronization
related, so move it to nvhost.c from channel_sync.c. Move the
declaration from gk20a.h to nvhost.h.

As the debugfs knob is Linux related, move it from struct gk20a to
struct nvgpu_os_linux.

Jira NVGPU-4548

Change-Id: I4236086744993c3daac042f164de30939c01ee77
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318814
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 2020-12-15 14:13:28 -06:00
ajesh
9846573d64 gpu: nvgpu: handle the return values from OS APIs 
Handle the return values from standard OS library calls.

Jira NVGPU-4987

Change-Id: I41bf0113097d6bfa344ed58f68448abc9cc7f367
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299985
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 2020-12-15 14:13:28 -06:00
Terje Bergstrom
6d4e4f633f gpu: nvgpu: posix: Use non-atomic types when appropriate 
Atomic functions return non-atomic types. Change the type definitions
and casts to follow that.

Change-Id: If6fbfa5f75810151fe4765874f3dd610b85a39d1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318384
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
da8ee8d615 gpu: nvgpu: add therm_max_fpdiv_factor gops.therm 
Use therm_max_fpdiv_factor gops.therm for nvgpu-next to get the maximum
fp_div_factor.

Jira NVGPU-4860

Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Change-Id: If0e9b82f5b61289e226ceeff386fc88763af66e2
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313336
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 2020-12-15 14:13:28 -06:00
Abdul Salam
4f5bd9e633 gpu: nvgpu: Implement clk_good and pll_lock check 
Add clk_good and pll_lock check as a part of fmon polling.
This will poll for any clock related faults at FTTI interval.
Add new function to poll for vbios init completion.

NVGPU-4967
Bug 2849506
Bug 200564937

Change-Id: I5bc885329981e07376824e148edabe9be4120e1c
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2305782
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 2020-12-15 14:13:28 -06:00
Seema Khowala
21e2214c3d gpu: nvgpu: support nvgpu-next intr config 
JIRA NVGPU-4864

Change-Id: I2fb5be3270c73ea891021161f539a7f731e05f63
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
a5b3170c6f gpu: nvgpu: Refactor allocator lite unit 
- Changed the names of structs as per private/public
  naming convention.
- Renamed allocator.c file

NVGPU-4487

Change-Id: I42ec5730f1cb0029a6bb6e6ddff151bd08d6bbd8
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316945
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
f43d5df83a gpu: nvgpu: build dGPU in safety 
Enable build flags for dGPU in safety, when
NVGPU_FORCE_DGPU_SAFETY_PROFILE is set.

Use libnvgpu-dgpu_safe.exports for dGPU safety build.

Add build flags for tu104 HAL initialization (to solve
undefined symbols in safety build).

Temporarily add non-fusa files needed to build dGPU in safety.
related functions will have to move to fusa files.

Jira NVGPU-4611

Change-Id: I41db0c039c7f15d9191cdb811b4906e779d5cc88
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310276
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
872b3946dd gpu: nvgpu: add nvgpu-next fb gops 
JIRA NVGPU-5222

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I3004fcfd9cf17b81c6d218954da140982a76c6fd
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316212
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 2020-12-15 14:13:28 -06:00
rmylavarapu
f5acc98db3 gpu: nvgpu: Refactor Super surface lite unit 
- Changed the names of structs as per private/public
  naming convention.
- Removed unwanted code in struct super_surface.

NVGPU-4486

Change-Id: I5834c2296ccbe1545bca6a608ad88817a9104fb8
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313989
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
682966ef4c gpu: nvgpu: posix: add some nvhost primitives 
Add the following primitives to resolve build issues
when enabling dGPU in safety build:
- nvgpu_nvhost_syncpt_is_expired_ext
- nvgpu_nvhost_syncpt_is_valid_pt_ext
- nvgpu_nvhost_syncpt_incr_max_ext
- nvgpu_nvhost_intr_register_notifier
- nvgpu_nvhost_get_syncpt_host_managed
- nvgpu_nvhost_syncpt_wait_timeout_ext
- nvgpu_nvhost_syncpt_read_ext_check

Jira NVGPU-4661

Change-Id: Iabd7b2a9addc96ed48f42aedb5640a17c6dce62c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2314207
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
8ec4395e82 gpu: nvgpu: build flag for deterministic channel 
Add CONFIG_NVGPU_DETERMINISTIC_CHANNELS and fix
preprocessor #ifdefs to allow compiling kernel mode
submit without deterministic feature enabled.

Jira NVGPU-4661

Change-Id: I4aa678715824e8981d39bd8db0c5ae61ef3a675c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310325
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 2020-12-15 14:13:28 -06:00
Seeta Rama Raju
5ce7d5acff gpu: nvgpu: Add fault injection variable for clock UT 
Bug 2861451

Change-Id: Ie51c1524c47934e44cde06515f5daccd8e1e7dd9
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
(cherry picked from commit d57a51ba6db7b6c2df28d1770727506214b85e08)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310971
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
7aa9e90bfc gpu: nvgpu: update gops.cg 
Update gops.cg to include following runlist level cg ops:
- blcg_runlist_load_gating_prod
- slcg_runlist_load_gating_prod

Jira NVGPU-5048

Change-Id: Ia2a3f887d5c2fd6f1dd35d606afd19d117468c2c
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300448
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Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Sagar Kamble
59c6947fc6 gpu: nvgpu: add CONFIG_NVGPU_TEGRA_FUSE 
Encapsulate the tegra fuse functionality under the config flag
CONFIG_NVGPU_TEGRA_FUSE.

Bug 2834141

Change-Id: I54c9e82360e8a24008ea14eb55af80f81d325cdc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306432
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
3748be5792 gpu: nvgpu: move timer functions from soc files 
Move following timer functions from soc header and c file to timer
header and c file:
1. nvgpu_delay_usecs
2. nvgpu_us_counter
3. nvgpu_get_cycles

Bug 2834141

Change-Id: I04cf7229a0d35c90a320bbe64e80912b08cccefb
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306431
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
00eec69b3f gpu: nvgpu: add hal to get_ctx_buffer_offsets 
Currently, gr_gk20a_get_ctx_buffer_offsets is defined as a function.
However, this function is used in the common code. So, add new GR hal
to get_ctx_buffer_offsets.

Jira NVGPU-5047

Change-Id: I0cec6ff19194fa726722e6af3a2f11a188dc9087
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310352
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
007ecfb5bc gpu: nvgpu: support upto four stall interrupt lines 
Add two new variables in nvgpu_mc struct to support
upto four stall interrupt lines.

Variables:-

Total number of stall interrupt lines:
u32 irq_stall_count

Array to store irq_stall interrupt number for upto 4
stall irq lines:
u32 irq_stall_lines[4]

JIRA NVGPU-4864

Change-Id: I9b43fc20c78dbcaf97fe8e685bb77963f06d3f99
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310377
Tested-by: Lakshmanan M <lm@nvidia.com>
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
vinodg
4aff9bcd4e gpu: nvgpu: fix for load imbalance across cta subpartitions 
CTA_SUBPARTITION_SKEW load balancing is broken across
subpartitions. SW WAR to disable the CTA_SUBPARTITION_SKEW.

Jira NVGPU-5132
Bug 200593339

Signed-off-by: vinodg <vinodg@nvidia.com>
Change-Id: I3faae882a94fc6262cc287df44994cc04b4fd5d6
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308905
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
rmylavarapu
147564cbd5 gpu: nvgpu: NVGPU migration to support latest ucode 
Changes:
- Send down BOARDOBJGRP classId to the PMU. Assign each
  BOARDOBJ the classId of its parent group which is set
  to zero in current implementation. Changed in NVGPU to send
  board obj grp classid to PMU.
- Disable IPC VMIN support as pmu-tu10a profile doesn't support.
- Change in clk vf point enumeration types.
- Change in pstate type values.
- Updated ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info
  NVGPU-PMU interface struct with b_ver_expected_is_mask to send
  whether the expected version is single value or should be
  interpreted as a bit mask with bits corresponding to
  expected versions set.

NVBUG-200593676
NVGPU-5066

Change-Id: I17b172d88f8b74fbf78044caf7f64cd8811f9fb7
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308533
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 2020-12-15 14:13:28 -06:00
rmylavarapu
dc32307c13 gpu: nvgpu: Rename therm public struct 
Renamed therm public struct to match with the other
units.

NVGPU-4449

Change-Id: I675ce43b136139420b8cc1eecdc395d9165d9f30
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307090
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 2020-12-15 14:13:28 -06:00
Petlozu Pravareshwar
6859c9c5a6 gpu: nvgpu: Add nvgpu macro for a pthread API 
Add nvgpu macro for pthread API pthread_cleanup_pop(0). The argument
zero would mean that the thread cancellation cleanup handler which is
pushed onto the thread's stack using pthread_cleanup_push() will not
get executed.

JIRA NVGPU-5110

Change-Id: I89a45ccccd8709685f487513bf99d622a82ed891
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307977
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
9aa669797d gpu: nvgpu: add pbdma gops for nvgpu_next 
Add pbdma gops for nvgpu-next.

Jira NVGPU-4979

Change-Id: If04f5c09cd4a13b0f536a15dbe2b4bd9eb24107a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2302772
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
2e4fb38870 gpu: nvgpu: add eng_config hal for nvgpu_next 
Add gr.eng_config hal for nvgpu_next.

Jira NVGPU-5049

Change-Id: Ieb342cb0416f965a3f80e3a6e3f0f43a853485ff
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300534
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
5fa0d7f994 gpu: nvgpu: add bundle programming for nvgpu_next 
Update bundle programming for nvgpu_next.

JIRA NVGPU-5004

Change-Id: I1c452a9e78cd018de86fb57de10291c4411e7d89
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299128
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 2020-12-15 14:13:28 -06:00
rmylavarapu
e424e4791a gpu: nvgpu: perf: Refactor Perf unit 
-Renamed and moved nvgpu_pmu_perf struct from public
to unit specific
-Renamed all functions as per public/private format

NVGPU-5029

Change-Id: If3f479bb1443850a5c8a8714cd1c9da346cb566a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300609
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
14f268563a gpu: nvgpu: add gr.zbc hal for nvgpu_next 
Add gr.zbc hal for nvgpu_next

Jira NVGPU-5084

Change-Id: I678dac83ea67818e1b657b22840f3f4a04584ba8
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2304195
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Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Seema Khowala
ffe44aab13 gpu: nvgpu: mc: add hooks for nvgpu-next 
JIRA NVGPU-4864

Change-Id: I692d041d005b0d62813df5f16d21c8ae92a2c3e0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2293201
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
sagar
88e27271eb gpu: nvgpu: fix static analysis issues 
coverity tool is not detecting the lenght validation done at caller.
moved length checks to appropriate functions.

used macro instead of hardcoded values.

Jira NVGPU-4780

Change-Id: Ie6b420a6e625eed5374715fd7ca5c87d3ba3d015
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2302335
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
630eaa46cb gpu: nvgpu: update the config options & makefile 
Added dependency between the Kconfig options as follows where
'->' indicates 'depends on' relation:

SUPPORT_CDE -> COMPRESSION -> DMABUF_HAS_DRVDATA
DGPU -> GK20A_PCI

Defined Kconfig option for VPR and for DGPU that is dependent GK20A_PCI
as well. DGPU related sources are now compiled under config flag DGPU.
Also update conditional compilation of the driver paths w.r.t DGPU,
VPR and COMPRESSION flags.

Bug 2834141

Change-Id: Ia0a39d6d4cf8b36e7f955b7355a5ab41783f821c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299627
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 2020-12-15 14:13:28 -06:00
Abdul Salam
29d4831780 gpu: nvgpu: Segregate volt unit members based on their accessibility 
Currently all unit specific private members are inside ucode_volt_inf.h.
This patch moves the members specific to pmuif to ucode_volt_inf.h and
local to volt.h.
Append all unit specific local functions with volt/nvgpu.
Move volt specific rpc handler from g->pmu to g->pmu->volt.

NVGPU-4492

Change-Id: I626e002b3876c6c5330dec4396b7661b986c6119
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299555
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
ed4eb79ac1 gpu: nvgpu: SWUD Lite updates 
Updated minor typo errors found during code inspection

JIRA NVGPU-4785
JIRA NVGPU-4789

Change-Id: I37384a852e9a2783e3033a6f12c21eafc00e5bcf
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300560
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
43324f7b1b gpu: nvgpu: Reconcile sim escape paths between RM and nvgpu 
SIM models are getting updated to have same escape read path
for RM and nvgpu. Updated nvgpu driver code to have same escape
read mechanism as RM.

This is required for igpu to pass on NET21.

Bug 2539889

Change-Id: I5d37ceb799cafb7fc7dec611fda5f5caac7d7f17
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2130414
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Tested-by: Lakshmanan M <lm@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Rajesh Devaraj
50d71f7c56 gpu: nvgpu: report fecs ctxsw init error 
This patch adds callback to report fecs ctxsw init error to 3LSS.
It also moves the related wrapper function to nvgpu_err header
file and adds doxygen documentation.

JIRA NVGPU-5042

Change-Id: I2a051cf19c2940859169799a4dd51adf8870eff4
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300003
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Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
18f9d05aae gpu: nvgpu: spec_barrier & DMA_ERROR_CODE update 
These macros are not defined in future kernel.

Bug 2834141

Change-Id: Ib2ee419b66f4d949fd538dfbb04b8cffa73c1e44
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299626
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Scott Long
4fd8df5ca0 gpu: nvgpu: fix misra 10.5 violations 
MISRA Advisory Rule 10.5 states that the value of an expression should
not be cast to an inappropriate essential type.

This change eliminates such a violation in the posix implementation
of nvgpu_thread_cleanup_pop().

Jira NVGPU-3178

Change-Id: I2ad363b4d60c321fa20b23c167d783bebaceb7d3
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298986
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:13:28 -06:00