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5329 Commits

Author SHA1 Message Date
Sagar Kamble
7b51c6befc gpu: nvgpu: isolate common & hal falcon_copy_from|to_dmem|imem functions 
nvgpu_falcon_copy_from|to_dmem|imem should validate copy parameters. And
gk20a_falcon_copy_from|to_dmem|imem is supposed to be hal API that will
copy the data.

JIRA NVGPU-1459

Change-Id: I2648721f42cffd30d29058818af26d4ad47c7277
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2015592
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2019-02-14 02:28:03 -08:00
Sagar Kamble
11fa89d618 gpu: nvgpu: isolate common & hal falcon_set_irq functions 
nvgpu_falcon_set_irq should handle interrupts state. gk20a_falcon_set_irq
is supposed to be hal API that will enable/disable the falcon interrupts.

JIRA NVGPU-1459

Change-Id: I2c97a7c1fd5cc0a5d11d80f62bca5aaa66f3b3c9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2015591
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-02-14 02:27:58 -08:00
Sagar Kamble
b6b56bd556 gpu: nvgpu: isolate common & hal falcon_reset functions 
nvgpu_falcon_reset should handle engine specific falcon reset or resort to
falcon CPU reset. gk20a_falcon_reset is supposed to be hal API that will
reset the falcon CPU. Hence move the dependent engine reset to
nvgpu_falcon_reset.

JIRA NVGPU-1459

Change-Id: I1b15f31a8bbb515736af5b0122ce206be0811bbc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2015590
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-02-14 02:27:54 -08:00
Sagar Kamble
69dd2ce8be gpu: nvgpu: make falcon dump_stats and get_ctls static 
These functions need not be exported from hal.

JIRA NVGPU-1459

Change-Id: Iaccb9542e280e2869ec3be7e4c9f06d62f887430
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2015589
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2019-02-14 02:27:49 -08:00
Sagar Kamble
f2fc0c2ba8 gpu: nvgpu: move falcon mem copy locking to common 
Falcon copy_lock mutex operations are hal independent. Move to falcon.c.

JIRA NVGPU-1459

Change-Id: I6ff90eb7c96d495c317fcf0313aa2934d1fc0d8c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2015588
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-02-14 02:27:45 -08:00
Sagar Kamble
c2a1cc5ff8 gpu: nvgpu: remove unneeded falcon struct members 
Remove unneeded members from falcon struct - flcn_core_rev, isr_enabled,
isr_mutex, intr_mask & intr_dest.

JIRA NVGPU-1459

Change-Id: I682666355778c1ac9ff0ffae014ff3271f9149a7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2015587
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-02-14 02:27:39 -08:00
Debarshi Dutta
ddcdf364b7 gpu: nvgpu: use public APIs of engine_status_info unit 
nvgpu driver presently uses h/w functions to read and process
the engine_status registers. H/w headers shouldn't be directly invoked
by common code and should be called via HAL layer. This patch replaces
the h/w headers with the APIs in the engine_status_info unit.

Jira NVGPU-1315

Change-Id: I767a2b116b07cce4f4b587e6da8dd118afa27de5
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2005470
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2019-02-13 14:34:03 -08:00
Debarshi Dutta
e60bae8ec4 gpu: nvgpu: add engine_status_info unit 
A new unit nvgpu_engine_status_info is added. The unit provides a HAL
ops function pointer read_engine_status_info() to read and produce
a struct of type nvgpu_engine_status_info. Additionally, the unit
provides public APIs to retrieve data from the struct
nvgpu_engine_status_info.

Jira NVGPU-1315

Change-Id: I6c167c36081bee5c9a8db51d3467c8f5f02c2685
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2003886
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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 2019-02-13 14:34:00 -08:00
Nicolas Benech
af2385b563 gpu: nvgpu: unit: add MMU faults unit 
Add a new unit to cover MMU faults, with a focus on GV11B

JIRA NVGPU-907

Change-Id: I7cab1b75ce03cc30e8a0d593239c8420a7f243f5
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018404
GVS: Gerrit_Virtual_Submit
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 2019-02-13 12:24:36 -08:00
Preetham Chandru R
a7e4390e73 gpu: nvgpu: rename dma map/umap interfaces 
On Desktop verion, map is called nvidia_p2p_dma_map_pages and umap is
called nvidia_p2p_dma_umap_pages. So renamed these two apis to match
the desktop version.

Bug 200438879

Change-Id: I66301c48b832dfed8c3950678f473c2f82b8761a
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014943
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 2019-02-13 01:45:43 -08:00
Rohith Seelaboyina
aa6317e10a Revert "gpu: nvgpu: unit: add MMU faults unit" 
This reverts commit 1d49e8218d.

Change-Id: Ifdcc5acc7e5d3df3cf0174068dccaf795675ee8b
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017916
 2019-02-12 22:55:36 -08:00
rmylavarapu
8e6d9a4b40 gpu: nvgpu: Debugfs for VF table 
Changes:
1. Added Vftable debugfs in existing gv100_clk_init_debugfs function.
2. Created file operations for VF table printing.
3. Command for reading VF table:
   cat /sys/kernel/debug/gpu_pci/clocks/vftable

Jira NVGPU-1603

Change-Id: I9893ef8452ecef5d3c8a519a3abd5fe292f3b8c8
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1987430
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2019-02-12 20:28:56 -08:00
Konsta Holtta
25c433e2a3 gpu: nvgpu: join reset_{eng,pbdma}_faulted_tsg 
Resetting the engine and the pbdma masks of a channel go via the same
API and are often called together, so join them for a single function.

Jira NVGPU-1307

Change-Id: I0723bacca8f6be67ba74464bc44a94c8bf4489ab
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017271
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-02-12 17:06:50 -08:00
Konsta Holtta
0d3f06931b gpu: nvgpu: delete unnecessary ccsr includes 
ce2 and cde are not using the hw ccsr header for anything so delete the
include directives from them.

Jira NVGPU-1307

Change-Id: I7b74504a8e3eae4be4e189e74358254cb10f1ac7
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017270
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 2019-02-12 17:06:46 -08:00
Konsta Holtta
38c548a39c gpu: nvgpu: Add channel.reset_faulted HAL 
Add a HAL op for resetting the eng_faulted and pbdma_faulted states on a
channel. This used to be a local feature in fifo_gv11b.c; the HAL is
defined for all chips from gv11b onwards.

Jira NVGPU-1307

Change-Id: I120a59c429851cc69e712ddd5b06a4b3d16c06c9
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017269
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 2019-02-12 17:06:37 -08:00
Konsta Holtta
44e4d69734 gpu: nvgpu: add channel.force_ctx_reload HAL 
Isolate the write to ccsr_channel_force_ctx_reload behind a HAL op.

Jira NVGPU-1307

Change-Id: Iaef7d740f4a89e4a45c7de28f001a7dea98ce066
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017268
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 2019-02-12 17:06:28 -08:00
Konsta Holtta
9457a5ea91 gpu: nvgpu: add eng_faulted to channel HAL for gv11b+ 
The ccsr_channel_eng_faulted field exists from Volta onwards. Implement
the read_state HAL op for those chips, and store that bit as a boolean
in the channel state info.

Jira NVGPU-1307

Change-Id: Ie997892f2d3db0725496661a4d3083e7396894cc
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017267
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 2019-02-12 17:06:18 -08:00
Konsta Holtta
cd4b2f642c gpu: nvgpu: add HAL for reading ccsr_channel 
Refactor read accesses to the ccsr_channel register for channel state to
be done via a channel HAL op for all chips. A new op called read_state
is added for this; information needed by other units is collected in a
new struct nvgpu_channel_hw_state.

Jira NVGPU-1307

Change-Id: Iff9385c08e17ac086d97f5771a54b56b2727e3c4
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017266
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 2019-02-12 17:06:09 -08:00
Konsta Holtta
335e4f1839 gpu: nvgpu: add complete ccsr status values 
Currently we're hardcoding some of these as magic constants. Some of the
status values are used so just add all of them for consistency.

Jira NVGPU-1307

Change-Id: I613a96c603b3db6a0b90dfa87b972533ebdf8d0e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017265
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2019-02-12 17:06:00 -08:00
Konsta Holtta
7189630e7c gpu: nvgpu: drop fifo_ in channel HAL names 
Now that the moved HAL ops from fifo are in channel, rename the
implementations to match.

Jira NVGPU-1307

Change-Id: I7b9336f506c9e71bcd0af98886216958bd6695eb
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017264
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 2019-02-12 17:05:56 -08:00
Konsta Holtta
c04ad92cd1 gpu: nvgpu: include bitops.h from posix log2.h 
The posix log2 header defines macros that need the bitops header which
was missing. Add the necessary include.

Change-Id: I20ceee53e9fe380879c1e49a0d4c7495fb35e8a8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017263
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2019-02-12 17:05:47 -08:00
Konsta Holtta
5cde4c2140 gpu: nvgpu: move chip specific channel reg ops to common 
Extract out the HAL ops' implementation that now belongs to the channel
unit. This unit is responsible for channel register accesses and the
like (ccsr_*).

Rename channel_gm20b_bind to gm20b_fifo_channel_bind to match with the
rest of the naming. Same with channel_gv11b_unbind.

Jira NVGPU-1307

Change-Id: I58b9d96dbdaf36bdb163a5729544a41faec828ab
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017262
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 2019-02-12 17:05:43 -08:00
Konsta Holtta
c330d8fd98 gpu: nvgpu: add channel HAL section for ccsr_* 
Split out ops that belong to channel unit to a new section called
channel. Channel is a broad concept; this includes just the code that
accesses channel registers (ccsr_*). This is effectively just renaming;
the implementation still stays put.

The word "channel" is also dropped from certain HAL entries to avoid
redundancy (e.g., channel.disable_channel -> channel.disable).
fifo.get_num_fifos gets an entirely new name: channel.count.

Jira NVGPU-1307

Change-Id: I9a08103e461bf3ddb743aa37ababee3e0c73c861
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017261
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-02-12 17:05:34 -08:00
Nicolas Benech
1d49e8218d gpu: nvgpu: unit: add MMU faults unit 
Add a new unit to cover MMU faults, with a focus on GV11B

JIRA NVGPU-907

Change-Id: Ia5f80d5b5614cae24a5dcf2835a8e84edb271ab9
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1978366
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2019-02-12 15:54:31 -08:00
Abdul Salam
6945209418 gpu: nvgpu: Add unified check for clk_arb support 
Currently clk_arb needs PSTATE to be true for dGPU.
Setting PSTATE only FALSE, causes issue as clk_arb fails.
There is no such dependency of PSTATE on iGPU.
Making it unified with a call to check_clk_arb_support().
This call is implemented based on its dependency in iGPU, dGPU.
check_clk_arb_support returns true if supported, else false.

Jira NVGPU-1948

Change-Id: I108dc12bd6ad8d0e074352080c978b7dda9bee05
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014775
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2019-02-12 08:54:49 -08:00
Kyle Guo
962c0f818b nvgpu: gk20a: fix NULL deref in gk20a_ce_suspend 
g->ce_app could be NULL. And dereferencing it causes crash during STR. This
patch checks the pointer before accessing it.

Bug 200481958

Change-Id: I493821ba1fa4c7be5d6a05514a2be20f154048b3
Signed-off-by: Kyle Guo <kyleg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2009080
(cherry picked from commit c64b95cc22dbe9a0525bb7f6aca265bcf53627cb)
Reviewed-on: https://git-master.nvidia.com/r/2011663
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Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
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 2019-02-12 03:38:00 -08:00
Tejal Kudav
cb0d314f23 gpu: nvgpu: Fix MISRA 16.x violations in nvlink 
All the 16.x MISRA rules are relevant to switch statement
formatting and hence addressed in single patch

As per MISRA 16.1, all switch statements should be well formatted.

16.3 fixes:
Add unconditional break statements to all the switch-clauses
to adhere to MISRA rule 16.3.

JIRA NVGPU-1921

Change-Id: I7caee762bad03889944c94b44124e673b64e1fbc
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014634
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-02-12 00:29:43 -08:00
rmylavarapu
75f9486b82 gpu: nvgpu: Debugfs for S_param 
Changes:
1) Added nvgpu_s_param_init_debugfs for creating debugfs interface.
2) Command for S_param value:
   cat /sys/kernel/debug/gpu_pci/s_param
3) vfe_var_boardobj_grp_get_status is implemented.

Jira NVGPU-1736

Change-Id: Icbcf39e47777fe969ae2592b58a3103a21011a87
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989334
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 2019-02-11 20:55:07 -08:00
Philip Elcan
824b8b5a41 gpu: nvgpu: volt: update type for size param 
Update interfaces to use size_t to align with boardobj_construct_super()
and avoid unnecessary casts.

JIRA NVGPU-1008

Change-Id: Ie890296a9a3db1af0d6c37c4319d6225cba1fcb7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011439
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 2019-02-11 14:04:43 -08:00
Philip Elcan
a789034209 gpu: nvgpu: pstate: update type for size param 
Update interfaces to use size_t to align with boardobj_construct_super()
and avoid unnecessary casts.

JIRA NVGPU-1008

Change-Id: I4e1aca8c061ec8ee6da7428f6bc200437894dc57
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011438
Reviewed-by: Automatic_Commit_Validation_User
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 2019-02-11 14:04:39 -08:00
Philip Elcan
0a0d866400 gpu: nvgpu: therm: update type for size param 
Update interfaces to use size_t to align with boardobj_construct_super()
and avoid unnecessary casts.

JIRA NVGPU-1008

Change-Id: I5aac3483ed5080bf633ba564e8684db425c50a22
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011437
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Scott Long <scottl@nvidia.com>
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 2019-02-11 14:04:36 -08:00
Philip Elcan
699c2a15fa gpu: nvgpu: pmgr: update type for size param 
Update interfaces to use size_t to align with boardobj_construct_super()
and avoid unnecessary casts.

JIRA NVGPU-1008

Change-Id: I7bff681f04f43e2f599d6f47138b04b2a94bfff3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011436
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Scott Long <scottl@nvidia.com>
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 2019-02-11 14:04:32 -08:00
Philip Elcan
0298551613 gpu: nvgpu: perf: update type for size param 
Update interfaces to use size_t to align with boardobj_construct_super()
and avoid unnecessary casts.

JIRA NVGPU-1008

Change-Id: I83676ba8c7f91be610da5e83d15dbecdf767925e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011435
Reviewed-by: Automatic_Commit_Validation_User
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 2019-02-11 14:04:28 -08:00
Philip Elcan
2beed190a7 gpu: nvgpu: clk: update type for size param 
Update interfaces to use size_t to align with boardobj_construct_super()
and avoid unnecessary casts.

JIRA NVGPU-1008

Change-Id: Ib4539239363f106f1fba8d523072b28d0b8369ad
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011434
Reviewed-by: Automatic_Commit_Validation_User
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 2019-02-11 14:04:25 -08:00
Philip Elcan
0510641114 gpu: nvgpu: boardobj: use size_t for construct API 
Rather than having everyone cast their sizeof() values to u16, just use
size_t for the size for the boardobj_construct_super() API.

JIRA NVGPU-1008

Change-Id: I0201de802a48776e05f39a756105f1a5e88b4dec
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011433
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Scott Long <scottl@nvidia.com>
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 2019-02-11 14:04:21 -08:00
Philip Elcan
ab5684ce1b gpu: nvgpu: channel: use u32 for syncpt id 
Make the APIs nvgpu_channel_sync_get_syncpt_id() and
channel_sync_syncpt_get_id() return u32s rather than converting to
ints and back.

Also define FIFO_INVAL_SYNCPT_ID to use for invalid syncpt IDs rather
than using magic numbers.

JIRA NVGPU-1008

Change-Id: I4dde6b15fd3708fb0126b46c6fea8ac1b447c7ce
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014821
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 2019-02-11 12:55:36 -08:00
Philip Elcan
fa81cf9000 gpu: nvgpu: fifo: cleanup MISRA 10.3 violations 
MISRA 10.3 prohibits assigning of objects of different size or essential
type. This fixes a number of violations in the common/fifo code.

JIRA NVGPU-1008

Change-Id: I138c27eb86f6e0f9481c39a94d6632e2b4360af8
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2009940
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-02-11 12:55:27 -08:00
Philip Elcan
ff80b0e6c1 gpu: nvgpu: gp10b: misc MISRA 10.3 fixes 
This fixes some miscellaneous MISRA 10.3 violations in gp10b for
assignment of objects of different size or essential type.

JIRA NVGPU-1008

Change-Id: I40e83cd5682c9407ce4301663d07578a40ce1814
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2006586
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 2019-02-11 12:55:15 -08:00
Philip Elcan
2c195de777 gpu: nvgpu: gp10b: fix mm MISRA 10.3 violations 
This fixes MISRA 10.3 violations in mm_gp10b.c to avoid assigning of
objects from different size or essential type.

JIRA NVGPU-1008

Change-Id: I4ad69f465971a32888c727b33e9da078530f4518
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2006585
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-02-11 12:55:06 -08:00
Philip Elcan
cb5f9fd59f gpu: nvgpu: gp10b: make pending chid a u32 
The channel ID is typically unsigned, so change the
cilp_preempt_pending_chid from an int to a u32.

JIRA NVGPU-1008

Change-Id: I773dac22c61903aafb311f43b19dfd08d4983eea
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011683
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 2019-02-11 12:55:02 -08:00
Philip Elcan
08ec580cd0 gpu: nvgpu: gp10b: fix gr MISRA 10.3 violations 
This fixes MISRA 10.3 violations in gr_gp10b.c to avoid assigning of
objects from different size or essential type.

JIRA NVGPU-1008

Change-Id: Ifafb17a3d6f91331d6dff20366cee046f62bf364
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2006584
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 2019-02-11 12:54:53 -08:00
Deepak Nibade
a3068cebc6 gpu: nvgpu: patch SMPC only for main context image 
In __gr_gk20a_exec_ctx_ops(), we right now call gr_gk20a_ctx_patch_smpc()
even if operations are on pm_ctx image which is incorrect since this is
only required for SMPC operations on main context image

Fix this by not calling gr_gk20a_ctx_patch_smpc() for pm_ctx image

Jira NVGPU-1527
Jira NVGPU-1613

Change-Id: I5111fb0e6ea1f329750b42a37a98f5c006b47deb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011095
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-02-11 10:25:42 -08:00
Deepak Nibade
5b2eb887d5 gpu: nvgpu: add gr/ctx and gr/subctx APIs to configure patch context 
gr_gk20a_ctx_patch_smpc() updates patch countext count and mode by
directly calling g->ops.gr.ctxsw_prog HALs

Move the configuration of patch context to gr/ctx and gr/subctx units
with below APIs and call these from gr_gk20a_ctx_patch_smpc()
nvgpu_gr_ctx_reset_patch_count()
nvgpu_gr_ctx_set_patch_ctx()
nvgpu_gr_subctx_set_patch_ctx()

Jira NVGPU-1527
Jira NVGPU-1613

Change-Id: Ib1ccbc036aa0916e7bd0a002d16b74430a7e47c9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011094
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-02-11 10:25:38 -08:00
Deepak Nibade
fe27a7f934 gpu: nvgpu: add gr/ctx and gr/subctx APIs to set hwpm ctxsw mode 
gr_gk20a_update_hwpm_ctxsw_mode() right now validates the incoming
hwpm mode, checks if it is already set, and if not, it will go ahead
and set the new hwpm mode by calling g->ops.gr.ctxsw_prog HALs

Instead of programming hwpm mode in gr_gk20a.c, move the programming
to gr/ctx and gr/subctx units by adding below APIs
nvgpu_gr_ctx_prepare_hwpm_mode() - validate the incoming mode and
                                   check if it is already set
nvgpu_gr_ctx_set_hwpm_mode() - set pm mode in graphics context
nvgpu_gr_subctx_set_hwpm_mode() - set pm mode in subcontext

Add gpu_va field to struct pm_ctx_desc to store the gpu_va to be
programmed into context

Rename NVGPU_DBG_HWPM_CTXSW_MODE_* to NVGPU_GR_CTX_HWPM_CTXSW_MODE_*
and move them to gr/ctx.h

Remove below HALs since they are no longer used
g->ops.gr.ctxsw_prog.set_pm_mode_no_ctxsw()
g->ops.gr.ctxsw_prog.set_pm_mode_ctxsw()
g->ops.gr.ctxsw_prog.set_pm_mode_stream_out_ctxsw()

Jira NVGPU-1527
Jira NVGPU-1613

Change-Id: Id2a4d498182ec0e3586dc7265f73a25870ca2ef7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011093
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 2019-02-11 10:25:34 -08:00
Deepak Nibade
dd12b9b320 gpu: nvgpu: add gr/ctx API to set smpc ctxsw mode 
gr_gk20a_update_smpc_ctxsw_mode() right now directly sets the SMPC
mode in context image by calling g->ops.gr.ctxsw_prog HAL

Add new API nvgpu_gr_ctx_set_smpc_mode() in gr/ctx unit to set SMPC
mode and use it in gr_gk20a_update_smpc_ctxsw_mode()

Jira NVGPU-1527

Change-Id: Ib9a74781d6bb988caffc2a79345be773fd4942e4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011092
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2019-02-11 10:25:25 -08:00
Deepak Nibade
2af1558d42 gpu: nvgpu: add gr/ctx API to init zcull in context 
gr_gk20a_init_golden_ctx_image() right now directly initializes
zcull state in context image by calling g->ops.gr.ctxsw_prog HAL

Add new API nvgpu_gr_ctx_init_zcull() in gr/ctx unit to do this
initialization and use it in gr_gk20a_init_golden_ctx_image()

Jira NVGPU-1527

Change-Id: I8cf58168cbc9c01fdd663e1ade50b7804118ef01
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011091
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2019-02-11 10:25:21 -08:00
Deepak Nibade
bac95b36d8 gpu: nvgpu: move zcull context setup to gr/ctx and gr/subctx units 
In gr_gk20a_ctx_zcull_setup(), we configure context/subcontext with
zcull details
This API now does it directly by calling g->ops.gr.ctxsw_prog HAL

Move all context/subcontext setup to gr/ctx and gr/subctx units
respectively
Define and use below new APIs for same
gr/ctx : nvgpu_gr_ctx_zcull_setup()
gr/subctx : nvgpu_gr_subctx_zcull_setup()

Jira NVGPU-1527
Jira NVGPU-1613

Change-Id: I1b7b16baea60ea45535c623b5b41351610ca433e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011090
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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 2019-02-11 10:25:16 -08:00
Deepak Nibade
319eca3498 gpu: nvgpu: move get_ctx_id API to gr/ctx unit 
API gr_gk20a_get_ctx_id() extracts ID of the context and as such
belongs to gr/ctx unit
Move it to gr/ctx and rename it as nvgpu_gr_ctx_get_ctx_id()

All the book keeping for valid ID is also done in same API using
ctx_id_valid flag in gr/ctx unit

Use new API in gr_gp10b_set_cilp_preempt_pending() to get the
context ID

Jira NVGPU-1527

Change-Id: I198262765e95133220f20cfbb1516d4a0758e30d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011089
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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 2019-02-11 10:25:13 -08:00
Mahantesh Kumbar
de3ff22726 gpu: nvgpu: ACR LSF loader config changes 
LSF loader cleanup, on gm20b/gp10b PMU falcon & other GR falcons
uses different struct to store loader config which needs different
functions to fill LSF loader config data, but on gv11b/gv10x/tu10a
uses common falcon struct to store loader config, so made single
function to fill LSF loader config data using ACR LSF struct &
removed duplicate code.

Removed ACR LSF loader ops which were part of PMU ops
to cleanup dependency

JIRA NVGPU-1148

Change-Id: I681829e05463d2517a4049433d8b0de3adeb06d9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012853
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2019-02-11 03:28:49 -08:00
Mahantesh Kumbar
7b933d58e0 gpu: nvgpu: ACR refactor to manage LSF ucodes 
Added data struct under ACR struct to manage LS falcons ucode
as LS falcon ucode holds multiple properties & can be set at acr
init stage to bootstrap LS falcons as required, at present LS falcons
code is part ACR & partially part of PMU code to setup LSF bootstrap,
so, needed to clean up the dependency.

JIRA NVGPU-1148

Change-Id: Ie206e129e3db838041db44d5227ab76a1de991c8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012763
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2019-02-11 03:28:41 -08:00