nvgpu_timeout_init() returns an error code only when the flags parameter
is invalid. There are very few possible values for flags, so extract the
two most common cases - cpu clock based and a retry based timeout - to
functions that cannot fail and thus return nothing. Adjust all callers
to use those, simplfying error handling quite a bit.
Change-Id: I985fe7fa988ebbae25601d15cf57fd48eda0c677
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
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* As of now, working on multiple chip bringup in nvgpu-next repo has
an issue because we end with losing control on source code (hard to
find which part of the code belongs to which chip) and it's valuable
history this affects chip migration on release.
* To support multiple chip bringup simultaneously, we need new
guidelines to avoid losing control on source code and make migration
easier. This change adds links to nvgpu-next repo.
* Updated return code to ENODEV for consistency
* Updated ACR unittest to work with ENODEV return code
NOTE:
These are the initial set of infrastructure changes, guidelines
will evolve, and source code will get updated accordingly.
Based on future chip features, Which part of the source code falls
under nvgpu-next repo is decided.
JIRA NVGPU-6574
Change-Id: I81827e35d189c55554df00e255b527a4473e0338
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
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Replace all nvgpu_next functions/structs either by 1) collapsing them
into nvgpu legacy functions/structs 2) renaming them as follows:
- nvgpu_next_*() => nvgpu_(ga10b/ga100)_*()
- nvgpu_next_*() => (ga10b/ga100)_*()
- nvgpu_next_*() => nvgpu_*() [only if this doesn't cause collision]
- nvgpu_next_*() = > nvgpu_*_extra()
Create hal.sim unit and move Ampere+ SIM code into it.
Jira NVGPU-4771
Change-Id: I215594a0d0df4bd663bd875a0d0db47bcb9ff6a2
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548056
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The CONFIG_NVGPU_NEXT config is no longer required now that ga10b and
ga100 sources have been collapsed. However, the ga100, ga10b sources
are not safety certified, so mark them as NON_FUSA by replacing
CONFIG_NVGPU_NEXT with CONFIG_NVGPU_NON_FUSA.
Move CONFIG_NVGPU_MIG to Makefile.linux.config and enable MIG support
by default on standard build.
Jira NVGPU-4771
Change-Id: Idc5861fe71d9d510766cf242c6858e2faf97d7d0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
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Passing branch of nvgpu_timeout_peek_expired was not covered due to jump
over it in nvgpu_falcon_mem_scrub_wait. Remove that jump to cover the
branch.
Add unit test for covering the error handling in case of read from
DMEM control register returns invalid data using fault injection.
JIRA NVGPU-4814
Change-Id: I9f99186bd2b1c5f39ead130d3161d3e7fa622ac4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2272937
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Add unit tests to cover the invalid falcon port access, falcon sw init
switch cases, nvgpu_falcon_set_irq, nvgpu_timeout_init failure branch
coverage.
Compile out the functions nvgpu_falcon_get_mem_size & falcon_bootstrap
as they are needed by LS PMU and VBIOS code. For iGPU safety the
falcon functions needing these will call the HAL APIs directly.
This way we avoid the unreachable code as well. Updated the
prototype of falcon bootstrap HAL API as that doesn't return
any error.
With these changes, we get 100% line coverage for common.falcon unit.
JIRA NVGPU-2214
Change-Id: I1fe653d97c1a6a1521d7da38f171928dda58c5b5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258311
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PMU IRQs were not enabled assuming entire functionality for LS PMU.
Debugging early init issues of PMU falcon ECC errors triggered
during nvgpu power-on will be cumbersome if interrupts are not
enabled early. FMEA analysis of the nvgpu init path also
requires this interrupt be enabled earlier.
Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron.
pmu_enable_irq is updated to enable interrupts differently for
safety and non-safety. PMU interrupts disabling is moved out
of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new
wrapper API nvgpu_pmu_enable_irq.
PMU ECC init and isr mutex init is moved to the beginning of
nvgpu_pmu_early_init as for safety, ls pmu code path is
disabled. Fixed the pmu_early_init dependent and mc
interrupt related unit tests.
Update the doxygen for changed functions.
JIRA NVGPU-4439
Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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nvgpu_falcon_setup_bootstrap_config functionality can be kept static.
nvgpu_falcon_bl_bootstrap and nvgpu_falcon_bl_info are removed as it
is replaced by nvgpu_falcon_hs_ucode_load_bootstrap.
Update the test case accordingly, SWUTS and doxygen comments. Other
nits addressed about doxygen documentation.
JIRA NVGPU-2412
Change-Id: Idaa670ce6d6d6b735b4a2af34e1f1a229ff2a3e9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2220089
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Moving HS ucode bootstrap from ACR unit to Falcon unit as HS ucode
bootstrap needs to be accessed by multiple units. Currently FB unit
calls ACR unit function to do self HS load & bootstrap memory unlock
HS ucode. This adds dependency on ACR unit which is not correct. So,
moving to Falcon unit to make it generic.
JIRA NVGPU-3811
Change-Id: I3696296c9df661d821199cb93872265ef6d10bfc
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195016
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Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.
The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.
JIRA NVGPU-3820
Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
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Advisory Rule 5.9 states that identifiers that define objects or
functions with internal linkage should be unique.
This change eliminates an Advisory Rule 5.9 violation in our falcon
code involving falcon_sw_init() by renaming it to
falcon_sw_chip_init().
Jira NVGPU-3178
Change-Id: Ia064f383131ad3a7db56b5dcc02c754a7cc3e6f6
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2190094
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emem related handling is specific to DGPU hence compile it out.
falcon_sw_init for platforms other than gv11b is also compiled
out.
Restored the DGPU falcons handling as the falcon common sw
init handling has case for initialization of unsupported
falcons that needs to be covered.
JIRA NVGPU-898
Change-Id: I41e886aba2aead052f3ef00278309759dd410df3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2160233
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This change switches nvgpu_timeout_peek_expired() to return a bool
instead of an int to remove advisory rule MISRA 10.5 violations.
MISRA 10.5 states that the value of an expression should not be
cast to an inappropriate essential type.
JIRA NVGPU-3798
Change-Id: I5cf9badaf07493e11a639e47ae4cf221700134ff
Signed-off-by: Scott Long <scottl@nvidia.com>
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Following common and corresponding hal functions are non-safe. They are
either required for intr handling or for debug. Compile them out for
igpu safety release. Moved corresponding HALs to falcon_gk20a.c.
nvgpu_falcon_copy_from_emem
nvgpu_falcon_copy_to_emem
nvgpu_falcon_clear_halt_intr_status
nvgpu_falcon_set_irq
nvgpu_falcon_copy_from_dmem
nvgpu_falcon_copy_from_imem
nvgpu_falcon_print_dmem
nvgpu_falcon_print_imem
nvgpu_falcon_get_ctls
nvgpu_falcon_dump_stats can be used in the safety debug build.
JIRA NVGPU-898
JIRA NVGPU-2214
Change-Id: Icb7f904b088aa74b976f75a6a0ecdb783486bab3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152978
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Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.
This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.
Jira NVGPU-3476
Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
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Since dGPU support is not required for initial safety release, compile
out dGPU sw and hal implementations except below files that are used
by gv11b currently: acr_sw_gv100.c, engine_status_gv100.c, gr_gv100.c
gr_config_gv100.c and hwpm_map_gv100.c.
JIRA NVGPU-3062
Change-Id: I8a6bc8b235e7e5eac5b0e76147b8bd12f9abbd2d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119586
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Access to falcon's EMEM has to be synchronized to ensure atomic access
to EMEM control and data registers. Add this locking.
Not all falcons support EMEM hence handle mutex based on the enabled
flag emem_supported that is set only for TU104 currently.
JIRA NVGPU-1993
Change-Id: Idaedfb564ea0068d4690a2717d7983eb2384a69f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030618
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Earlier falcon HAL ops were embedded in the falcon structure. For clear
separation of common and HAL these ops will have to be accessed through
g->ops.falcon interfaces.
With these changes nvgpu_falcon_* functions directly call falcon gpu
ops functions for falcon. Falcon registers and HAL functions are
exported from falcon_gk20a.h. HAL files per platform are now
updated with base falcon functions.
Falcon software state such as is_falcon_supported, is_interrupt_enabled
and flcn_base are set from software init functions defined per chip.
JIRA NVGPU-2038
Change-Id: Ib1729d2833cd2c6c7b2c8ed7cbc17d4d6daeba73
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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This struct was earlier moved to falcon_priv.h to give exclusive access
to only falcon unit. However with HAL unit needing access to this we
need to move it public header nvgpu/falcon.h.
JIRA NVGPU-1993
Change-Id: Ia3b211798009107f64828c9765040d628448812a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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Semantics of the engine bootloader bootstrap are to set falcon mailbox0
register to non-zero value and verify that it is cleared to ascertain
successful completion of bootstrap.
Read was done in the engine bl_bootstrap related functions. Hence move
the write as well to those functions.
JIRA NVGPU-1993
Change-Id: I6d04148fbf1d517f0af8b4cfc2ee144d38704647
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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