-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files
JIRA NVGPU-3418
Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
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Hal API g->ops.gr.halt_pipe() is defined in unsafe unit hal.gr.gr
It is called from safe unit, and it calls into API
g->ops.gr.falcon.ctrl_ctxsw() which is also safe
Hence get rid of unsafe API g->ops.gr.halt_pipe().
Caller now directly calls hal.gr.falcon API to halt pipe
Jira NVGPU-3506
Change-Id: I5439cb79431795fc7c22384832cf632d6db03316
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127755
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Move some interrupt handling hals from hal.gr.gr unit to hal.gr.intr
unit as below
g->ops.gr.intr.set_hww_esr_report_mask()
g->ops.gr.intr.handle_tpc_sm_ecc_exception()
g->ops.gr.intr.get_esr_sm_sel()
g->ops.gr.intr.clear_sm_hww()
g->ops.gr.intr.handle_ssync_hww()
g->ops.gr.intr.log_mme_exception()
g->ops.gr.intr.record_sm_error_state()
g->ops.gr.intr.get_sm_hww_global_esr()
g->ops.gr.intr.get_sm_hww_warp_esr()
g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask()
g->ops.gr.intr.get_sm_hww_warp_esr_pc()
g->ops.gr.intr.tpc_enabled_exceptions()
g->ops.gr.intr.get_ctxsw_checksum_mismatch_mailbox_val()
Rename gv11b_gr_sm_offset() to nvgpu_gr_sm_offset() and move to
common.gr.gr unit
All of above functions and hals will be needed in safety build
Jira NVGPU-3506
Change-Id: I278d528e4b6176b62ff44eb39ef18ef28d37c401
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127753
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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This flag is added to compile out below features from
safety build
-set_preemption_mode
-channel_enable
-channel_disable
-channel_preempt
-channel_force_reset
-tsg_enable
-tsg_disable
-tsg_preempt
-tsg_event_id_ctrl
-post_event_id
JIRA NVGPU-3516
Change-Id: I935841db766f192f62598240c0e245a2959555be
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126829
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renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow
nvgpu naming standard
Compile out LS PMU files when PMU RTOS support is
disabled for safety build by setting NVGPU_LS_PMU
build flag to 0
JIRA NVGPU-3418
Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127794
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Compile out PMU RTOS specific PMU HAL code when
PMU RTOS support is disabled for safety build by setting
NVGPU_LS_PMU build flag to 0
Added new functions for gv11b PMU HAL to easy compile out
other PMU HAL files.
Replaced all gk20a_writel/readl calls with nvgpu_writel/readl
calls in hal/pmu/pmu_gv11b.c files
JIRA NVGPU-3418
Change-Id: I7c315349aa95721990dc7b1570383669bcb6221f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117691
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pmu_gk20a.c includes hw_mc_gk20a.h other than hw_pwr_gk20a.h
to access & configure pmu interrupt, this breaks single hw header
for HAL file.
Moved PMU interrupt enable to MC unit by creating/modifying current
mc ops intr_unit_config to intr_pmu_unit_config to configure PMU
interrupt specifically as this ops is only used by PMU unit
JIRA NVGPU-3239
Change-Id: I2514f17197708047b46ea712cf4569a5b3bfab2a
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126420
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pbdma fault recovery function reads pbdma status info to retrieve
channel id, tsg id and engine id. pbdma interrupts can only be cleared
after that information has been read otherwise because pbdma exits
from stall state, channel/tsg/engine could have changed and fault
recovery function reads information different from that when interrupt
is issued.
Bug 2123866
Change-Id: Ia0e0462ae02ec89a333c81bd933a74fbae8ae1e7
Signed-off-by: Peng Liu <pengliu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123774
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Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.
Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.
Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.
Bug 2515097
Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
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Some functions are not accessing hardware directly
but are being called using HAL ops: For example
g->ops.pmu.pmu_elpg_statistics,
g->ops.pmu.pmu_pg_init_param,
g->ops.pmu.pmu_pg_supported_engines_list,
g->ops.pmu.pmu_pg_engines_feature_list,
g->ops.pmu.pmu_is_lpwr_feature_supported,
g->ops.pmu.pmu_lpwr_enable_pg,
g->ops.pmu.pmu_lpwr_disable_pg,
g->ops.pmu.pmu_pg_param_post_init,
g->ops.pmu.save_zbc
Change the function access by using sw ops, like:
Create new functions:
int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
struct pmu_pg_stats_data *pg_stat_data);
void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries);
bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g,
u32 feature_id);
JIRA NVGPU-3209
Change-Id: I6db9b43c7c4a5054720a72487302b740b091044d
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110963
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Some functions are not accessing hardware directly
but are being called using HAL ops: For example
.pmu_init_perfmon = nvgpu_pmu_init_perfmon_rpc,
.pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling_rpc,
.pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling_rpc,
.pmu_perfmon_get_samples_rpc = nvgpu_pmu_perfmon_get_samples_rpc,
These were being called by:
g->ops.pmu.pmu_init_perfmon,
g->ops.pmu.pmu_perfmon_start_sampling,
g->ops.pmu.pmu_perfmon_stop_sampling,
g->ops.pmu.pmu_perfmon_get_samples_rpc
Change the function access by using sw ops, like:
Create new functions:
int nvgpu_pmu_perfmon_init(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_start_sampling_perfmon(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_stop_sampling_perfmon(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_get_samples_rpc_perfmon(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
and based on hardware chip call the chip specific
perfmon sw init function: nvgpu_gv11b_perfmon_sw_init() and
nvgpu_gv100_perfmon_sw_init() and assign the sw ops for perfmon
JIRA NVGPU-3210
Change-Id: I2470863f87a7969e3c0454fa48761499b08d445c
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109899
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- To enable FECS trace support, nvgpu should set the MSB
of the read pointer (MAILBOX1).
- The ucode will check if the feature is enabled/disabled
before writing a record into the circular buffer. If the
feature is disabled, it will not write the record.
- If the feature is enabled and the buffer is not allocated,
HW will throw a page fault error.
Bug 2459186
Change-Id: I71daf6fdb1bb67974f6e51e091f868cb08d3b0bf
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111028
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Create a new unit for pramin. This is used for handling the HAL init for
pramin. Move the setup of the pramin gops for to the new pramin HAL.
This eliminates the need for the nvgpu.common.hal.init unit from having
to include the HW header file for pramin.
JIRA NVGPU-3274
Change-Id: I4e2402cf3e4eeb53e0fa5b6428624f8f3668fcd0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108805
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Move the get_litter() functions out of the main hal init to its own
source file for each device. This allows removal of the hw_proj_*.h
files in the main hal init file. This reduces the number of hw header
includes per file creating better code isolation.
JIRA NVGPU-3274
Change-Id: I9e04294434acf274ccc2236646f0f15f710a6976
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107751
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create a new unit common.fbp which initializes fbp support and provides
APIs to retrieve fbp data.
Create private header with below data
struct nvgpu_fbp {
u32 num_fbps;
u32 max_fbps_count;
u32 fbp_en_mask;
u32 *fbp_rop_l2_en_mask;
};
Expose below public APIs to initialize/remove fbp support:
nvgpu_fbp_init_support()
nvgpu_fbp_remove_support()
vgpu_fbp_init_support() for vGPU
Expose below APIs to retrieve fbp data
nvgpu_fbp_get_num_fbps()
nvgpu_fbp_get_max_fbps_count()
nvgpu_fbp_get_fbp_en_mask()
nvgpu_fbp_get_rop_l2_en_mask()
Use above APIs to retrieve fbp data in all the code.
Remove corresponding fields from struct nvgpu_gr since they are no
longer referred from that structure
Jira NVGPU-3124
Change-Id: I027caf4874b1f6154219f01902020dec4d7b0cb1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108617
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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channel.c calling nvgpu_gr_flush_channel_tlb() creating circular
dependency between gr and fifo. Avoid this by moving channel tlb
related data to struct nvgpu_gr_intr in gr_intr_priv.h and
initialized this data in gr_intr.c.
Created following new gr intr hal and called this new hal from channel.c
void (*flush_channel_tlb)(struct gk20a *g);
JIRA NVGPU-3214
Change-Id: I2d259bf52db967273030680f50065af94a17f417
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109274
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Remove gr_priv.h from outside gr files.
Add hal function in gr.init for get_no_of_sm. This helps
to avoid dereferencing gr in couple of files for g->gr->config and
avoid gr_priv.h include in those files.
Replace nvgpu_gr_config_get_no_of_sm call with
g->ops.gr.init.get_no_of_sm for files outside gr unit.
Jira NVGPU-3218
Change-Id: I435bb233f70986e31fbfcb900ada3b3bda0bc787
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109182
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There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.
Much of this is fairly straightforward copy/paste and updates to the
HAL init files.
The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.
JIRA NVGPU-2042
Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
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The alloc_insty_block() function in the MM HAL is not a HAL. It does
not abstract any HW accesses; instead it just wraps a dma allocation.
As such remove it from the HAL and move the single gk20a implementation
to common/mm/mm.c as nvgpu_alloc_inst_block().
JIRA NVGPU-2042
Change-Id: I0a586800a11cd230ca43b85f94a35de107f5d1e1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109049
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- Create nvlink_bios.c/.h files to separate out nvlink
related bios code.
- Create bios_sw_<chip speciific>.c/.h files to separate
out chips specific bios code.
- Create hal files for bios under hal/bios/ and move
hardware specific code there.
- Move hardware accessing hal files from common/top
to hal/top
JIRA NVGPU-2071
Change-Id: Ia466f1cd8947540b07b237e891312123df2c6b46
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107371
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Move remaining chip specific gr hal files to hal.gr.gr unit.
Remove unused headers include from hal files in hal.gr.gr unit
Update gr hal headers include location in the files currently
using these headers.
Jira NVGPU-3219
Change-Id: Ic632020a90ac4b8ac1e0359e979864b42f0ef2c0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105489
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Renamed
- gk20a_tsg_set_runlist_interleave -> nvgpu_tsg_set_interleave
Moved set_interleave from runlist to tsg
- runlist.set_interleave -> tsg.set_interleave
Existing HAL was only setting tsg->interleave, and was not
accessing any register. This is now done in nvgpu_tsg_set_interleave
and tsg.set_interleave is only used in vgpu case.
Jira NVGPU-3156
Change-Id: I5dac1305afcbd950214316289cf704ee8b43fc89
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100610
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Moved the following HALs from fifo to tsg
- set_timeslice
- default_timeslice_us
Renamed
- gk20a_tsg_set_timeslice -> nvgpu_tsg_set_timeslice
- min_timeslice_us -> tsg_timeslice_min_us
- max_timeslice_us -> tsg_timeslice_max_us
Scale timeslice to take into account PTIMER clock in
nvgpu_runlist_append_tsg.
Removed gk20a_channel_get_timescale_from_timeslice, and
instead moved timeout and scale computation into runlist HAL,
when building TSG entry:
- runlist.get_tsg_entry
Use ram_rl_entry_* accessors instead of hard coded values
for default and max timeslices.
Added #defines for min, max and default timeslices.
Jira NVGPU-3156
Change-Id: I447266c087c47c89cb6a4a7e4f30acf834b758f0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100052
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Currently max_css_buffer_size is incorrectly stored in struct nvgpu_gr
Add a new hal g->ops.css.get_max_buffer_size() to get the size and
remove the variable from struct nvgpu_gr
Jira NVGPU-3125
Change-Id: If78fd86559526b84031051e281a98327a46fc11d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105652
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Move the gk20a_init_mm_setup_hw to common code. This function just
calls HALs to initialize various bits of HW. However, since this
code assumes that (some of) the HALs are present this code is treated
as a vGPU HAL (that is it's NULL for vGPU).
This patch also renames the MM HW init HAL.
Sicne the gv11b variant of this setup_hw HAL did have some differences
from the gk20a version the new common version required some work. The
gv11b code was copied into the common function but now the gv11b
specific calls were HAL'ified (since they will need to be anyway for
the MMU fault buf code) and protected by an if-condition.
JIRA NVGPU-2042
Change-Id: I959293394ee8793923d858ee37b7ce346096654f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104541
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This "HAL" exists to handle the vGPU specific bind channel operation.
This patch moves the native function implementation to common/mm/vm.c
and renames the gk20a to nvgpu to follow the convention for vGPU vs
native HAL functions.
JIRA NVGPU-2042
Change-Id: I02b9ebf0d53d58a6d2ede544e34f2b8ff1b1eb42
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104540
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