The GV100 PMU ucode needs to be updated to add support
for PS3.5 Clock Programming boardobj.
The entrysize in GV100 PMU ucode is increased to match
that on Turing R400 PMU ucode.
JIRA NVGPU-1153
Change-Id: Ied3163522bf4e124849517e90bfa42fe4b320a96
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918174
Reviewed-by: Automatic_Commit_Validation_User
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1. Add VBIOS PS3.5 Clk programming table parsing code.
2. Update pmuifclk.h to match R400 pmu ucode pmuifclk.h
3. New clk_prog boardobj types have been added to support
PS3.5 and to match the pmu ucode side changes
4. Add PS3.5 related construct and pmudatainit fops
5. PS3.5 clk programming table has secondary VF curve entries.
Though these entries are currently marked as invalid for
all SKUs, we need to add them to match struct sizes on PMU.
6. The pmuifclk.h nvgpu<->pmu interface changes needed for
Turing(PS3.5) are NOT compatible with GV100 branched ucode.
The secondary VF curve entries added for PS3.5 increase the
entrysize breaking compatibility with GV100.
7. This change is therefore dependant on GV100 PMU ucode changes
which increase the entrysize on GV100 pmu side.
JIRA NVGPU-1153
Change-Id: I868e503f87731442aae6503872ade4c208831d34
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1842627
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Fixed timeout checking flow in sync-unmap where timeout message could
be printed while there is not a timeout.
The original codeflow doesn't check refcount of a mapped_buffer again
after 10ms waiting. So if the buffer is released during the last
round of waiting, the timeout message will still be printed. The new
codeflow combines refcount and timeout checking. So that there won't
be an inconsistency between the two.
Bug 200434475
Change-Id: Id0a0aebcb24906a1ec7113e669227788e729564b
Signed-off-by: Kyle Guo <kyleg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1930236
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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For a long time now, the ALLOC_GPFIFO_EX channel IOCTL has done much
more than just gpfifo allocation, and its signature does not match
support that's needed soon. Add a new one called SETUP_BIND to hopefully
cover our future needs and deprecate ALLOC_GPFIFO_EX.
Change nvgpu internals to match this new naming as well.
Bug 200145225
Change-Id: I766f9283a064e140656f6004b2b766db70bd6cad
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1835186
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When turning off CONFIG_DEBUG_FS, there are build errors:
drivers/gpu/nvgpu/os/linux/os_ops_gp106.o: In function `nvgpu_fecs_trace_init_debugfs':
os_ops_gp106.c:(.text+0x8): multiple definition of `nvgpu_fecs_trace_init_debugfs'
drivers/gpu/nvgpu/os/linux/os_ops_gp10b.o:os_ops_gp10b.c:(.text+0x0): first defined here
drivers/gpu/nvgpu/os/linux/os_ops_gv100.o: In function `gp106_therm_init_debugfs':
os_ops_gv100.c:(.text+0x0): multiple definition of `gp106_therm_init_debugfs'
drivers/gpu/nvgpu/os/linux/os_ops_gp106.o:os_ops_gp106.c:(.text+0x0): first defined here
drivers/gpu/nvgpu/os/linux/os_ops_tu104.o: In function `gv100_clk_init_debugfs':
os_ops_tu104.c:(.text+0x0): multiple definition of `gv100_clk_init_debugfs'
drivers/gpu/nvgpu/os/linux/os_ops_gv100.o:os_ops_gv100.c:(.text+0x10): first defined here
This is because those functions aren't marked as static.
So this patch just simply fixes the bug.
Bug 2284925
Change-Id: I1da39345c653dfb50c509adb0c822b4657646c56
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929355
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This adds a fault injection module to the POSIX build that can be added
to modules (for example k*alloc) then exercised in unit tests. The unit
tests can then verify that the driver units handle errors from the
modules.
JIRA NVGPU-1235
Change-Id: I9d9e443608e3d2026e165a62f7a7f011df96fd54
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1927455
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: If80c848a47455e631187669b9a67f444dab1e5bc
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921503
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I1e8659ee6759b05dec93bef83928bae77a9ee01b
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812198
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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If the total size of SGLs is lower than the size to copy,
we will reach the end of the list so the sgl var will become NULL,
and calling nvgpu_sgt_get_length will cause a null pointer dereference.
This change will cause a BUG() which should be clearer than a NULL
pointer dereference. There is no easy way to add more advanced error
checking and handling, and an SGL bug would most likely be linked to
another bug in the OS or OS layer.
JIRA NVGPU-1279
Change-Id: Ide83f2b91ecae25f3a0f3202febfb115110315d7
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1923706
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-Added method nvgpu_tu104_acr_ahesasc_sw_init()
to set ACR-AHESASC properties.
-Added method nvgpu_tu104_acr_asb_sw_init() to
set ACR-ASB properties.
-Modified method nvgpu_tu104_acr_sw_init() to
call ACR AHESASC/ASB init & set bootstrap_owner
to LSF_FALCON_ID_GSPLITE by removing older support
of default ACR executing on SEC2.
-Added method tu104_bootstrap_hs_acr to execute
ACR AHESASC & ASB ucode.
-Execute ACR-AHESASC(ACR hub encryption setter and
signature checker) on SEC2 falcon to copy ucode
blob from non-wpr to wpr & lockdown wpr then
perform signature verification of LS falcon ucode
whitout doing any LS flacon bootstrap.
-Once first stage of ACR is successful then execute
ACR-ASB(ACR SEC2 booter) on GSP falcon to bootstrap
SEC2-RTOS on sec2 falcon to perform PMU & GR
falcons bootstrap.
-Enable SEC2 RTOS support by setting
NVGPU_SUPPORT_SEC2_RTOS to true
-Added tu104 ACR remove support to clear
allocated space
JIRA NVGPUT-134
Change-Id: I2d1777af83feda5e8f6845876177cce062c43ace
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918937
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The chid member of the channel_gk20a struct was being used as a unsigned
value. By being declared as an int, it was causing MISRA 10.3 violations
for implicit assignment of different types.
JIRA NVGPU-647
Change-Id: I7477fad6f0c837cf7ede1dba803158b1dda717af
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918470
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MISRA 10.3 rule disallows implicit assignments between different
essential types. This adds casts to address some of these violations
in fifo_gk20a.
This also removes unnecessary bar1 test in
gk20a_fifo_handle_sched_error() (rather than add messy casting).
JIRA NVGPU-647
Change-Id: Ic8700459e47a59dc03e0149f6efb060efa4d4e42
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917635
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MISRA 10.3 forbids assigning an object with a narrower essential type
or of a different essential type. This addresses the file
fifo_gk20a.c where constants were in violation.
JIRA NVGPU-647
Change-Id: I0ecf9b0ce40de76464efbde9e9c9b6aa69d80ec0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917630
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Move the wait_cmd_buffer programming for channel_sync->wait_fd to
channel_sync.c. nvgpu_os_fence->program_waits
interface is now removed. channel_sync can directly retrieve
syncpt/semaphore from the interfaces of struct nvgpu_os_fence_syncpt
and struct nvgpu_os_fence_sema and use it for the wait programming.
Also, change int to u32 for some variables such as num_fences,
max_wait_size and wait_cmd_size.
Jira NVGPU-1093
Change-Id: I19c1b10d676caff49ce57861091f7f0ea65e7676
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829719
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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channel_sync->wait_fd depends upon nvgpu_os_fence->program_waits which
invokes a channel_sync method and this leads to a circular dependency.
In order to resolve the above, constructed struct nvgpu_os_fence_sema and
struct nvgpu_os_fence_syncpt with interfaces that support conversion
between struct nvgpu_os_fence to above. Also, added the following
interfaces for retrieving syncpts and semaphore from the above structs
respectively.
void nvgpu_os_fence_sema_extract_nth_semaphore(...)
int nvgpu_os_fence_sema_get_num_semaphores(...)
void nvgpu_os_fence_syncpt_extract_nth_syncpt(...)
int nvgpu_os_fence_syncpt_get_num_syncpoints(...)
These enable channel_sync code to directly program the cmd_bufs
based on the syncpts and semaphore received using the above APIs
instead of the current state of doing the wait programming from
within nvgpu_os_fence's interfaces.
Jira NVGPU-1093
Change-Id: Ie411f0ba60bca38f66a0024f5dfca03ef0b836eb
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1827475
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Current gating reglist includes both unicast and broadcast registers
Having unicast registers is unnecessary since corresponding broadcast
registers are already being written
Also some of the unicast registers were manually commented out in
auto generated file to avoid PRI timeouts
Re-generate gating reglist with new script which skips unicast
registers so that we don't have to manually update auto generated
file
Bug 2150883
Change-Id: I0b099d23049d8c7154a9b1fb709dd9e6709cdf38
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1922579
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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The PMM type-specific broadcast->unicast expansion calculation
was using incorrect values. This caused the invalid register
accesses to be generated.
This change HAL-ifies the values, so that the expansion will be
performed correctly.
Bug 200454109
Change-Id: I96c15de27b5e16e4db2e788fd98e6bf7d6e7d564
Signed-off-by: Matthew Braun <matthewb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1919476
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struct gk20a from gk20a.h needs defination of struct gk20a_ce_app
and ce2_gk20a.h needs defination of struct gk20a. This creates
a circular dependency.
Fix this by making gk20a_ce_app a pointer to skip knowing the
complete type details and using forward declarations for struct
gk20a_ce_app and struct gk20a.
The gk20a_ce_app pointer is alloc'ed in gk20a_init_ce_support()
and free'ed in gk20a_ce_destroy.
JIRA NVGPU-611
Change-Id: I4d62d5f2b2d1492db73bae69f90a1fe5586fba76
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917945
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gv100 hw headers
by renaming them to follow the convention, 'NVGPU_HEADER_NAME'.
JIRA NVGPU-1028
Change-Id: I78945233d16e47483b3c1f03fc0c7ca5774c3e95
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1850997
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gp10b hw headers
by renaming them to follow the convention, 'NVGPU_HEADER-NAME'.
JIRA NVGPU-1028
Change-Id: I82575d34c1d73542b93f95759e39d63a291514fb
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829945
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gm20b hw headers
by renaming them to follow the convention, 'NVGPU_HEADER_NAME'.
JIRA NVGPU-1028
Change-Id: I49e4af38b83d54a5814ab3e9246a8af1f1e55fe8
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829976
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gp106 hw headers
by renaming them to follow the convention, 'NVGPU_HEADER-NAME'.
JIRA NVGPU-1028
Change-Id: I280aed3ca6d903d95c8fd8261a621591fbe4411e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829942
GVS: Gerrit_Virtual_Submit
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gv11b hw headers
by renaming them to follow the convention, 'NVGPU_HEADER-NAME'.
JIRA NVGPU-1028
Change-Id: Ifceda60d2fbd33bdb5d05bf1e484819d88dedd1e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829718
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in tu104 hw headers
by renaming them to follow the convention, 'NVGPU_HEADER-NAME'.
JIRA NVGPU-1028
Change-Id: Id5f46c5cb50765f178379b23f660f759fa881e9b
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921250
Reviewed-by: Automatic_Commit_Validation_User
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MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in gk20a hw headers
by renaming them to follow the convention, 'NVGPU_HEADER-NAME'.
JIRA NVGPU-1028
Change-Id: Ib14774860a784bf066dd958ae1056ecc0115be71
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829809
Reviewed-by: Automatic_Commit_Validation_User
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Add new separate unit common/perf/cyclestats_snapshot.c and add
corresponding header file include/nvgpu/cyclestats_snapshot.h
This unit is h/w independent and simply calls gops.perf.* HALs
exposed by perf unit to do the h/w configurations
Also remove gv11b/css_gr_gv11b.* files as h/w specific sequence
implemented in them is already moved to perf unit
Rename all cyclestats_snapshot HALs in the form nvgpu_css_*()
Jira NVGPU-1103
Change-Id: I303f6becb313ac918e06c495a5fe299947a1f0b1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1916652
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This patch moves the increment and decrement of the user mapped
buffer count to the insert/remove mapped buffer functions since
this value should only ever change when these functions are called.
Bug 200105199
Change-Id: I5b0a86d00e9e948c48e313153a668eb2e10fca49
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917791
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