Do some doxygen cleanup for the whitelisting macros:
- Previously doxygen documentation was being generated for the no-op
whitelisting macros. Enable the NV_IS_COVERITY define in the
doxygen build. This generates doxygen documentation for the actual
whitelisting macros.
- Create a doxygen group for the whitelisting macros. This adds
additional documentation for the whitelisting macros.
- Add doxygen line breaks
JIRA NVGPU-3820
Change-Id: Id452147a3a909da7981303d0908f2aff4a2ff86b
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194711
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Some of the debugger and graphics specific functions were already
not being used in safety build. Compile out their definitions
and declarations as well.
Also, fail preemption set call if non-zero graphics preemption mode
is requested in safety build.
Jira NVGPU-3967
Change-Id: Iaf5e3bd58e6096da40301b79e9295a6c5893cd4a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191764
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Reduce code complexity of gr_intr_handle_tpc_exception and
nvgpu_gr_intr_handle_gpc_exception functions below 10
Move multiple if statements from those functions to sub
functions to reduce complexity
Jira NVGPU-3975
Change-Id: I443a26d8addf2129bd5b3e512a59f4d4ecc922ea
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191296
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Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.
The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.
JIRA NVGPU-3820
Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180600
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Advisory Rule 5.9 states that identifiers that define objects or functions
with internal linkage should be unique.
This change eliminates an Advisory Rule 5.9 violation in our acr code
due to duplicate definitions of flcn64_set_dma() by placing a single
inline version in flcnif_cmn.h.
Jira NVGPU-3178
Change-Id: Id9171059ee490cbadd46204f520fccefc44669f7
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2190074
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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g->ops.gr.init.get_access_map() returns whitelist of register addresses
that can be accessed by SET_FALCON methods when added into pushbuffer.
SET_FALCON method does not need to be supported in safety.
Hence install an empty register access map in safety build by adding
a new flag CONFIG_NVGPU_SET_FALCON_ACCESS_MAP.
Compile out g->ops.gr.init.get_access_map() and code that writes
whitelist in access map buffer.
Note that we still need to configure base address of access map in
context image even for safety.
Jira NVGPU-3995
Bug 2686235
Change-Id: I111b46f96821a09929aff32fcba5bb2215c81b9a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2185469
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Replaced ch->mmu_debug_mode_enabled with ch->mmu_debug_mode_refcnt.
If channel is enabled multiple times by userspace, then ref count is
updated accordingly. There is an expectation that enable/disable
calls are balanced for setting channel's mmu debug mode.
When unbinding the channel, decrease refcnt for the channel until it
reaches 0.
Also, removed tsg parameter from nvgpu_tsg_set_mmu_debug_mode as it
can be retrieved from ch.
Bug 2515097
Change-Id: If334e374a55bd14ae219edbfd3b1fce5ff25c226
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2184702
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This patch adds nvgpu API in linux and posix to query vpr resize.
The new API nvgpu_is_vpr_resize_enabled() is used in
nvgpu_submit_channel_gpfifo().
Previously, if non-deterministic channel has timeout disabled and
GPU cannot railgate on some platform, then channel doesn't power ref
count and results in video freeze. To resolve non-determinstic channel
job tracking needs to be enabled if vpr resize is supported or if GPU
can railgate.
Bug 200532122
Change-Id: Icfbff6253762b195b2f5955749343974b1a7a269
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2171093
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For safety build, nvgpu driver should enter SW quiesce state
in case an uncorrectable error has occurred. In this state, any
activity on the GPU should be prevented, without powering off the GPU.
Also, a minimal set of operations should be used to enter SW quiesce
state.
Entering SW quiesce state does the following:
- set sw_quiesce_pending: when this flag is set, interrupt
handlers exit after masking interrupts. This should help mitigate
an interrupt storm.
- wake up thread to complete quiescing.
The thread performs the following:
- set NVGPU_DRIVER_IS_DYING to prevent allocation of new resources
- disable interrupts
- disable fifo scheduling
- preempt all runlists
- set error notifier for all active channels
Note: for channels with usermode submit enabled, userspace can
still ring doorbell, but this will not trigger any work on
engines since fifo scheduling is disabled.
Jira NVGPU-3493
Change-Id: I639a32da754d8833f54dcec1fa23135721d8d89a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2172391
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Rule 10.1 Requires that operands shall not be of an inappropriate
essential type.
Rule 14.3 Requires that controlling expressions shall not be
invariant.
Rule 20.7 Requires that expressions resulting from the expansion
of macro parameters shall be enclosed in parentheses.
Fix violations of above rules in the macro defined in cond unit.
Jira NVGPU-3878
Change-Id: Icd5758ae12210e68333c4ab820a36dc48c0aa29e
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2183647
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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The following violations are fixed in this patch
a) misra_c_2012_rule_2_1_violation: This code cannot be reached: "return
err;".
b) misra_c_2012_directive_4_7_violation: Calling function
"nvgpu_preempt_channel(g, ch)" which returns error information without
testing the error information.
c) misra_c_2012_rule_8_6_violation: "" is declared but never defined for
following functions
1) gm20b_dump_engine_status
2) gp10b_ramfc_setup
3) gp10b_ramfc_get_syncpt
4) gp10b_ramfc_set_syncpt
5) gk20a_fifo_intr_0_enable
6) gk20a_fifo_intr_0_isr
7) gk20a_fifo_handle_sched_error
8) gk20a_fifo_is_mmu_fault_pending
9) gk20a_fifo_intr_set_recover_mask
10) gk20a_fifo_intr_unset_recover_mask
11) gk20a_init_fifo_reset_enable_hw
12) gk20a_init_fifo_setup_hw
13) nvgpu_tsg_set_runlist_interleave
14) gm20b_dump_engine_status
15) gp10b_pbdma_channel_fatal_0_intr_descs
16) gp10b_pbdma_allowed_syncpoints_0_index_f
17) gp10b_pbdma_allowed_syncpoints_0_valid_f
18) gp10b_pbdma_allowed_syncpoints_0_index_v
19) gk20a_runlist_reschedule
The above functions declarations are now embedded within
CONFIG_NVGPU_HAL_NON_FUSA
d) The function nvgpu_channel_abort_clean_up has a UMD version and hence
its taken out of CONFIG_NVGPU_KERNEL_MODE_SUBMIT to avoid errors of
type c above.
Jira NVGPU-3881
Change-Id: I5f85c7070e1d2f0b18d14db07ce22a01c29f0e40
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2181032
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add doxygen documentation for gr/gr.h header.
Also add necessary plumbing to add common.gr unit documentation HTML
link.
Fix gr_init_reset_enable_hw() to return error code in case of error.
Compile nvgpu_gr_enable_ctxsw()/nvgpu_gr_disable_ctxsw() only if
debugger or recovery support is enabled.
Jira NVGPU-3911
Change-Id: Iaa942748a00aeffce9349cb0669d2cd5baca1e55
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180312
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- Add doxygen documentation.
- Remove unused fields of nvgpu_tsg struct:
-- timeslice_timeout
-- timeslice_scale
- Remove unused functions:
-- nvgpu_tsg_set_runlist_interleave
- nvgpu_tsg_post_event_id is not supported in safety build.
This function is moved under CONFIG_NVGPU_CHANNEL_TSG_CONTROL
compiler flag.
- Below functions are moved under CONFIG_NVGPU_KERNEL_MODE_SUBMIT
nvgpu_tsg_ctxsw_timeout_debug_dump_state
nvgpu_tsg_set_ctxsw_timeout_accumulated_ms
- Rename
gk20a_is_channel_active -> nvgpu_tsg_is_channel_active
release_used_tsg -> nvgpu_tsg_release_used_tsg
- nvgpu_tsg_unbind_channel_common declared static
- Fix build issue when CONFIG_NVGPU_CHANNEL_TSG_CONTROL is disabled
Remove CONFIG_NVGPU_CHANNEL_TSG_CONTROL for
nvgpu_gr_setup_set_preemption_mode as it is needed in safety build.
By default compute preemption mode will be set to WFI. CUDA will
change it to CTA during context init time.
JIRA NVGPU-3595
Change-Id: I8ff6cabc8b892c691d951c37cdc0721e820a0297
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2151489
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A call to exit the PMU state machine/kthread must
be prioritized over any other state change.
It was possible to set the state as PMU_STATE_EXIT,
signal the kthread and overwrite the state before
the kthread has had the chance to exit its loop.
This may lead to a "lost" signal, resulting in
indefinite wait during the destroy sequence.
Faulting sequence:
1. pmu_state = PMU_STATE_EXIT in nvgpu_pmu_destroy()
2. cond_signal()
3. pmu_state = PMU_STATE_LOADING_PG_BUF
4. PMU kthread wakes up
5. PMU kthread processes PMU_STATE_LOADING_PG_BUF
6. PMU kthread sleeps
7. nvgpu_pmu_destroy() waits indefinitely
This patch adds a sticky flag to indicate PMU_STATE_EXIT,
irrespective of any subsequent changes to pmu_state.
The PMU PG init kthread may wait on a call to
NVGPU_COND_WAIT_INTERRUPTIBLE, which requires a
corresponding call to nvgpu_cond_signal_interruptible()
as the core kernel code requires this task mask to
wake-up an interruptible task.
Bug 2658750
Bug 200532122
Change-Id: I61beae80673486f83bf60c703a8af88b066a1c36
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2181926
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Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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Change the directly called init functions to function pointers in the
HAL. This makes it more consistent. This also allows for writing more
comprehensive unit tests for nvgpu.common.init.
JIRA NVGPU-2239
Change-Id: I05d739a8f8a2e7d385322d93154206eb0bfddc10
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2173920
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Rename reserved identifier __here to label_here to fix
around 180 DCL37-C violations - "The reserved identifier "__here",
which is reserved for use as identifiers with file scope in both
the ordinary and tag name spaces, is declared.
JIRA NVGPU-3908
Change-Id: Iecaaa03674800bec919d71dc5fd226d362fc6f56
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2178457
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Advisory Rule 2.7 states that there should be no unused
parameters in functions.
This patch removes the unused 'post_event', 'fault_ch' and
'hww_global_esr' parameters from the following:
* gv11b_gr_intr_handle_l1_tag_exception()
* gv11b_gr_intr_handle_lrf_exception()
* gv11b_gr_intr_handle_cbu_exception()
* gv11b_gr_intr_handle_l1_data_exception()
* gv11b_gr_intr_handle_icache_exception()
These changes allowed the same parameters to be removed from the
the gr.intr.handle_tpc_sm_ecc_exception() interface.
Jira NVGPU-3178
Change-Id: I4d5dcbf2a5325e38782cdac67f9dd0b223fa1a18
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2171220
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Changes added to support "rmmod nvgpu" in dgpu simulation after gpu
poweron.
nvgpu_engine-wait_for_idle got stuck in busy mode for nvdec and nvec
engines in simulation as simulation doesnt support timeout.
These engines are not valid engines in nvgpu engine list.
Add nvgpu_engine_check_valid_id before checking engine status.
Simulation crash on accessing 0xb81604 top interrupt register.
Add func_priv_cpu_intr_top__size_1_v() function to get the supported
size than using default MAX_INTR_TOP_REGS.
nvlink is not supprted in dgpu simulation. Avoid warning for
-ENODEV return.
Avoid register read following gpu power off completion.
Bug 2498574
Change-Id: I9f9f1cf1ac4620242bda1d2cc0f29f51f81a6711
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2179930
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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CE app functionality from nvgpu is non-safe for igpu. CE engines init
/reset/cg related functionality is required in safety. Hence move the
CE app logic under CONFIG_NVGPU_DGPU flag and update the sources
accordingly.
JIRA NVGPU-3814
Change-Id: I37aa00b1184baccd5fe569ec315be60ac42dac9b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168956
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