Error: CERT INT30-C:
drivers/gpu/nvgpu/common/gr/ctx.c:644:
cert_violation: Unsigned integer operation
"gr_ctx->patch_ctx.mem.size / 4UL - 2UL" may wrap.
Error: CERT INT31-C:
drivers/gpu/nvgpu/common/gr/ctx.c:580:
cert_violation: Casting "gr_ctx->boosted_ctx" from "bool" to "unsigned int"
without checking its value may result in lost or misinterpreted data.
JIRA NVGPU-3409
Change-Id: Ib3c865d43ecd3c0eaaafd47b7b65111aa77689bd
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118521
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Add functions which perform addition, subtraction and
multiplication of u32 and u64 types in a secure way
returning an error if operand type cannot correctly hold
the operation result.
Also, add type casting functions which handle conversions to
ensure that a conversion doesn't result in lost or misinterpreted
data.
JIRA NVGPU-3432
Change-Id: I1a622a178a907cc3fe5e48317a5bb9267220bd74
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118520
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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NV_PGPC_PRI_MMU_DEBUG_CTRL is now context switched in gv11b
FECS ucode. Enable NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, so that
userspace can use NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE
ioctl for gv11b.
Bug 2515097
Change-Id: Ia9fb36cffc9e67cf96c31c50ffa4c59997258ce2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115019
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For some units, we want to use register spaces with
data already initialized with power-on register values.
Added the following routines:
- nvgpu_posix_io_register_reg_space
- nvgpu_posix_io_unregister_reg_space
Jira NVGPU-3476
Change-Id: Id4f5beb5e5d6b4af795e2eb58ccee13d2cfa6da5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120563
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nvgpu userspace and test builds are prepared for both host/x86 and
target/aarch64. nvgpu common cflags file was included in the
Makefile of target builds. Include it in the host build
Makefile as well.
This makes sure we run the same config of qnx and nvgpu userspace
and test builds for MISRA, Coverage.
nvgpu shared config file defines the make variables and cflags app-
licable to nvgpu common shared by qnx, nvgpu userspace, test builds.
Note that cflags are added to variable NVGPU_COMMON_CFLAGS that need
to be used by the parent Makefile to update corresponding cflags
variable.
JIRA NVGPU-3062
Change-Id: Ia7a879698220f3b73aae3f02416cab28432531e0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119319
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We prepare new exports file libnvgpu-drv_safe.export that will not
export interfaces for non-safe features. We set the exports file
conditionally based on NV_BUILD_CONFIGURATION_IS_SAFETY.
As the features get removed from the libnvgpu-drv.so, corresponding
interfaces need to be removed from the new interface exports file.
JIRA NVGPU-3062
Change-Id: I87a5d727c8b4338c1f16d3e97af469effba6645f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119318
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MISRA rule 5.7 forbids from re-using tag or identifier names multiple
times. Multiple definitions of a tag or identifier may create developer
confusion.
Enum nvgpu_nvlink_link_mode and nvgpu_nvlink_sublink_mode definitions
were used in gk20a.h as return types to functions without including
nvlink_link_mode_transitions.h header file. MISRA scanner considered
this as two different definitions for these enums. Including correct
header file resolves this issue.
Jira NVGPU-3303
Change-Id: I1f8e198620ee20d81e663df2faa32337851abb93
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120458
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MISRA rule 13.5 doesn't allow right-hand operand of logical && or ||
operator to have persistent side effects. The reason is right-hand
operand is executed or checked depending on the left-hand operand value.
That means side effects in the right-hand operand may or may not occur,
contrary to programmer's expectation. Hence, this rule is implemented to
avoid unexpected behavior.
This patch divides if condition with logical && operator to nested if
conditions to resolve this violation.
Jira NVGPU-3277
Change-Id: I9f4387d71427821278db6bbda2eb53bd4d8ea543
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119684
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.
Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.
Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.
Bug 2515097
Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
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Fix 8.2 violation for not specifying parameter name in prototype of
secure_alloc().
Fix 21.3 & 21.8 violations for using reserved names "free" and "exit."
Fix 8.6 and 21.2 violations for __gk20a_do_idle() and
__gk20a_do_unidle() by renaming the functions and wrapping them in a
missing #ifdef CONFIG_PM.
Fix 5.7 violation for reusing "class" as parameter name when already
defined as a struct.
JIRA NVGPU-3343
Change-Id: I976e95a32868fa0a657f4baf0845a32bd7aceb9e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117913
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Below MISRA 17.7 violations are reported in nvgpu.hal.mm.mm,
for nvgpu_timeout_init functions:
misra_c_2012_rule_17_7: The return value of a non-void function
"nvgpu_timeout_init" is unused.
Fix this by asserting that nvgpu_timeout_init is successful, since
it should never fail with NVGPU_TIMER_RETRY_TIMER flag.
Jira NVGPU-3283
Change-Id: I89a6afa5d024683a50dfa5dc277da7fe4a6478bb
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119606
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Check return value of below function and add void to ignore
the return value
update_gp_get
Rename
nvgpu_get_gp_free_count -> nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_gp_free_count -> nvgpu_channel_get_gpfifo_free_count
JIRA NVGPU-3388
Change-Id: I6e2265882c1f34e3bb47eaeac7a2c5a9fbe9b4eb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115784
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Fix several 17.7 violations where the return values were ignored.
Fix 8.6 violation by removing unused declaration of
gp106_init_xve_ops().
Fix a 21.2 violation by renaming function __do_xve_set_speed_gp106().
JIRA NVGPU-3308
Change-Id: I480950aa42478329df33fd8c9c8c63a10dc11434
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116841
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule 17.2 prohibits indirect recursion. nvgpu_allocator_initi()
was calling nvgpu_page_allocator_init(), which in turn was calling back
to nvgpu_allocator_init() to init a buddy allocator. Rather than
calling back to nvgpu_allocator_init(), have nvgpu_page_allocator_init()
call nvgpu_buddy_allocator_init() directly.
JIRA NVGPU-3332
Change-Id: I1102450ae26dda355d5f5dcc3ddb195871c26c32
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114028
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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This fixes MISRA rule 4.7 violations in the function nvgpu_vm_map(). The
violations were caused by trying to use ERR_PTR() to return error
information. Rather than try to return errors in a pointer, just change
the API to return an int and pass the pointer the arguments.
JIRA NVGPU-3332
Change-Id: I2852a6de808d9203b8c7826e2b8211bab97ccd16
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114027
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Fix Rule 4.7 violation for failing to check return value.
Fix Rule 14.2 violation when using the nvgpu_list_for_each_entry_safe
macro by refactoring to use a while loop.
Fix Rule 13.5 violation for using a nvgpu_timeout_expired_msg() in a
logical expression because it can have side effects. This was fixed by
refactoring the while loop.
JIRA NVGPU-3332
Change-Id: I1454db82f766a06d3ffd549de43aad6e1b632928
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114026
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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MISRA mandates switch clauses to end with an unconditional break
statement. Refactor switch/case in gv100_mm_get_flush_retries
function to set retries in each clause, then return result
at the end of the function.
Refactoring of the switch/case solves MISRA 16.1, 16.3 and 16.6
violations.
Jira NVGPU-3314
Change-Id: Ie051a8f2df805b63a7bef6a55fea3ae011603a0e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118887
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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