Add nvgpu macro for pthread API pthread_cleanup_pop(0). The argument
zero would mean that the thread cancellation cleanup handler which is
pushed onto the thread's stack using pthread_cleanup_push() will not
get executed.
JIRA NVGPU-5110
Change-Id: I89a45ccccd8709685f487513bf99d622a82ed891
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307977
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Added dependency between the Kconfig options as follows where
'->' indicates 'depends on' relation:
SUPPORT_CDE -> COMPRESSION -> DMABUF_HAS_DRVDATA
DGPU -> GK20A_PCI
Defined Kconfig option for VPR and for DGPU that is dependent GK20A_PCI
as well. DGPU related sources are now compiled under config flag DGPU.
Also update conditional compilation of the driver paths w.r.t DGPU,
VPR and COMPRESSION flags.
Bug 2834141
Change-Id: Ia0a39d6d4cf8b36e7f955b7355a5ab41783f821c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299627
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MISRA Advisory Rule 10.5 states that the value of an expression should
not be cast to an inappropriate essential type.
This change eliminates such a violation in the posix implementation
of nvgpu_thread_cleanup_pop().
Jira NVGPU-3178
Change-Id: I2ad363b4d60c321fa20b23c167d783bebaceb7d3
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298986
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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In the upstream kernel ACCESS_ONCE is now deprecated with reason as
given in the following related commit:
commit 381f20fceba8e ("security: use READ_ONCE instead of deprecated
ACCESS_ONCE")
ACCESS_ONCE() does not work reliably on non-scalar types. For
example gcc 4.6 and 4.7 might remove the volatile tag for such
accesses during the SRA (scalar replacement of aggregates) step.
Replace usages of ACCESS_ONCE with READ_ONCE and WRITE_ONCE in nvgpu.
Bug 2834141
Change-Id: I9904c49e1a4d7b17ed2fe54360051d08595a2982
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294096
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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Implmented functions to load and execute PUB which
is the safety POR.
PUB has following functionality:
1) Lower PLM
2) Reset PMU
3) FBPA register access to devtools
Secure Boot and Runtime (SBR) microcode comprises of
single PLM Update Binary (PUB) which will execute on
SEC2 Engine Falcon. NVGPU shall load and execute PUB
and wait for falcon halt. On successful halt NVGPU
shall proceed with ns ucode loading on respective
falcons.
NVGPU-4549
Change-Id: I8ea897a026bbe2b1714823aba51bfa51864dd68a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292330
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Current clk unit has multiple header files under include folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within clk unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_clk_inf.h from include which only
clk can access.
All public items are moved into include/clk.h which other units can
access and removed the clk_xxx.h files
NVGPU-4689
Change-Id: I469270ae539e09a3f6fe6187207791732407863e
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298220
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This is fixing the following misra violation
MISRA 5.1 :
Declaration with identical names.
The first 31 characters of identifiers
"nvgpu_nvhost_syncpt_unit_interface_get_aperture" and
"nvgpu_nvhost_syncpt_unit_interface_get_byte_offset" are identical.
JIRA NVGPU-4811
Change-Id: Ib862c4acd53cf748b47c1edffa91b5f033c08953
Signed-off-by: Dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298136
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Currently, we are performing obj ctx alloction for bellow classes
1. VOLTA_COMPUTE_A
2. VOLTA_DMA_COPY_A
3. VOLTA_CHANNEL_GPFIFO_A
In safety, we use Async CE but not GRCE.
So allocating obj context only for COMPUTE_A and return success(0) for
all other valid classes, after setting class in the channel struct.
Jira NVGPU-4378
Change-Id: Ie99872e062cc66f9ddf699397a13df85c3d8d59e
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287486
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Current clk unit has multiple header files under pmuif folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within clk unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_clk_inf.h from pmuif which only
clk can access.
All public items are moved into include/clk.h which other units can
access
This will help in documentation of items for public items.
NVGPU-4491
Change-Id: Iccb0571e05ecb3cb13363390bed8c7214409b543
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292318
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Currently, size of zbc index table is defined as a macro. This macro is
independent of the number of address bits in the ltc zbc index register.
Adding below hal will update zbc index table size as per number of
address bits.
Add hal to get gr_zbc_index_table_size:
u32 (*zbc_table_size)(struct gk20a *g);
ZBC index table address 0 is reserved. Logic to start zbc table index
from 1 is moved to corresponding hals.
JIRA NVGPU-4838
Change-Id: I700cadfdd1f3dc5f323055b8f44d769d6627920a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2288479
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Allocated the following two waiter objects for sync point waith path:
Job tracking and CE threads.
2. QNX channel specific job tracking thread.
The above implementation is only available for QNX.
For Linux, waiter index is skipped.
JIRA NVGPU-3009
Change-Id: If12ad1dc90a24a7b922b205829ca335805c02c3d
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292080
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Current volt unit has multiple header files under pmuif folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within volt unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_volt_inf.h from pmuif which only
volt can access.
All public items are moved into include/volt.h which other units can
access
This will help in documentation of items for public items.
NVGPU-4492
Change-Id: Id40bf4922408a55f1e67d071be726839ac57718f
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289114
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From gv11b onwards, FECS ucode returns an ACK for set watchdog
timeout method. Failure to wait for this ACK was leading to races,
and in some cases, the ACK could be mistaken for the reply to the
next method.
In particular, this happened for the discover golden image size
method which is sent after set watchdog timeout.
With instrumented FECS ucode, it takes longer for the code to
process the set watchdog timeout method, and the write to ack
that method could happen after nvgpu driver clears the mailbox to
send the discover image size method.
With an invalid golden context image size, FECS ended up causing
an MMU fault while attempting to save past allocated buffer.
Added NVGPU_GR_FALCON_METHOD_SET_WATCHDOG_TIMEOUT to be used with
gops_gr_falcon.ctrl_ctxsw, and implemented 2 variants:
- gm20b_gr_falcon_ctrl_ctxsw, without ACK
- gv11b_gr_falcon_ctrl_ctxsw, with ACK
Added NVGPU_GR_FALCON_SUBMIT_METHOD_F_LOCKED flag to allow
executing above method without re-acquiring FECS lock. Longer term,
the 'flags' could be added to gop_gr_falcon.ctrl_ctxsw parameters.
Use gops_gr_falcon.ctrl_ctxsw instead of register writes to invoke
set watchdog timeout method in gm20b_gr_falcon_wait_ctxsw_ready.
Also replaced calls to gm20b_gr_falcon_ctrl_ctxsw to
gops_gr.falcon.ctrl_ctxsw when appropriate, since there are
multiple variants (gm20b, gp10b and gv11b).
Last, fixed clearing of mailbox 0 in gm20b_gr_falcon_bind_instblk.
Bug 200586923
Change-Id: I653b9a216555eec8cd4bb01d6f202bc77b75a939
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287340
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