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2039 Commits

Author SHA1 Message Date
Divya Singhatwaria
3e5fda3730 gpu: nvgpu: Fix MISRA 17.7 violations for PMU-FW unit 
- Rule 17.7 states that the value returned by a
  function having non-void return type shall be used.
- Fix this violation by proper error handling.

JIRA NVGPU-3419

Change-Id: Ia66906747cc2a95ea7f1ce5da16e4251ff521e53
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121936
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-26 22:36:45 -07:00
Deepak Nibade
f4a040cc9d gpu: nvgpu: add safety flag for cyclestats support 
Add new flag NVGPU_CYCLESTATS_SUPPORT to compile cyclestats support
in safety builds

This flag is now enabled until whole debugger support is disabled

Jira NVGPU-3504

Change-Id: I5bf8e0d8eb6e58bebe04eff691a756517017c6d8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123621
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-24 11:16:23 -07:00
Thomas Fleury
dbbb7d2965 gpu: nvgpu: remove nvgpu_tsg_update_sm_error_state_locked 
Remove nvgpu_tsg_update_sm_error_state_locked which is not
used anymore.

Jira NVGPU-3476

Change-Id: I4188f6ff71c02045f1628d4be1599c891c2219b5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124411
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2019-05-23 17:45:58 -07:00
Seema Khowala
4cf2d2166c gpu: nvgpu: Add NVGPU_VPR compiler flag 
This flag is added to compile out vpr support for
safety build.

JIRA NVGPU-3518

Change-Id: I6646a39ff6f1b7fd0948aacc3ede4a7a48bec734
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123900
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2019-05-23 17:45:40 -07:00
Sagar Kamble
08add88e1d gpu: nvgpu: remove dgpu hal and sw from the safety build 
Since dGPU support is not required for initial safety release, compile
out dGPU sw and hal implementations except below files that are used
by gv11b currently: acr_sw_gv100.c, engine_status_gv100.c, gr_gv100.c
gr_config_gv100.c and hwpm_map_gv100.c.

JIRA NVGPU-3062

Change-Id: I8a6bc8b235e7e5eac5b0e76147b8bd12f9abbd2d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119586
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2019-05-23 10:07:31 -07:00
Sagar Kamble
17607e6bc9 gpu: nvgpu: remove sec2 from the safety build 
Since dGPU support is not required for initial safety release, disable
features from dGPU. Remove sec2 to start.

JIRA NVGPU-3062

Change-Id: I4448ab0fde603bc749dfdec5646308490971e18f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119585
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2019-05-23 10:07:22 -07:00
Mahantesh Kumbar
a081fba30c gpu: nvgpu: move gv100 ACR functions to gv11b 
moved some gv100 ACR functions to gv11b as gv11b will be used for
safety build & gv11b dependency on gv100 will removed with this
changes to compile out gv100 ACR files from safety build.

LS-PMU ACR related functions put under NVGPU_LS_PMU check
to compile out those functions for safety-build

JIRA NVGPU-3418

Change-Id: I1af29c649e8ef7f46e369f00245efe93a55d1658
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123739
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 2019-05-23 07:35:06 -07:00
Debarshi Dutta
47dc0b9ebd gpu: nvgpu: move chip specific channel HAL files to hal/fifo/ 
Moved the channel HAL files from common/fifo/ to hal/fifo

Jira NVGPU-3248

Change-Id: Ibb85b7c0e71422dbd774a518e4f0bba0b97ef807
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123399
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2019-05-23 02:19:47 -07:00
Debarshi Dutta
0eb0242bdd gpu: nvgpu: rename public channel unit APIs 
Rename the public channel unit APIs to follow the convention of
nvgpu_channel_*.

gk20a_channel_deterministic_idle -> nvgpu_channel_deterministic_idle
gk20a_channel_deterministic_unidle -> nvgpu_channel_deterministic_unidle
gk20a_wait_until_counter_is_N -> nvgpu_channel_wait_until_counter_is_N
nvgpu_gk20a_alloc_job -> nvgpu_channel_alloc_job

Jira NVGPU-3248

Change-Id: I358d63d4e891f6d92c70efe887c07674bc0f9914
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123398
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-23 02:19:38 -07:00
Mahantesh Kumbar
3d1169544f gpu: nvgpu: alloc space for PMU's struct nvgpu_pmu at runtime 
Allocating space for struct nvgpu_pmu at run time as part of
nvgpu_pmu_early_init() stage and made required changes to
dependent fiels as needed.

JIRA NVGPU-1972

Change-Id: I2d1c86d713e533c256ba95b730aa2e9543a66438
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110109
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-23 00:56:55 -07:00
Mahantesh Kumbar
0a64f6cb2d gpu: nvgpu: PMU pmu.c/h header include cleanup 
Some headers are not required to include in pmu.c/h as
lot of PMU code restructure happened, so removed headers
which not required anymore.

JIRA NVGPU-1972

Change-Id: Iead7f049d167cdaaaf7c75c2a5e19ae7b068fe6b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110108
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-23 00:56:45 -07:00
Vedashree Vidwans
c3f7d9a3b0 gpu: nvgpu: fix MISRA 17.7 in common.sec2.allocator 
MISRA Rule 17.7 doesn't allow return value of a function to be ignored.
This patch checks return value of nvgpu_allocator_init function and
returns error to the sec2_process_init_msg() function.

Jira NVGPU-3321

Change-Id: Ie3eb1b5f9312e178f8f3e6de310d768c3ac3e220
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123221
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-22 16:44:59 -07:00
Philip Elcan
4071b35235 gpu: nvgpu: bios: use memcpy to fix MISRA 11.3 bugs 
MISRA Rule 11.3 prohibits casting between different pointer types. The
previous "fix" in nvgpu_bios_parse_rom() was to use an intermediate cast
to uintptr_t. However, that leaves the possibility of creating a
mis-aligned pointer.  So, instead of casts, use nvgpu_memcpy() to make a
copy of the data in a local structure.

JIRA NVGPU-3317

Change-Id: I3f9dd0d6c10a7425f300b51410be2e248177b505
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122390
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-22 13:36:07 -07:00
Vaibhav Kachore
854e861ad0 gpu: nvgpu: fix CERT-C violations 
This patch fixes following CERT-C violations for power management unit:
- CERT INT31-C

NVGPU-3403

Change-Id: I4eb2374cc720c6d0bb81d6a4d9750348d4e5a670
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117659
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-22 03:16:56 -07:00
Divya Singhatwaria
7a18c10dbe gpu: nvgpu: Fix MISRA 16.6 violations in PMU-FW unit 
- Rule 16. states that all switch statements must
  shall have atleast two switch-clauses.
- Some "default" cases were missing the "break"
  statement so fix this violation in switch
  statements.

JIRA NVGPU-3419

Change-Id: I2072c3aacf437766693cb30a07b8f6678c76d48e
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121890
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 21:47:54 -07:00
Seshendra Gadagottu
c7cc1d1e2d gpu: nvgpu: fix CERT INT30-C in common.gr.falcon 
Fixed CERT INT30-C violations in common gr falcon driver
by using nvgpu_safe_add_u64 and nvgpu_safe_add_u32
for u32 arithmetic operations.

JIRA NVGPU-3413

Change-Id: I574af10aa3352b8f855632c886adac3fce3141c3
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122510
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 16:26:07 -07:00
Vinod G
cd02e4d70f gpu: nvgpu: Fix CERT INT30-C errors in gr intr unit 
Fix CERT INT30-C error in gr interrupt units

cert_violation: Unsigned integer operation may wrap.

Use nvgpu_safe_ops macros for addition and subtraction.

Jira NVGPU-3412

Change-Id: Id2d936e77959005616faf069aff6701789342456
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122474
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 15:15:59 -07:00
Vinod G
1f85c3190b gpu: nvgpu: Fix CERT INT31-C errors in hal.gr.init 
Fix CERT INT31-C errors in hal.gr.init unit.
cert-violation: Casting "array_size" from "unsigned long" to "int"
without checking its value may result in lost or misinterpreted data.

Use nvgpu_safe_cast_u64_to_u32 macro to covert size_t to u32

Jira NVGPU-3411

Change-Id: Ib160e43af683d5ca6a1cc86c4b9ee3322ddc971d
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119847
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 15:15:41 -07:00
Vedashree Vidwans
d8c934a000 gpu: nvgpu: fix MISRA common.mm.allocator.page 
MISRA rule 5.7 doesn't allow reuse of tag or variable names as this
would lead to developer confusion. Patch renames page_alloc_slab_page
struct pointer's local variable name to page_ptr to resolve the
violation. Also, renames function "nvgpu_page_alloc" to
"nvgpu_page_balloc" to remove identifier name overloading.

MISRA rule 10.x forbids from casting value of composite expression to an
object with different essential type category. This patch replaces
multiplication operation to left shift operation.

MISRA rule 15.7 requires every if .. else if construct to be terminated
with an else statement. This patch updates if .. else if condition to
resolve the violation.

MISRA Rule 17.2 doesn't allow recursive call from a function to itself,
as this might lead to stack overflow. Updated nvgpu_page_allocator_init
to call nvgpu_buddy_allocator_init() directly.

MISRA rule 21.6 doesn't allow use of snprintf from standard library.
This patch replaces snprintf call with string functions.

JIRA NVGPU-3338

Change-Id: Ic8cb956edb3c72811752008de192e6e8ba12463e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 15:15:32 -07:00
Deepak Nibade
dfdd05a3d6 gpu: nvgpu: disable fecs trace support for safety builds 
Compile all files with fecs trace support only if flag
NVGPU_FECS_TRACE_SUPPORT is set

remove CONFIG_GK20A_CTXSW_TRACE checks from within the files

add POSIX file for fecs trace support for compilation with
make command

Jira NVGPU-3414

Change-Id: I205e3494ce94138ab6c6fccf7fbcefc41f953c77
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120276
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 10:36:04 -07:00
Debarshi Dutta
f39a5c4ead gpu: nvgpu: rename gk20a_channel_* APIs 
Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.

Jira NVGPU-3248

Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 09:26:16 -07:00
Nitin Kumbhar
1bf55ec715 gpu: nvgpu: rename secure ops to safe ops 
Change secure_ops.h to safe_ops.h and rename unsigned
type operations from nvgpu_secure_* to nvgpu_safe_*.

NVGPU-3432

Change-Id: I395896405ee2e4269ced88f251b097c5043cdeef
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122571
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 04:37:57 -07:00
Divya Singhatwaria
a46eca3483 gpu: nvgpu: Fix PG unit members direct access in other units 
Other units directly access PG unit members like:
pmu->pg->pg_buf

This direct access is fixed by introducing public
interface to handle this correctly

JIRA NVGPU-3405

Change-Id: I13f5922bb04ece680f4b487ffc8f1d11e4efd234
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118281
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-20 22:46:18 -07:00
Deepak Nibade
646b08a032 gpu: nvgpu: add flag for fecs trace support in rest of the units 
Add CONFIG_GK20A_CTXSW_TRACE flag for fecs trace support in rest of
the units like common.gr.utils and common.hal.gr.ctxsw_prog

Jira NVGPU-3414

Change-Id: I8f56bc38defd49a5fc30f79a35047afa7db2ffdf
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120277
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-20 15:46:30 -07:00
Vinod G
4d3df9deae gpu: nvgpu: Fix CERT INT30-C error in commom.gr 
Fix CERT INT30-C error in common.gr unit

Error- Unsigned integer operation "gpc_stride * gpc" may wrap.
Error- Unsigned integer operation "tpc_stride * tpc" may wrap.
Use nvgpu_secure_mult_u32 function to do wrap checking.

Error- Signed integer operation ctxsw_disable_count++ may overflow
Add checking and return error.
_
Jira NVGPU-3411

Change-Id: I6e52283ee1a1e883e0195bde79fc69d58f71d5c9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118147
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-20 15:45:52 -07:00
Nitin Kumbhar
709896c48d gpu: nvgpu: fs_state: fix CERT-C INT violations 
Error: CERT INT30-C:
drivers/gpu/nvgpu/common/gr/fs_state.c:61:
cert_violation: Unsigned integer operation "num_tpc_per_gpc * gpc"
 may wrap.

Error: CERT INT30-C:
drivers/gpu/nvgpu/common/gr/fs_state.c:70:
cert_violation: Unsigned integer operation "(1U << (u32)max_tpc_count) - 1U"
 may wrap.

JIRA NVGPU-3410

Change-Id: If6c12bd6883a8d55d38d128fdef9fab65a600751
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119396
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-20 04:36:59 -07:00
Nitin Kumbhar
bf03ffbb05 gpu: nvgpu: obj_ctx: fix CERT-C INT violations 
Error: CERT INT31-C:
drivers/gpu/nvgpu/common/gr/obj_ctx.c:310:
cert_violation: Casting "size" from "unsigned long" to "unsigned int"
 without checking its value may result in lost or misinterpreted data.

Error: CERT INT30-C:
drivers/gpu/nvgpu/common/gr/obj_ctx.c:594:
cert_violation: Unsigned integer operation
 "(*g->ops.gr.init.get_patch_slots)(g, config) * 2U" may wrap.

JIRA NVGPU-3410

Change-Id: Icae8246903693d7f5ad66635d3e81d22f6ff2df5
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118522
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-20 04:36:49 -07:00
Nitin Kumbhar
7c5316c142 gpu: nvgpu: ctx: fix CERT-C INT violations 
Error: CERT INT30-C:
drivers/gpu/nvgpu/common/gr/ctx.c:644:
cert_violation: Unsigned integer operation
 "gr_ctx->patch_ctx.mem.size / 4UL - 2UL" may wrap.

Error: CERT INT31-C:
drivers/gpu/nvgpu/common/gr/ctx.c:580:
cert_violation: Casting "gr_ctx->boosted_ctx" from "bool" to "unsigned int"
 without checking its value may result in lost or misinterpreted data.

JIRA NVGPU-3409

Change-Id: Ib3c865d43ecd3c0eaaafd47b7b65111aa77689bd
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118521
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-20 04:36:40 -07:00
Thomas Fleury
3881dd6a26 gpu: nvgpu: fix build issue w/ NVGPU_CHANNEL_WDT 
Fix build issue w/ safety build.
Add missing } when NVGPU_CHANNEL_WDT is not set.

Jira NVGPU-3012

Change-Id: I60f017a0203662b9acc8a2fa791079deade93736
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121305
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-18 03:54:52 -07:00
Philip Elcan
aeb8852d54 gpu: nvgpu: fix MISRA 9.1 issues in page_table 
MISRA Rule 9.1 requires objects to be initialized before being read.
Update nvgpu_set_pte() to initialize values before they are passed to
nvgpu_locate_pte().

JIRA NVGPU-3340

Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Change-Id: I3d6b3d3eb3d8cb657c46c80c8d03ecf1c0b4f12c
Reviewed-on: https://git-master.nvidia.com/r/2120491
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-17 16:16:54 -07:00
Philip Elcan
f8f9dfeea8 gpu: nvgpu: mm: fix MISRA 13.5 violations in page_table 
Fix MISRA rule 13.5 violation for using a function that has side effects
as the right hand side of a logical expression. In this case,
is_iommuable() can have side effects in some OS implementations.

JIRA NVGPU-3340

Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Change-Id: If465f68fce0e9d6d8ef98564229eebd112b28f29
Reviewed-on: https://git-master.nvidia.com/r/2120490
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-17 16:16:45 -07:00
Philip Elcan
40d9609eff gpu: nvgpu: mm: fix 4.7 violation in page_table 
MISRA 4.7 requires checking errors returned by functions. This fixes a
case where the error information wasn't being checked before performing
other operations.

JIRA NVGPU-3340

Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Change-Id: I480fde75a07f779450096533ab29c76975aff092
Reviewed-on: https://git-master.nvidia.com/r/2120489
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-17 16:16:36 -07:00
Philip Elcan
dfccdeaace gpu: nvgpu: mm: fix MISRA 16.4 in dma.c 
MISRA Rule 16.4 requires a comment or statement in the default lable.
This moves a comment in nvgpu_dma_free(0 before the break to be
compliant.

JIRA NVGPU-3328

Change-Id: Ic4293f486c35eb6396a508508d43d53311fc693c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119647
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-17 15:05:30 -07:00
Vaibhav Kachore
11630ad56f gpu: nvgpu: add support for TEGRA_VGPU_CMD_GET_TPC_EXCEPTION_EN_STATUS 
This patch adds support for TEGRA_VGPU_CMD_GET_TPC_EXCEPTION_EN_STATUS
in vgpu.

Bug 2555113

Change-Id: I9c822e09e1b4ec84ccaa3110b6f500b26eec6490
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118328
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-17 06:36:33 -07:00
Antoine Chauveau
b8ba882399 gpu: nvgpu: Remove assertion which triggers intermittently 
Partially revert patch c0e725a, which causes intermittent test
failures.

Bug 2599340

Change-Id: I4ac7ef007b4a7beaa2010cc3795ed0f78b4ce9c7
Signed-off-by: Antoine Chauveau <achauveau@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120867
 2019-05-17 04:52:47 -07:00
Debarshi Dutta
4c30bd599f gpu: nvgpu: rename tsg_gk20a*/gk20a_tsg* functions. 
rename the functions with the prefixes tsg_gk20a*/gk20a_tsg*
to nvgpu_tsg_*

Jira NVGPU-3248

Change-Id: I9f5f601040d994cd7798fe76813cc86c8df126dc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120165
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-17 01:49:27 -07:00
Debarshi Dutta
1dea88c6c7 gpu: nvgpu: Add NVGPU_CHANNEL_WDT flag 
NVGPU_CHANNEL_WDT feature is embedded within the NVGPU_CHANNEL_WDT flag
to allow it to be compiled out for safety builds.

Jira NVGPU-3012

Change-Id: I0ca54af9d7b1b8e01f4090442341eaaadca8e339
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114480
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 23:28:13 -07:00
Seshendra Gadagottu
b2980b0c22 gpu: nvgpu: fix MISRA 10.3 issues in hal.ltc 
Change following ltc hal prototype from:
int (*determine_L2_size_bytes)(struct gk20a *gk20a);
to
u64 (*determine_L2_size_bytes)(struct gk20a *gk20a);

JIRA NVGPU-3422

Change-Id: I53cbd7f37cad3c6851e3c5b46af6cdc04013d690
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119996
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 16:26:22 -07:00
Seema Khowala
6f5cd4027c gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below functions
gk20a_enable_channel_tsg
gk20a_disable_channel_tsg

Rename
gk20a_disable_channel_tsg -> nvgpu_channel_disable_tsg
gk20a_enable_channel_tsg -> nvgpu_channel_enable_tsg

JIRA NVGPU-3388

Change-Id: I0c18c4a14a872cecb12ae3089da886be9da43914
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115211
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 16:25:22 -07:00
Thomas Fleury
af2ccb811d gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl 
Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.

Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.

Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.

Bug 2515097

Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 15:15:18 -07:00
Philip Elcan
5c09935297 gpu: nvgpu: common: fix MISRA violations 
Fix 8.2 violation for not specifying parameter name in prototype of
secure_alloc().

Fix 21.3 & 21.8 violations for using reserved names "free" and "exit."

Fix 8.6 and 21.2 violations for __gk20a_do_idle() and
__gk20a_do_unidle() by renaming the functions and wrapping them in a
missing #ifdef CONFIG_PM.

Fix 5.7 violation for reusing "class" as parameter name when already
defined as a struct.

JIRA NVGPU-3343

Change-Id: I976e95a32868fa0a657f4baf0845a32bd7aceb9e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117913
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 11:57:56 -07:00
Philip Elcan
78c7e601f8 gpu: nvgpu: debug: fix MISRA 5.7 violation 
MISRA 5.7 requires tag names be unique. Rename the struct
gk20a_debug_output to nvgpu_debug_context to avoid name collision with
the function of the same name.

JIRA NVGPU-3346

Change-Id: I9566b9dc6a7d090e87d9a09f6b8faf688589fbbd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116877
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 11:57:32 -07:00
Philip Elcan
10006b723a gpu: nvgpu: mm: fix MISRA 21.6 violations in vm.c 
MISRA 21.6 prohibits use of snprintf(). Replace uses with strcpy/strcat.

JIRA NVGPU-3332

Change-Id: I795b673d0a855c0fcb28fac76b31ef1b1f39543e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119633
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 09:46:01 -07:00
Seeta Rama Raju
671cc9d785 gpu: nvgpu: MISRA 10.x fix 
-- This will MISRA 10.x violations in semaphore_pool.c,
   nvgpu_mem.h, nvgpu_mem.c and posix-nvgpu_mem.c.

JIRA NVGPU-3177

Change-Id: I1db234a47c7097da28fdfd3236d9b7c5fe385d79
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119524
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 04:29:50 -07:00
Philip Elcan
5a0a711464 gpu: nvgpu: fix MISRA 21.2 violation in io.h 
MISRA Rule 21.2 prohibits naming functions beginning with double
underscore. So, rename __nvgpu_readl() to nvgpu_readl_impl().

JIRA NVGPU-3361

Change-Id: Ia09a0f57e250fa3934f843671a529ee1b2ac2493
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118041
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 22:29:21 -07:00
Seema Khowala
fb603ef467 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below function and add nvgpu_assert
nvgpu_channel_deferred_reset_engines

JIRA NVGPU-3388

Change-Id: I745de9fb618803824ae62ed586944ce5d838c92a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115787
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:47:24 -07:00
Seema Khowala
334f855ac4 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below function and add void to ignore
the return value
update_gp_get

Rename
nvgpu_get_gp_free_count -> nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_gp_free_count -> nvgpu_channel_get_gpfifo_free_count

JIRA NVGPU-3388

Change-Id: I6e2265882c1f34e3bb47eaeac7a2c5a9fbe9b4eb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115784
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:47:14 -07:00
Seema Khowala
766dfb2cb1 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below function and add nvgpu_assert.
nvgpu_assert is warning on linux but a system halt on safety
builds.
nvgpu_runlist_reload_ids

JIRA NVGPU-3388

Change-Id: Ie2bf6c48d4f9e673695dc6587df24651e9d8c78c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115767
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:47:05 -07:00
Seema Khowala
c0e725a576 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below function and add nvgpu_assert.
nvgpu_assert is warning on linux but a system halt on safety
builds.
nvgpu_preempt_channel

JIRA NVGPU-3388

Change-Id: Id60d10c0d1593a6b798a037b9ec0efe6c4d20dd5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115762
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:46:56 -07:00
Seema Khowala
7ebb9d85d9 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below functions and print error messages
g->ops.tsg.force_reset
nvgpu_channel_wdt_stop

JIRA NVGPU-3388

Change-Id: Ia02b0fe040d2181a2b2dc24ec56e443f59505e99
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:46:46 -07:00