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Thomas Fleury
0fa55ffac9 gpu: nvgpu: units: pramin build issues for dGPU 
Fix pramin related build issues in unit tests, when enabling dGPU
in safety build.

pram_data032_r is now defined as a macro which cannot be used to
initialize g->ops.pramin.data032_r in unit tests.

Instead, use nvgpu_pramin_ops_init, and check that
g->ops.pramin.data032_r is non NULL.

Jira NVGPU-4661

Change-Id: I33522fc42bfe5f8c23b579126a21680fd5880fd8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2314206
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
0c23bf57ea gpu: nvgpu: build flag for secure boot 
Use CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT build flag for
gm20b_gr_falcon_fecs_host_int_enable.

Jira NVGPU-4661

Change-Id: Id7d991b81206d00e38049556b42b4e9a4abd1708
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313620
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
d980bd2781 gpu: nvgpu: build flag for fb mmu debug mode 
Use CONFIG_NVGPU_DEBUGGER for the following function:
- gv100_fb_set_mmu_debug_mode

Jira NVGPU-4661

Change-Id: Ia074fcab6695ba20b3cf1ef86f08d1b1735fcefe
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313590
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
8ec4395e82 gpu: nvgpu: build flag for deterministic channel 
Add CONFIG_NVGPU_DETERMINISTIC_CHANNELS and fix
preprocessor #ifdefs to allow compiling kernel mode
submit without deterministic feature enabled.

Jira NVGPU-4661

Change-Id: I4aa678715824e8981d39bd8db0c5ae61ef3a675c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310325
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
cc043e1506 gpu: nvgpu: cond. compilation of tegra dvfs code 
Protect the code dependent on tegra dvfs and bpmp dvfs code under the
config flags CONFIG_TEGRA_DVFS and CONFIG_NV_TEGRA_BPMP.

Also, update clk_config_dvfs and clk_program_na_gpc_pll to handle the
error value returned from g->ops.clk.predict_mv_at_hz_cur_tfloor.

Bug 2834141

Change-Id: I124d29f22e59fd6af7801ca859c4470483c8f7d8
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306433
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
bf353cea6c gpu: nvgpu: sim_pci: reconcile sim escape paths between RM and nvgpu 
SIM models are getting updated to have same escape read path
for RM and nvgpu. Updated nvgpu driver code to have same escape
read mechanism as RM for dgpu.

Required for dgpu to work on NET23.

Bug 2539889
Bug 200582707

Change-Id: Ied05dae00928d44249df695429fb5029331f1286
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2256665
Reviewed-by: Lakshmanan M <lm@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Abdul Salam
53bd199e30 gpu: nvgpu: Seperate clk monitor from clk unit 
Clock monitor is for monitoring clk status.
This is separated from clk unit which manages the clk.

NVGPU-4491

Change-Id: If83434db7970f1b024f545672a6f1e92ee66dbbc
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313201
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 2020-12-15 14:13:28 -06:00
Seeta Rama Raju
5ce7d5acff gpu: nvgpu: Add fault injection variable for clock UT 
Bug 2861451

Change-Id: Ie51c1524c47934e44cde06515f5daccd8e1e7dd9
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
(cherry picked from commit d57a51ba6db7b6c2df28d1770727506214b85e08)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310971
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
7aa9e90bfc gpu: nvgpu: update gops.cg 
Update gops.cg to include following runlist level cg ops:
- blcg_runlist_load_gating_prod
- slcg_runlist_load_gating_prod

Jira NVGPU-5048

Change-Id: Ia2a3f887d5c2fd6f1dd35d606afd19d117468c2c
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300448
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
490e1ee06c gpu: nvgpu: conditional compile of tegra powergate 
Include tegra bpmp and powergate headers under the config flag
CONFIG_NV_TEGRA_BPMP.
tegra186-powergate.h included by tegra powergate header defines
TEGRA186_POWER_DOMAIN_GPU that can be used to conditionally
compile the railgate code similar to t194.

Bug 2834141

Change-Id: Ib52923ec02438f0f10ea78d6a8874f387e17ee2c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306435
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
59c6947fc6 gpu: nvgpu: add CONFIG_NVGPU_TEGRA_FUSE 
Encapsulate the tegra fuse functionality under the config flag
CONFIG_NVGPU_TEGRA_FUSE.

Bug 2834141

Change-Id: I54c9e82360e8a24008ea14eb55af80f81d325cdc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306432
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
3748be5792 gpu: nvgpu: move timer functions from soc files 
Move following timer functions from soc header and c file to timer
header and c file:
1. nvgpu_delay_usecs
2. nvgpu_us_counter
3. nvgpu_get_cycles

Bug 2834141

Change-Id: I04cf7229a0d35c90a320bbe64e80912b08cccefb
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306431
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
92db0b3048 gpu: nvgpu: conditional compilation of dgpu code 
There were few more dgpu related references unprotected by the config
flag. Fix those.

Bug 2834141

Change-Id: Ia9fd58d97552efeff84d6c0c52b8d5de481fab31
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306430
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
00eec69b3f gpu: nvgpu: add hal to get_ctx_buffer_offsets 
Currently, gr_gk20a_get_ctx_buffer_offsets is defined as a function.
However, this function is used in the common code. So, add new GR hal
to get_ctx_buffer_offsets.

Jira NVGPU-5047

Change-Id: I0cec6ff19194fa726722e6af3a2f11a188dc9087
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310352
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
a182be7b8d gpu: nvgpu: add ctxsw_reg bundles for nvgpu-next 
Add ctxsw_reg bundle programming for nvgpu-next.

Jira NVGPU-5047

Change-Id: I3df9d89a6615825d224ec5d46b550cd68623e7d7
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2309817
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
75f79cea47 gpu: nvgpu: unit: modify mmu-fault-gv11b-fusa UT 
Modify mmu-fault-gv11b-fusa tests to reset environment at end of each
test. Also, re-write test asserts for
test_gv11b_mm_mmu_fault_disable_hw().

Jira NVGPU-4987

Change-Id: If1866d39444717f5d5f3e0d30e29263a083ab56d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310544
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
f38a5a4f09 gpu: nvgpu: build flag for compression_page_size 
Use CONFIG_NVGPU_COMPRESSION flag instead of CONFIG_NVGPU_DGPU
for g->ops.fb.compression_page_size.
This is to allow compiling dGPU without compression in safety build.

Jira NVGPU-4661

Change-Id: Ida53bb79ee10ff875a70bcad00cde6f6ada3c8fe
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310232
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 2020-12-15 14:13:28 -06:00
Seema Khowala
007ecfb5bc gpu: nvgpu: support upto four stall interrupt lines 
Add two new variables in nvgpu_mc struct to support
upto four stall interrupt lines.

Variables:-

Total number of stall interrupt lines:
u32 irq_stall_count

Array to store irq_stall interrupt number for upto 4
stall irq lines:
u32 irq_stall_lines[4]

JIRA NVGPU-4864

Change-Id: I9b43fc20c78dbcaf97fe8e685bb77963f06d3f99
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310377
Tested-by: Lakshmanan M <lm@nvidia.com>
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 2020-12-15 14:13:28 -06:00
vinodg
4aff9bcd4e gpu: nvgpu: fix for load imbalance across cta subpartitions 
CTA_SUBPARTITION_SKEW load balancing is broken across
subpartitions. SW WAR to disable the CTA_SUBPARTITION_SKEW.

Jira NVGPU-5132
Bug 200593339

Signed-off-by: vinodg <vinodg@nvidia.com>
Change-Id: I3faae882a94fc6262cc287df44994cc04b4fd5d6
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308905
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
3d5162f01c gpu: nvgpu: enable fe auto go idle for nvgpu-next 
Enable fe auto go idle feature for nvgpu-next.

JIRA NVGPU-5135

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I5afecea8e039be90424e1bee6e1fd20a2584576b
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2309662
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
ea09ef92b5 gpu: nvgpu: conditional compilation of nvhost code 
There were few more nvhost related references unprotected by the config
flag. Fix those.

Bug 2834141

Change-Id: Id7d94e3e6fa471f02697d121b557884c7287c26e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306437
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 2020-12-15 14:13:28 -06:00
rmylavarapu
147564cbd5 gpu: nvgpu: NVGPU migration to support latest ucode 
Changes:
- Send down BOARDOBJGRP classId to the PMU. Assign each
  BOARDOBJ the classId of its parent group which is set
  to zero in current implementation. Changed in NVGPU to send
  board obj grp classid to PMU.
- Disable IPC VMIN support as pmu-tu10a profile doesn't support.
- Change in clk vf point enumeration types.
- Change in pstate type values.
- Updated ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info
  NVGPU-PMU interface struct with b_ver_expected_is_mask to send
  whether the expected version is single value or should be
  interpreted as a bit mask with bits corresponding to
  expected versions set.

NVBUG-200593676
NVGPU-5066

Change-Id: I17b172d88f8b74fbf78044caf7f64cd8811f9fb7
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308533
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
4b97628278 gpu: nvgpu: conditional compile of ltc_streamid 
ltc_streamid and tegra-swgroup.h header inclusion is applicable to
gp10b. Hence compile it under the flag CONFIG_ARCH_TEGRA_18x_SOC.

Bug 2834141

Change-Id: I79b8f5e0a4cfeff9298eca5f13a7d1c6f291f7ad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307298
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 2020-12-15 14:13:28 -06:00
Seema Khowala
c79522d452 gpu: nvgpu: gr: enhance firmware method error message 
Dump set_falcon method, class and whitelist register
being accessed.

Bug 200594051

Change-Id: Ic7fe014ba917a23b1ca9474bf5bd1d231f7ed60f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308857
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
ad227d9c31 gpu: nvgpu: unit: fix mutex acquire fail for l4t 
In hal.mm.mmu_fault UT, some tests are dependent on each other. Reset
environment variables at the end of test_gv11b_mm_mmu_fault_setup_sw(),
Modify test_gv11b_mm_mmu_fault_setup_hw() to avoid destroying mmu_fault
setup for branch coverage.

Jira NVGPU-4987

Change-Id: I2e6904cb5304285123a29c24d00bd4dcd035e0ff
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306652
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 2020-12-15 14:13:28 -06:00
rmylavarapu
dc32307c13 gpu: nvgpu: Rename therm public struct 
Renamed therm public struct to match with the other
units.

NVGPU-4449

Change-Id: I675ce43b136139420b8cc1eecdc395d9165d9f30
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307090
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
d0850123a8 gpu: nvgpu: remove tegra_edp_notify_gpu_load usage 
Since this is just a nop stub, remove it's usage to reduce the
downstream debt.

Bug 200593710
Bug 2834141

Change-Id: I13e16462d9555bb9ebae01de65c43f59e007785d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307299
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
40d3f7518b gpu: nvgpu: create of_chosen variable 
nvgpu relies on this OF device_node variable to determine joint_xpu_rail
property. Instead of exporting it from the OF driver as nvgpu is not
available in the upstream, define it in the nvgpu itself.

Bug 200593710
Bug 2834141

Change-Id: I80b928b20869b93f5255b757bcc1758245ee2650
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307297
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 2020-12-15 14:13:28 -06:00
Petlozu Pravareshwar
6859c9c5a6 gpu: nvgpu: Add nvgpu macro for a pthread API 
Add nvgpu macro for pthread API pthread_cleanup_pop(0). The argument
zero would mean that the thread cancellation cleanup handler which is
pushed onto the thread's stack using pthread_cleanup_push() will not
get executed.

JIRA NVGPU-5110

Change-Id: I89a45ccccd8709685f487513bf99d622a82ed891
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307977
Reviewed-by: Automatic_Commit_Validation_User
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
fa9db74ba6 gpu: nvgpu: conditional compilation of vpr code 
There were few more vpr related references unprotected by the config
flag. Fix those.

Bug 2834141

Change-Id: Ic934b7aeb303193c21b73921982a5df9c021ea9b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306438
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
7b301c5ace gpu: nvgpu: cond. compile with CONFIG_TEGRA_BWMGR 
Protect tegra bwmgr code under the config flag CONFIG_TEGRA_BWMGR.

Bug 2834141

Change-Id: Icb3c9a363a639e3fd8e91ef12dcb62ba7e498747
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306436
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
9aa669797d gpu: nvgpu: add pbdma gops for nvgpu_next 
Add pbdma gops for nvgpu-next.

Jira NVGPU-4979

Change-Id: If04f5c09cd4a13b0f536a15dbe2b4bd9eb24107a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2302772
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
2e4fb38870 gpu: nvgpu: add eng_config hal for nvgpu_next 
Add gr.eng_config hal for nvgpu_next.

Jira NVGPU-5049

Change-Id: Ieb342cb0416f965a3f80e3a6e3f0f43a853485ff
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300534
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
5fa0d7f994 gpu: nvgpu: add bundle programming for nvgpu_next 
Update bundle programming for nvgpu_next.

JIRA NVGPU-5004

Change-Id: I1c452a9e78cd018de86fb57de10291c4411e7d89
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299128
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
feebc746ca gpu: nvgpu: fix global register access list 
For legacy chips (gm20b, gp10b and gv11b), incorrect register
offset is used for global access register list:

incorrect: 0x418300, /* gr_pri_gpcs_rasterarb_line_class  */
correct:   0x418380, /* gr_pri_gpcs_rasterarb_line_class  */

Fix this issue by updating global access register list by using
correct register offset value.

NVGPU-5108

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Id6722039f8d874dbcb79732dffd727d2ff2a1a72
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306642
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 2020-12-15 14:13:28 -06:00
rmylavarapu
e424e4791a gpu: nvgpu: perf: Refactor Perf unit 
-Renamed and moved nvgpu_pmu_perf struct from public
to unit specific
-Renamed all functions as per public/private format

NVGPU-5029

Change-Id: If3f479bb1443850a5c8a8714cd1c9da346cb566a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300609
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
14f268563a gpu: nvgpu: add gr.zbc hal for nvgpu_next 
Add gr.zbc hal for nvgpu_next

Jira NVGPU-5084

Change-Id: I678dac83ea67818e1b657b22840f3f4a04584ba8
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2304195
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 2020-12-15 14:13:28 -06:00
Seeta Rama Raju
551b3bebe8 gpu: nvgpu: Add 0x if falcon data is 0000000 
- When the falcon data is 00000000, the dump does not add 0x while printing.

Bug 200586923

Change-Id: I9fda75258290a85b0e4c38f426adc4474d88cdd8
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306485
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 2020-12-15 14:13:28 -06:00
Prateek sethi
451797a6d5 gpu: nvgpu: move userspace firmware files to gv11b 
qnx unit test access ucode from /proc/boot/gv11b. QNX Unit test face
issues like permission, platform dependency etc when test tries to
access ucode from /proc/boot. To fix issue updating qnx firmware unit
to read ucode from firmware/gv11b in case of unit test. Patch also
updates firmware access path for posix as well.

Jira NVGPU-3582
Bug 2693908

Change-Id: I1b28c8475b6bc4fe5ec3d6a525cb3af152feb887
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306278
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Deepak Nibade
7a4ecc8966 gpu: nvgpu: make debugger register access ELPG protected 
Some of the APIs that access debugger register are not protected
from ELPG. This might trigger PRI access timeouts for corresponding
registers if GR engine is power gated.

Add nvgpu_pg_elpg_protected_call() to protect against ELPG.

Bug 2820066

Change-Id: I467ea28aaea1c0e36c2d6aabce6a2daea6ee9911
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306383
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 2020-12-15 14:13:28 -06:00
Seema Khowala
31b8ecbcee gpu: nvgpu: gp10b: sim: handle priv ring interrupts 
priv_ring interrupts are enabled for sim. Handle the
interrupt on sim too.

JIRA NVGPU-4864
JIRA NVGPU-5017

Change-Id: I2ff16c0a8ff152839765556dd3b117995f9de109
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306040
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 2020-12-15 14:13:28 -06:00
Philip Elcan
20a4080be0 gpu: nvgpu: quiesce: stop thread gracefully 
Previously, nvgpu_sw_quiesce_remove_support() stopped the quiesce
thread abruptly with nvgpu_thread_stop(), which could mean the thread
was killed while still waiting on the cond. Then when the cond was
destroyed, there may be an error since the underlying implementation may
think there is still a thread waiting (such as the Posix
implementation).

Change nvgpu_sw_quiesce_remove_support() to use
nvgpu_thread_stop_graceful() and signal the cond in the callback after
the thread is marked to be stopped. The quiesce thread will then wake up
from the cond wait and see the thread should stop.

JIRA NVGPU-4987

Change-Id: I29322d7867acc33a91092016c540e00bb1ae945a
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306024
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
0220409d0f gpu: nvgpu: unit: fix mutex reacquire fail for l4t 
Currently, setup_sw_s2 case of test_gv11b_mm_mmu_fault_setup_sw() in
hal.mm.mmu_fault fails for L4T OS. setup_sw_s2 test case executes
gv11b_mm_mmu_fault_info_mem_destroy() twice consecutively. This makes
the test acquire hub_isr_mutex after being destroyed; leading to failure
This patch removes setup_sw_s2 case to resolve this error. Local GCOV
report shows that there is no change in coverage with this change.

Jira NVGPU-4780

Change-Id: I7b9470180d8f3146ac09318ed34281f723cc7e1a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2302212
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
c383b631d7 gpu: nvgpu: check power state in pci shutdown 
Bail out if dGPU has not been powered on,

Bug 2867345

Change-Id: I3c388f9fb801cc97de7d9d2c9c3b21bc88e530fa
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2304269
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 2020-12-15 14:13:28 -06:00
Nicolin Chen
5e854efa65 gpu: nvgpu: Maximize DMA segmentation boundary 
Linux kernel has a default 32-bit segmentation boundary for
any device that doesn't explicitly configure it. When nvgpu
tries to allocate a larger memory > 4GB, iommu_dma_map_sg()
function in the kernel will take this boundary into account
and add an internal padding to the allocated IOVA space:

|<---IOVA space 1--->|<---padding--->|<---IOVA space 2--->|

When DMA reads/writes the memory using this discountinued
IOVA space, it may end up with accessing the padding part,
instead of the IOVA space 2.

So this patch adds dma_set_seg_boundary() to nvgpu driver,
by maximizing the segmentation boundary up to DMA_BIT_MASK
to ensure a continued IOVA space.

Bug 200558567

Change-Id: I979d56681dddca56f1b02fce83dc81147a6b0d82
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2304150
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 2020-12-15 14:13:28 -06:00
Philip Elcan
d9c6faa102 gpu: nvgpu: unit: mm: fix double destroy of mutex 
Update mm unit test for nvgpu_mm_remove_support() to avoid calling the
HAL info_mem_destroy() a second time. info_mem_destroy() destroys a
mutex, so if it is called a second time, it will errantly try to destroy
it again.

JIRA NVGPU-4987

Change-Id: I6e384b15955d4059662ded3679293456d9697a0e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2304124
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 2020-12-15 14:13:28 -06:00
Seema Khowala
ffe44aab13 gpu: nvgpu: mc: add hooks for nvgpu-next 
JIRA NVGPU-4864

Change-Id: I692d041d005b0d62813df5f16d21c8ae92a2c3e0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2293201
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 2020-12-15 14:13:28 -06:00
Philip Elcan
d01ab94537 gpu: nvgpu: unit: mm: remove errant call to info_mem_destroy 
Remove the second call to info_mem_destroy() in the unit test
test_page_faults_clean(). This did not add any additional coverage
and causes an attempt to access an invalid mutex since it is destroyed
by the first call.

JIRA NVGPU-4987

Change-Id: Ibbf5c4c300802566b6260f0236f705d48bebf3ee
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2302644
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 2020-12-15 14:13:28 -06:00
sagar
88e27271eb gpu: nvgpu: fix static analysis issues 
coverity tool is not detecting the lenght validation done at caller.
moved length checks to appropriate functions.

used macro instead of hardcoded values.

Jira NVGPU-4780

Change-Id: Ie6b420a6e625eed5374715fd7ca5c87d3ba3d015
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2302335
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Sagar Kamble
7aea87fb42 gpu: nvgpu: fix syncpt_cmdbuf_gv11b_fusa.o build 
On Linux, syncpt_cmdbuf_gv11b_fusa.c was not being compiled under the
config flag CONFIG_TEGRA_GK20A_NVHOST. Fix it.

Bug 2834141

Change-Id: Ib87b019d27f22b534905787b54c807eb7e9e13b4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300720
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00