The ALIGN() and ALIGN_MASK() macros were causing INT30 CERT-C
violations because of possible wrap issues. Update the macros to check
for potential wrap cases.
JIRA NVGPU-3515
Change-Id: I2af50fe036e8fcaf27e484af134c4a54fa4d19a1
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124998
Reviewed-by: Automatic_Commit_Validation_User
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pbdma fault recovery function reads pbdma status info to retrieve
channel id, tsg id and engine id. pbdma interrupts can only be cleared
after that information has been read otherwise because pbdma exits
from stall state, channel/tsg/engine could have changed and fault
recovery function reads information different from that when interrupt
is issued.
Bug 2123866
Change-Id: Ia0e0462ae02ec89a333c81bd933a74fbae8ae1e7
Signed-off-by: Peng Liu <pengliu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123774
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MISRA rule 5.7 forbids from re-using tag or identifier names multiple
times. Multiple definitions of a tag or identifier may create developer
confusion.
Currently, enum nvgpu_unit definition is used in gk20a.h as type of
function arguments without including unit.h header file. MISRA scanner
considered this as two different definitions for the enum. Including
correct header file resolves this issue.
Jira NVGPU-3307
Change-Id: I824888084632e8897c7c0edcc2b05adfea4a6aff
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122465
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- Fix Misra rule 20.7: Macro parameter expands into an expression without being
wrapped by parentheses.
- Following two macros has been updated to fix the above violation,
HZ_TO_MHZ_ULL and MHZ_TO_HZ_ULL.
Jira NVGPU-3176
Change-Id: I03f7d8f7d5c91ca33fcc594fed0359d5c62eea6b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120192
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.
Jira NVGPU-3248
Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Instead of using unsigned long for all __hweight variants
use unsigned int as it's sufficient to hold the result
without any data loss.
This also matches with return type used in other OS variants
like Linux and helps avoid CERT-C errors.
Error: CERT INT31-C:
drivers/gpu/nvgpu/common/gr/fs_state.c:76:
cert_violation: Casting "__hweight32(val)" from "unsigned long" to
"unsigned int" without checking its value may result in lost or
misinterpreted data.
JIRA NVGPU-3410
Change-Id: I7b9167ee21afd04b4ecc05faa838834e1047bf0d
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119993
GVS: Gerrit_Virtual_Submit
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Add functions which perform addition, subtraction and
multiplication of u32 and u64 types in a secure way
returning an error if operand type cannot correctly hold
the operation result.
Also, add type casting functions which handle conversions to
ensure that a conversion doesn't result in lost or misinterpreted
data.
JIRA NVGPU-3432
Change-Id: I1a622a178a907cc3fe5e48317a5bb9267220bd74
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118520
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For some units, we want to use register spaces with
data already initialized with power-on register values.
Added the following routines:
- nvgpu_posix_io_register_reg_space
- nvgpu_posix_io_unregister_reg_space
Jira NVGPU-3476
Change-Id: Id4f5beb5e5d6b4af795e2eb58ccee13d2cfa6da5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120563
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MISRA rule 5.7 forbids from re-using tag or identifier names multiple
times. Multiple definitions of a tag or identifier may create developer
confusion.
Enum nvgpu_nvlink_link_mode and nvgpu_nvlink_sublink_mode definitions
were used in gk20a.h as return types to functions without including
nvlink_link_mode_transitions.h header file. MISRA scanner considered
this as two different definitions for these enums. Including correct
header file resolves this issue.
Jira NVGPU-3303
Change-Id: I1f8e198620ee20d81e663df2faa32337851abb93
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120458
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Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.
Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.
Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.
Bug 2515097
Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
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Fix 8.2 violation for not specifying parameter name in prototype of
secure_alloc().
Fix 21.3 & 21.8 violations for using reserved names "free" and "exit."
Fix 8.6 and 21.2 violations for __gk20a_do_idle() and
__gk20a_do_unidle() by renaming the functions and wrapping them in a
missing #ifdef CONFIG_PM.
Fix 5.7 violation for reusing "class" as parameter name when already
defined as a struct.
JIRA NVGPU-3343
Change-Id: I976e95a32868fa0a657f4baf0845a32bd7aceb9e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117913
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Check return value of below function and add void to ignore
the return value
update_gp_get
Rename
nvgpu_get_gp_free_count -> nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_gp_free_count -> nvgpu_channel_get_gpfifo_free_count
JIRA NVGPU-3388
Change-Id: I6e2265882c1f34e3bb47eaeac7a2c5a9fbe9b4eb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115784
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This fixes MISRA rule 4.7 violations in the function nvgpu_vm_map(). The
violations were caused by trying to use ERR_PTR() to return error
information. Rather than try to return errors in a pointer, just change
the API to return an int and pass the pointer the arguments.
JIRA NVGPU-3332
Change-Id: I2852a6de808d9203b8c7826e2b8211bab97ccd16
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114027
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Fix cert c violations in common.gr
CERT INT31-C: unsigned long to unsigned int without checking, it value
may result in lose or misintepreted data.
Casting the U64 data type define to U32 is causing certc violation.
To avoid this error, add define BITS_PER_BYTE_U32 as a U32 data type.
CERT EXP34-C: dereferencing null pointer "g".
Jira NVGPU-3411
Change-Id: I9eaf76bde967ee075244723c51239a7c85d09e96
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118146
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Below MISRA 21.6 violation is reported in nvgpu.common.mm.as
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/as.c:79:
misra_violation: Using function "snprintf".
Fix this by replacing snprintf with strncpy.
Add nvgpu_strnadd_u32 function to convert u32 to string
The function supports radix from 2 to 16.
Jira NVGPU-3333
Change-Id: Idee739dfdedeabb74d0d9f7d4cddd798445f0ee1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117019
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Below MISRA 10.1 violation is reported in nvgpu.common.mm.as
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/as.c:69:
misra_violation: The expression "({...})" of non-boolean essential
type is being interpreted as a boolean value for the operator "!".
Fix this by adding an explicit cast to bool in is_power_of_2
macro.
Jira NVGPU-3333
Change-Id: I81e0110a6cd66088a5a39c63521efa41cbd90f48
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117018
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Allocate space at runtime for PMU RTOS fw struct, this helps
to reduce the size of nvgpu_pmu struct when LS_PMU support
is not required.
Allocation happens at pmu early init stage & will deinit at
remove_support stage.
JIRA NVGPU-1972
Change-Id: I1452b085f8d3a76e12186f788c2d999a8b4b202d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111072
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MISRA rule 10.1 requires that the operands shall not be of an
inappropriate essential type.
MISRA rule 10.3 requires that the values of an expression shall not be
assigned to an object with narrower essential type or of a different
essential type category.
MISRA rule 10.4 requires both the operands of an operator in which the
usual arithmetic conversions are performed to have the same essential
type category.
MISRA rule 10.8 requires that the value of a composite expression shall
not be cast to a different essential type category or a wider essential
type.
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore.
Fix violations of rules 10.1, 10.3, 10.4, 10.8 and 21.2 in types unit.
Jira NVGPU-3300
Change-Id: I3be4218ec8785aa9a116765233273097993baf0d
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117921
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Below MISRA 21.1 violation is reported in nvgpu.common.utils
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/utils.h:56:
misra_violation: The NVGPU_GET_IP shall not be defined or undefined.
Below MISRA 21.2 violation is reported in nvgpu.common.utils
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/utils.h:56:
misra_violation: The NVGPU_GET_IP shall not be declared.
Fix this by renaming _NVGPU_GET_IP_ to NVGPU_GET_IP
Jira NVGPU-3327
Change-Id: Ied94d8c8d80c2b26df8e742c18255c3dc657d59a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116696
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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