pbdma fault recovery function reads pbdma status info to retrieve
channel id, tsg id and engine id. pbdma interrupts can only be cleared
after that information has been read otherwise because pbdma exits
from stall state, channel/tsg/engine could have changed and fault
recovery function reads information different from that when interrupt
is issued.
Bug 2123866
Change-Id: Ia0e0462ae02ec89a333c81bd933a74fbae8ae1e7
Signed-off-by: Peng Liu <pengliu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123774
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MISRA rule 5.7 forbids from re-using tag or identifier names multiple
times. Multiple definitions of a tag or identifier may create developer
confusion.
Currently, enum nvgpu_unit definition is used in gk20a.h as type of
function arguments without including unit.h header file. MISRA scanner
considered this as two different definitions for the enum. Including
correct header file resolves this issue.
Jira NVGPU-3307
Change-Id: I824888084632e8897c7c0edcc2b05adfea4a6aff
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122465
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Since dGPU support is not required for initial safety release, compile
out dGPU sw and hal implementations except below files that are used
by gv11b currently: acr_sw_gv100.c, engine_status_gv100.c, gr_gv100.c
gr_config_gv100.c and hwpm_map_gv100.c.
JIRA NVGPU-3062
Change-Id: I8a6bc8b235e7e5eac5b0e76147b8bd12f9abbd2d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119586
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Since nvlink support is not required for initial safety release, disable
corresponding functionality.
nvgpu_mss_nvlink_init_credits defn. and call is now compiled out using
CONFIG_TEGRA_NVLINK config option.
JIRA NVGPU-3062
Change-Id: I402ed123f07f96125d640fb340957da4828d714a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119584
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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moved some gv100 ACR functions to gv11b as gv11b will be used for
safety build & gv11b dependency on gv100 will removed with this
changes to compile out gv100 ACR files from safety build.
LS-PMU ACR related functions put under NVGPU_LS_PMU check
to compile out those functions for safety-build
JIRA NVGPU-3418
Change-Id: I1af29c649e8ef7f46e369f00245efe93a55d1658
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123739
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MISRA Rule 11.3 prohibits casting between different pointer types. The
previous "fix" in nvgpu_bios_parse_rom() was to use an intermediate cast
to uintptr_t. However, that leaves the possibility of creating a
mis-aligned pointer. So, instead of casts, use nvgpu_memcpy() to make a
copy of the data in a local structure.
JIRA NVGPU-3317
Change-Id: I3f9dd0d6c10a7425f300b51410be2e248177b505
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122390
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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- Fix Misra rule 20.7: Macro parameter expands into an expression without being
wrapped by parentheses.
- Following two macros has been updated to fix the above violation,
HZ_TO_MHZ_ULL and MHZ_TO_HZ_ULL.
Jira NVGPU-3176
Change-Id: I03f7d8f7d5c91ca33fcc594fed0359d5c62eea6b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120192
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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MISRA rule 5.7 doesn't allow reuse of tag or variable names as this
would lead to developer confusion. Patch renames page_alloc_slab_page
struct pointer's local variable name to page_ptr to resolve the
violation. Also, renames function "nvgpu_page_alloc" to
"nvgpu_page_balloc" to remove identifier name overloading.
MISRA rule 10.x forbids from casting value of composite expression to an
object with different essential type category. This patch replaces
multiplication operation to left shift operation.
MISRA rule 15.7 requires every if .. else if construct to be terminated
with an else statement. This patch updates if .. else if condition to
resolve the violation.
MISRA Rule 17.2 doesn't allow recursive call from a function to itself,
as this might lead to stack overflow. Updated nvgpu_page_allocator_init
to call nvgpu_buddy_allocator_init() directly.
MISRA rule 21.6 doesn't allow use of snprintf from standard library.
This patch replaces snprintf call with string functions.
JIRA NVGPU-3338
Change-Id: Ic8cb956edb3c72811752008de192e6e8ba12463e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA rule 21.1 forbids the use of #define and #undef on a reserved
identifier or reserved macro name. Fix violations of rule 21.1 in
os_sched unit.
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore. Fix violation of MISRA rule 21.2 in os_sched unit.
Jira NVGPU-3299
Change-Id: Ib772f60adf5e81935f9cd2044ff8f6a402e15d82
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121955
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.
Jira NVGPU-3248
Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Add makefile targets to the tmake nvgpu-drv build to execute the arch.py
script before compiling the driver. This ensures that our source matches
our YAML at all times.
Also add one YAML fix to make sure the arch check actually passes!
JIRA NVGPU-3075
Change-Id: Ic893a26889732ce55ce16b0188da337629921e6b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119821
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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Error: CERT INT31-C:
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c:281:
cert_violation: Casting "ts >> 32" from "unsigned long long" to
"unsigned int" without checking its value may result in lost
or misinterpreted data.
Error: CERT INT31-C:
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c:186:
cert_violation: Casting "enable" from "bool" to "unsigned int"
without checking its value may result in lost or misinterpreted data.
JIRA NVGPU-3410
Change-Id: I4879c8e09d8498bb2377b166035ae0e79adf8870
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119397
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Instead of using unsigned long for all __hweight variants
use unsigned int as it's sufficient to hold the result
without any data loss.
This also matches with return type used in other OS variants
like Linux and helps avoid CERT-C errors.
Error: CERT INT31-C:
drivers/gpu/nvgpu/common/gr/fs_state.c:76:
cert_violation: Casting "__hweight32(val)" from "unsigned long" to
"unsigned int" without checking its value may result in lost or
misinterpreted data.
JIRA NVGPU-3410
Change-Id: I7b9167ee21afd04b4ecc05faa838834e1047bf0d
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119993
GVS: Gerrit_Virtual_Submit
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Error: CERT INT31-C:
drivers/gpu/nvgpu/common/gr/obj_ctx.c:310:
cert_violation: Casting "size" from "unsigned long" to "unsigned int"
without checking its value may result in lost or misinterpreted data.
Error: CERT INT30-C:
drivers/gpu/nvgpu/common/gr/obj_ctx.c:594:
cert_violation: Unsigned integer operation
"(*g->ops.gr.init.get_patch_slots)(g, config) * 2U" may wrap.
JIRA NVGPU-3410
Change-Id: Icae8246903693d7f5ad66635d3e81d22f6ff2df5
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118522
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Error: CERT INT30-C:
drivers/gpu/nvgpu/common/gr/ctx.c:644:
cert_violation: Unsigned integer operation
"gr_ctx->patch_ctx.mem.size / 4UL - 2UL" may wrap.
Error: CERT INT31-C:
drivers/gpu/nvgpu/common/gr/ctx.c:580:
cert_violation: Casting "gr_ctx->boosted_ctx" from "bool" to "unsigned int"
without checking its value may result in lost or misinterpreted data.
JIRA NVGPU-3409
Change-Id: Ib3c865d43ecd3c0eaaafd47b7b65111aa77689bd
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118521
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Add functions which perform addition, subtraction and
multiplication of u32 and u64 types in a secure way
returning an error if operand type cannot correctly hold
the operation result.
Also, add type casting functions which handle conversions to
ensure that a conversion doesn't result in lost or misinterpreted
data.
JIRA NVGPU-3432
Change-Id: I1a622a178a907cc3fe5e48317a5bb9267220bd74
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118520
GVS: Gerrit_Virtual_Submit
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