Below MISRA 10.1 violation is reported in nvgpu.common.mm.as
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/as.c:69:
misra_violation: The expression "({...})" of non-boolean essential
type is being interpreted as a boolean value for the operator "!".
Fix this by adding an explicit cast to bool in is_power_of_2
macro.
Jira NVGPU-3333
Change-Id: I81e0110a6cd66088a5a39c63521efa41cbd90f48
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117018
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Allocate space at runtime for PMU RTOS fw struct, this helps
to reduce the size of nvgpu_pmu struct when LS_PMU support
is not required.
Allocation happens at pmu early init stage & will deinit at
remove_support stage.
JIRA NVGPU-1972
Change-Id: I1452b085f8d3a76e12186f788c2d999a8b4b202d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111072
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Update the shared config file to use the safety build flag NV_BUILD_
CONFIGURATION_IS_SAFETY instead of NVGPU_REDUCED. With these changes
posix userspace and tests will be built in two configs based on this
flag.
JIRA NVGPU-3062
Change-Id: Iaf34dd1a8f66f2dd3f351365c369ed46a484a257
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116402
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Due to dependency on nvrm ioctl whitelisting, switch to user mode
submit and rmserver, we can't disable virt support, USERD, LS PMU
and debugger functionalities yet. Update the config options setup
accordingly. With these changes safety build will have same code
compiled as normal build.
JIRA NVGPU-3062
Change-Id: I99d1bb1c7bb8c244cab9d04304aa760c09e7dd1e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113483
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Since the safety build config options for qnx build are to be adhered
by posix userspace build as well, let us create shared configs file.
Add these config options to unit tests makefile as we would need to
control the tests based on these options and tests also access the
common nvgpu functions.
JIRA NVGPU-3062
Change-Id: I292eca9ac3160eed93485afddf7c30e993e0461c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116401
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA rule 10.1 requires that the operands shall not be of an
inappropriate essential type.
MISRA rule 10.3 requires that the values of an expression shall not be
assigned to an object with narrower essential type or of a different
essential type category.
MISRA rule 10.4 requires both the operands of an operator in which the
usual arithmetic conversions are performed to have the same essential
type category.
MISRA rule 10.8 requires that the value of a composite expression shall
not be cast to a different essential type category or a wider essential
type.
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore.
Fix violations of rules 10.1, 10.3, 10.4, 10.8 and 21.2 in types unit.
Jira NVGPU-3300
Change-Id: I3be4218ec8785aa9a116765233273097993baf0d
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117921
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Below MISRA 10.4 violation is reported in nvgpu.common.mm.nvgpu_sgt
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/nvgpu_sgt.c:131:
misra_violation: Essential type of the left hand operand
"mem->mem_flags & 8ULL" (unsigned) is not the same as that of the
right operand "0ULL"(signed).
Fix this by changing right hand operand to 0U.
Jira NVGPU-3334
Change-Id: Ib28bfce363a807ba9f8fa9df9cbb02c636a74898
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117034
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Below MISRA 21.1 violation is reported in nvgpu.common.utils
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/utils.h:56:
misra_violation: The NVGPU_GET_IP shall not be defined or undefined.
Below MISRA 21.2 violation is reported in nvgpu.common.utils
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/utils.h:56:
misra_violation: The NVGPU_GET_IP shall not be declared.
Fix this by renaming _NVGPU_GET_IP_ to NVGPU_GET_IP
Jira NVGPU-3327
Change-Id: Ied94d8c8d80c2b26df8e742c18255c3dc657d59a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116696
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Below MISRA 8.6 violation is reported in nvgpu.common.mm.mm
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/mm.h:184:
declaration_with_no_definition: "nvgpu_init_mm_setup_hw" is
declared but never defined.
Fix this by removing nvgpu_init_mm_setup_hw declaration.
Jira NVGPU-3331
Change-Id: I78352c13e6c85cc67a261f62fe33eff64b5f6f5f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116707
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Below MISRA 17.7 violation is reported in nvgpu.common.mm.mm
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/mm.c:645:
misra_c_2012_rule_17_7: The return value of a non-void function
"*g->ops.bus.bar1_bind" is unused.
Fix this by checking return value and returning an error in
case of failure.
Jira NVGPU-3331
Change-Id: Iab43d630163af782d3cc87989a64062516a4cd92
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116706
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 10.1 violation is reported in nvgpu.common.mm.mm
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/mm.c:378:
misra_violation: The expression "g->mm.vidmem.size" of non-boolean
essential type is being interpreted as a boolean value for the
operator "&&".
Fix this by explicitly checking g->mm.vidmem.size > 0U.
Jira NVGPU-3331
Change-Id: I1bb54736593801c7cb684973f411459dae6f008d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116705
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 21.2 violation is reported in nvgpu.common.rbtree
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/rbtree.c:188:
misra_violation: _delete_fixup shall not be declared.
Fix this by renaming to delete_fixup.
Jira NVGPU-3305
Change-Id: I09d8da721cc87d3bb9e4a23d00a31a82a8759365
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116681
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 15.7 violation is reported in nvgpu.common.rbtree
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/rbtree.c:200:
misra_violation: No non-empty terminating "else" statement.
Fix this by re-factoring for loop.
Also re-arranged code to avoid lines over 80 chars.
Jira NVGPU-3305
Change-Id: If7586f1ac9bc411751c92b94969123788a273cf8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116680
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 20.7 requires macro paramaters to be wrapped in parantheses
when the parameter expands into an expression. Fix violations of rule
20.7 in atomic unit.
MISRA rule 10.3 prohibits the assignment of the value of an expression
to an object with narrower essential type or of a different essential
type category. Fix violations of rule 10.3 in atomic unit.
Jira NVGPU-3296
Change-Id: I087a6d15c5d03885aea29f22853e5bbde7880014
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116306
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Avoid use of local variable "max" by renaming it to "max_netlist_num"
JIRA NVGPU-3420
Change-Id: Ie0a49aa6c24617d22efe401ae883d0a9c8b1dff0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116066
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Use uintptr_t casting to avoid following error:
The object pointer expression "netlist_fw->data" of type "u8 *"
is cast to type "struct netlist_image *"
JIRA NVGPU-3420
Change-Id: Ice2e22eefc40c1f33ee9be68f460d3f8b3a2225c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116065
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Below MISRA 10.3 violation is reported in hal.gr.config unit
Error: MISRA C-2012 Rule 10.3:
nvgpu/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c:174:
misra_violation: Implicit conversion of "pix_scale * min_scg_gpc_pix_perf + world_scale *
scg_world_perf + tpc_scale * tpc_balance" from essential type "unsigned 32-bit int" to different
or narrower essential type "signed 32-bit int".
Fix this by declaring corresponding variables u32.
This should have no functional impact as such
Jira NVGPU-3406
Change-Id: I5b66c8db25c33afec3ab622a8d45997d5c8e6daa
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115591
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 10.3 violation is reported in hal.gr.config unit
Error: MISRA C-2012 Rule 10.3:
nvgpu/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c:150:
misra_violation: Implicit conversion of "(int)average_tpcs - scale_factor * num_tpc_gpc[gpc_id]"
from essential type "unsigned 32-bit int" to different or narrower essential type "signed 32-bit int".
Fix this by converting "diff" variable to u32 and checking for greater
value before doing subtraction operation
Jira NVGPU-3406
Change-Id: I27695db5bd3a4f20db878888dc87dc78ff04888a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115590
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 10.3 violations are reported in hal.gr.config unit
Error: MISRA C-2012 Rule 10.3:
nvgpu/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c:72:
misra_violation: Implicit conversion of "gpc_tpc_mask[gpc_id]" from essential type
"unsigned 64-bit int" to different or narrower essential type "unsigned 32-bit int".
gpc_tpc_mask[] and tpc variables should really be u32, hence declare
them as u32 everywhere
for_each_set_bit() takes parameters as unsigned long
Use temporary unsigned long variables in above macro and then
explicitly cast them to/from u32
Jira NVGPU-3406
Change-Id: Idd1dc2ba95bd1f6a3968a0103f0ec4914101f629
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115589
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule 13.5 states that the right hand operand of a logical && or ||
operator shall not have persistent side effects. Update the while loop
in gk20a_wait_for_idle() to comply.
JIRA NVGPU-3318
Change-Id: I3e51361914c298416bab1f2f7500d743ce409c8b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114658
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule 21.2 prohibits naming identifiers beginning with a double
underscore. This updates the function names __nvgpu_check_gpu_state()
and __gk20a_warn_on_no_regs() to comply.
JIRA NVGPU-3318
Change-Id: Ied2d168272a0f45fb8a08dda0e6fc798ebe3d22d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114656
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix MISRA violations for Rule 10.6 and 10.8 in gr.init unit
Assigning composite expression of width 32 to a target of width 64.
Cast from 32 bit width to a wider 64 bit type.
Jira NVGPU-3390
Jira NVGPU-3391
Change-Id: Id06fa9c90ae6cea1a7251b7834aca3f2c2f76e53
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116154
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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