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7686 Commits

Author SHA1 Message Date
Vinod G
340ea241cb gpu: nvgpu: remove channel debug_dump hal 
Channel debug_dump hal function does not involve
any register related code.

Move gv11b_channel_debug_dump hal function to
common code nvgpu_channel_info_debug_dump function.

Check gpu hw version to limit instance variables
dump that differs between socs.

Add new hal pointer syncpt_debug_dump for pbdma.

Jira NVGPU-5109

Signed-off-by: Vinod G <vinodg@nvidia.com>
Change-Id: Icfca837ce8e4117387cffa6fadf6c094c7da5946
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321016
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
62c06723dd gpu: nvgpu: sim: defer sim buffers allocation 
Allocate sim buffers only after chip specific
memory properties are enabled.

JIRA NVGPU-5281

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I7b64b3a51b8cd66dbefd22a09216b2caaeccacbf
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2324083
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Sagar Kamble
c37c1b5474 gpu: nvgpu: fix null pointer access in nvgpu_vm_find_mapping 
mapped_buffer sgt is deallocated by dma_buf_unmap_attachment in the
function nvgpu_vm_find_mapping if it is previously mapped. Debug
print referred to the sgt page after deallocating hence move it
before deallocation.

Fix below null pointer dereference issue:

[   34.692659] Unable to handle kernel NULL pointer dereference
at virtual address 0000000000000000
...
[   34.699820] Hardware name: Jetson-AGX (DT)
[   34.709136] pc : nvgpu_vm_find_mapping+0xcc/0x240 [nvgpu]
[   34.714377] lr : nvgpu_vm_find_mapping+0xa4/0x240 [nvgpu]
...
[   34.804523] Call trace:
[   34.807093]  nvgpu_vm_find_mapping+0xcc/0x240 [nvgpu]
[   34.812195]  nvgpu_vm_map+0xd4/0x480 [nvgpu]
[   34.816168]  nvgpu_vm_map_linux+0x15c/0x1c8 [nvgpu]
[   34.821237]  nvgpu_vm_map_buffer+0x14c/0x270 [nvgpu]
[   34.825962]  gk20a_as_dev_ioctl+0x320/0xfe0 [nvgpu]
[   34.830955]  do_vfs_ioctl+0xb8/0xa40
[   34.834449]  ksys_ioctl+0x80/0xb8
[   34.837430]  __arm64_sys_ioctl+0x1c/0x28
[   34.841630]  el0_svc_handler+0x80/0x1a8
[   34.845129]  el0_svc+0x8/0xc
[   34.848106] Code: f9400021 d360ff3a b9406a62 f940007c (f9400034)
[   34.854227] ---[ end trace 1d8c4efb211dc317 ]---

Bug 2834141

Change-Id: I281ac21071fcc2e3e6f3685798c8e77daba6d4a4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323361
Tested-by: Debarshi Dutta <ddutta@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Debarshi Dutta
f483304238 gpu: nvgpu: add prerequisite for syncpoint-shim support 
add check for nvgpu_has_syncpoints() before enabling syncpoint-shim and
usermode_syncpoint support. Syncpoint shim cannot exist without
syncpoint support in the first place.

Bug 200551105

Change-Id: I2a9c6d23c72a25bcac4a2a8737ed0bad14cd4d8f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323208
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
ec54b8b2ad gpu: nvgpu: sim: set remove_support hal to NULL 
Found issues with removing sim support for igpu.
Set sim->remove_support to NULL  until JIRA NVGPU-5281
is fixed.

JIRA NVGPU-5257

Change-Id: I2c8af7a0d05f963233378bdb3aa2afcfc4f32b6e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2322987
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
6cb6a970af gpu: nvgpu: don't update ch syncpt for user sync 
g->ops.channel.set_syncpt() updates the inst block's allowed syncpt
field for the syncpoint that's allocated for kernelmode submits (if
any). This is different from the userspace-owned syncpoint that is used
with usermode submits, so don't call set_syncpt when creating the user
syncpt.

If the kernel sync object wouldn't exist, the call would even fail. The
allowed syncpt is written during nvgpu_channel_setup_bind() (if usermode
submit isn't requested), after the kernel syncpt is allocated.
Originally, just one syncpoint used to be shared for the kernel and
userspace; now that they're separate, this different path to update the
allowed syncpt would need other modifications to work with the user sync
if one would be used on platforms that care about the allowed syncpt.

Jira NVGPU-4548

Change-Id: If800e704ef8a3289e04c8d75a623affd6779e309
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2320357
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
675fb39ca0 gpu: nvgpu: add runlist.init_enginfo hal 
Add runlist.init_enginfo hal to initialize
runlist's engine info. nvgpu-next has it's own
implementation for init_enginfo hal, so removed
NVGPU_NEXT_INIT_RUNLIST_ENGINFO from nvgpu hals.

JIRA NVGPU-4979

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Ie35a88c6ba3c7c741124386f7c643b36b42d4143
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319103
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
2f6be2735e gpu: nvgpu: remove nvgpu-next gr init 
nvgpu-next gr init is handled within nvgpu-next
hals. So remove references to NVGPU_NEXT_INIT_GR_INFO from
nvgpu hals.

JIRA NVGPU-4979

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I2e493220f855a7ff2f940cf07b1fc0b876601df5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319102
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Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
44f12288ad gpu: nvgpu: add mc.reset_engine hal for nvgpu-next 
Engine reset process has changed for nvgpu-next. Add mc.reset_engine
gops for nvgpu-next.
Modify engine reset functions to use mc.reset_engine hal.

Jira NVGPU-5145

Change-Id: I176800212042eaef71c8cbd4bc499805c5af0e60
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2312485
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Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Debarshi Dutta
a2080a1208 gpu: nvgpu: add fuse clock support 
1) added support for fuse clock directly from nvgpu linux build for GV11B
and GP10B.
2) added a common function platform_acquire_clock thats used by both
GP10B, GV11B to acquire their respective clocks.
3) remove use of tegra_fuse_clock_enable/disable APIs

The clock parsing code is changed to verify the clock-names obtained
via DT with the static clock-names in the platform code before proceeding
with clk_enable.

Bug 2887230

Change-Id: I177cde9c4bf1a8be6f3437f36e1c6f75cd9c9279
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307136
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
002fb2431d gpu: nvgpu: nvgpu-next changes for fifo pbdma 
- Include nvgpu_next_pbdma.h in pbdma.h
- NULL check for fifo.init_pbdma_map hal before allocating
  memory for f->pbdma_map
- NULL check for f->pbdma_map before freeing memory for
  f->pbdma_map

JIRA NVGPU-4979

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I5eacc671b924c947620b2c49c8f82577c30ba1a3
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317804
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
b7767a604f gpu: nvgpu: add intr_top_enable fifo gops 
This is required for enabling fifo interrupts for nvgpu-next.

JIRA NVGPU-4864

Change-Id: I5c09105296a01b82505023ecf576d71ce74f7a31
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313013
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
d0ffb335dc gpu: nvgpu: move nvgpu_has_syncpoints 
nvgpu_has_syncpoints is more general than a channel synchronization
related, so move it to nvhost.c from channel_sync.c. Move the
declaration from gk20a.h to nvhost.h.

As the debugfs knob is Linux related, move it from struct gk20a to
struct nvgpu_os_linux.

Jira NVGPU-4548

Change-Id: I4236086744993c3daac042f164de30939c01ee77
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318814
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
db9c1b1f97 gpu: nvgpu: don't build sw semas for dgpu 
Make tu104's sema cmd HAL ops depend on CONFIG_NVGPU_SW_SEMAPHORE
in addition to the kernel mode submit flag.

Drop CONFIG_NVGPU_SW_SEMAPHORE from NVGPU_FORCE_DGPU_SAFETY_PROFILE.
Semaphore-based synchronization is not actually needed for dgpu.

Jira NVGPU-4548

Change-Id: I3fe066dbeb68295dfc4bbe09256ff6a20c892c2f
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318737
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 2020-12-15 14:13:28 -06:00
ajesh
9846573d64 gpu: nvgpu: handle the return values from OS APIs 
Handle the return values from standard OS library calls.

Jira NVGPU-4987

Change-Id: I41bf0113097d6bfa344ed58f68448abc9cc7f367
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299985
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 2020-12-15 14:13:28 -06:00
Terje Bergstrom
d7927778b3 gpu: nvpgu: posix: Remove unused static nvhost func 
Remove unused statuc function nvgpu_nvhost_syncpt_nb_hw_pts.

Change-Id: I73f6990957390e8ec0b93ca341056d30e17b79c5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318386
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 2020-12-15 14:13:28 -06:00
Terje Bergstrom
32db53d4e1 gpu: nvgpu: posix: Pass atomic types to atomic ops 
Atomic functions require the type of manipulated atomic to be of
_Atomic type.

Change-Id: I8cf417a2b15ef34488b82560b65d5abfbe67fde8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Terje Bergstrom
6d4e4f633f gpu: nvgpu: posix: Use non-atomic types when appropriate 
Atomic functions return non-atomic types. Change the type definitions
and casts to follow that.

Change-Id: If6fbfa5f75810151fe4765874f3dd610b85a39d1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318384
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
88c774e5d1 gpu: nvgpu: enable clk_arb for dGPU safety 
Enable CONFIG_NVGPU_CLK_ARB for dGPU safety build.

Use CONFIG_NVGPU_NON_FUSA for invocation of non-safe functions:
- nvgpu_hr_timestamp
- nvgpu_hr_timestamp_us

Jira NVGPU-4661
Jira NVGPU-5235 (for addressing usage of above functions).

Change-Id: I271fdbc45c1e4d01cb70d50dcf63d15b9df33c76
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317842
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
401d4cbc5f gpu: nvgpu: reorganize tegra clocks enable/disable 
When the tegra powergate support is not present, genpd takes care of
powergating. However, clocks are still controlled by nvgpu driver.
Hence enable/disable tegra clocks when the tegra powergate support
is not available.

Bug 2834141

Change-Id: I7ca4e5002604b30de6bddcf640d78b939136dd4d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316879
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
25edcc1353 gpu: nvgpu: cta preemption mode HAL for tu104 
Use gp10b_ctxsw_prog_set_compute_preemption_mode_cta instead
of gm20b_ctxsw_prog_set_compute_preemption_mode_cta for tu104.

Jira NVGPU-4661

Change-Id: I7b85cbcc139e6843c8b7bd89e0afb6030160362f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316206
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
28ccd63f69 gpu: nvgpu: enable CONFIG_NVGPU_LS_PMU for safety 
Enable CONFIG_NVGPU_LS_PMU for dGPU safety build.
Add missing #ifdefs for CONFIG_NVGPU_POWER_PG and
CONFIG_NVGPU_CLK_ARB which are not defined for safety build.

Moved gm20b_mc_is_enabled to fusa code.

NVGPU_UNIT_PWR is only defined when CONFIG_NVGPU_HAL_NON_FUSA
is defined. Added #ifdefs to compile out gk20a_pmu functions
that are using it.

Jira NVGPU-4661

Change-Id: Ieb552f9374bad6f3dad777322f118931e0bc94ec
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317085
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
1adf23eea5 gpu: nvgpu: build flags for dGPU safety 
Add the following flags for dGPU safety build:
- CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
- CONFIG_NVGPU_SM_DIVERSITY
- CONFIG_NVGPU_USE_3LSS_ERR_INJECTION

Jira NVGPU-4661

Change-Id: I50df5677f6b53d835852ef29fb378d4817bd4e2b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2315694
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
46761356e5 gpu: nvgpu: make channel sync ops const 
The function pointers for the syncpoint and semaphore implementations of
struct nvgpu_channel_sync do not change in runtime. Make this more
explicit by having the pointers in predefined private structures. Each
instance of a sync (which there are one per open channel) gets a pointer
to an ops structure instead of a list of all the individual ops.

Jira NVGPU-4548

Change-Id: I361b74bdfe32470203760d11c30e048cb4d20b77
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318242
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
fa6cf4598e nvgpu: userspace: update therm unit init 
Update therm unit testcase: test_setup_env to include assignment of hal
function: therm_max_fpdiv_factor.

Jira: NVGPU-4860

Change-Id: I644191cdd4d4538d0c189af9cb80cea3d6368820
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317074
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
da8ee8d615 gpu: nvgpu: add therm_max_fpdiv_factor gops.therm 
Use therm_max_fpdiv_factor gops.therm for nvgpu-next to get the maximum
fp_div_factor.

Jira NVGPU-4860

Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Change-Id: If0e9b82f5b61289e226ceeff386fc88763af66e2
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313336
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 2020-12-15 14:13:28 -06:00
Abdul Salam
4f5bd9e633 gpu: nvgpu: Implement clk_good and pll_lock check 
Add clk_good and pll_lock check as a part of fmon polling.
This will poll for any clock related faults at FTTI interval.
Add new function to poll for vbios init completion.

NVGPU-4967
Bug 2849506
Bug 200564937

Change-Id: I5bc885329981e07376824e148edabe9be4120e1c
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2305782
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 2020-12-15 14:13:28 -06:00
sagar
b8a3e54dda gpu: nvgpu: add invalid ctxsw method 
* For ctxsw negative testing, nvgpu need to send and invalid method
 * Sending 0xFFFF method will result in triggering ctxsw error intr.

JIRA NVGPU-5080

Change-Id: I6c16137d86ee2ddb25f1508161d9d6befcbcbefe
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317502
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 2020-12-15 14:13:28 -06:00
Seema Khowala
21e2214c3d gpu: nvgpu: support nvgpu-next intr config 
JIRA NVGPU-4864

Change-Id: I2fb5be3270c73ea891021161f539a7f731e05f63
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
a5b3170c6f gpu: nvgpu: Refactor allocator lite unit 
- Changed the names of structs as per private/public
  naming convention.
- Renamed allocator.c file

NVGPU-4487

Change-Id: I42ec5730f1cb0029a6bb6e6ddff151bd08d6bbd8
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316945
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
f254a09094 gpu: nvgpu: fix dgpu build for next kernels 
Add the following changes to build dgpu sources for kernels after 4.14:
1. tegra_alloc_fd is defined by downstream tegra mc driver built with
   the flag CONFIG_NV_TEGRA_MC, hence make the nvgpu config
   NVGPU_USE_TEGRA_ALLOC_FD dependent on it.
2. dma_buf_ops.map_atomic is removed in kernel version 4.17.
3. gk20a_vidbuf_ops.set_drvdata and .get_drvdata are to be set
   under the config CONFIG_NVGPU_DMABUF_HAS_DRVDATA

Bug 2834141

Change-Id: If2351beddfd6f22a1a1da4499cacf6a1880ede76
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316486
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
f43d5df83a gpu: nvgpu: build dGPU in safety 
Enable build flags for dGPU in safety, when
NVGPU_FORCE_DGPU_SAFETY_PROFILE is set.

Use libnvgpu-dgpu_safe.exports for dGPU safety build.

Add build flags for tu104 HAL initialization (to solve
undefined symbols in safety build).

Temporarily add non-fusa files needed to build dGPU in safety.
related functions will have to move to fusa files.

Jira NVGPU-4611

Change-Id: I41db0c039c7f15d9191cdb811b4906e779d5cc88
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310276
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
872b3946dd gpu: nvgpu: add nvgpu-next fb gops 
JIRA NVGPU-5222

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I3004fcfd9cf17b81c6d218954da140982a76c6fd
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316212
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 2020-12-15 14:13:28 -06:00
rmylavarapu
f5acc98db3 gpu: nvgpu: Refactor Super surface lite unit 
- Changed the names of structs as per private/public
  naming convention.
- Removed unwanted code in struct super_surface.

NVGPU-4486

Change-Id: I5834c2296ccbe1545bca6a608ad88817a9104fb8
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313989
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 2020-12-15 14:13:28 -06:00
vinodg
a9d8fc96a7 gpu: nvgpu: hal correction for class error handling 
Add new hal function
gp10b_gr_intr_handle_class_error.

Update handle_class_error hal function for
gp10b, gv11b and tu104 to
gp10b_gr_intr_handle_class_error from
gm20b_gr_intr_handle_class_error.
gr_trapped_data_mme_pc uses 12 bits from gp10b.

Move gm20b_gr_intr_handle_class_error hal function
to non-fusa section.

Jira NVGPU-4913

Signed-off-by: vinodg <vinodg@nvidia.com>
Change-Id: Ic93013ba43d4bf409527109f2f2d43db11c4238e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2314249
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
ebb91f0b4d gpu: nvgpu: gv11b: use read_engine_status_info gops for preempt poll 
Use read_engine_status_info hal to read engine status and use
NVGPU_CTX_STATUS_* for engine ctxsw_status check instead of
directly reading h/w registers and field defs. This will make
gv11b preempt driver usable for nvgpu-next.

JIRA NVGPU-4982

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Id063f9791f38715aed3a9c7999fd253b1bc2bc87
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2311276
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
f91495c41d gpu: nvgpu: cond. compile with CONFIG_NV_TEGRA_MC 
Protect tegra MC code under the config flag CONFIG_NV_TEGRA_MC.

Bug 2834141

Change-Id: Ibb883ca69ea26467f095aca22552b1ad20279cd9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306434
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 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
1f6dfb54d1 gpu: nvgpu: Remove hard coded constants from ACR 
During code inspection use of some hard constants was
found in some parts of the code.
Those constants are replaced by macros

JIRA NVGPU-5030

Change-Id: I09212be40746317440218bc7ada9a578dde7c6ed
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2301596
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
682966ef4c gpu: nvgpu: posix: add some nvhost primitives 
Add the following primitives to resolve build issues
when enabling dGPU in safety build:
- nvgpu_nvhost_syncpt_is_expired_ext
- nvgpu_nvhost_syncpt_is_valid_pt_ext
- nvgpu_nvhost_syncpt_incr_max_ext
- nvgpu_nvhost_intr_register_notifier
- nvgpu_nvhost_get_syncpt_host_managed
- nvgpu_nvhost_syncpt_wait_timeout_ext
- nvgpu_nvhost_syncpt_read_ext_check

Jira NVGPU-4661

Change-Id: Iabd7b2a9addc96ed48f42aedb5640a17c6dce62c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2314207
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
0c23bf57ea gpu: nvgpu: build flag for secure boot 
Use CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT build flag for
gm20b_gr_falcon_fecs_host_int_enable.

Jira NVGPU-4661

Change-Id: Id7d991b81206d00e38049556b42b4e9a4abd1708
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313620
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
d980bd2781 gpu: nvgpu: build flag for fb mmu debug mode 
Use CONFIG_NVGPU_DEBUGGER for the following function:
- gv100_fb_set_mmu_debug_mode

Jira NVGPU-4661

Change-Id: Ia074fcab6695ba20b3cf1ef86f08d1b1735fcefe
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313590
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 2020-12-15 14:13:28 -06:00
Thomas Fleury
8ec4395e82 gpu: nvgpu: build flag for deterministic channel 
Add CONFIG_NVGPU_DETERMINISTIC_CHANNELS and fix
preprocessor #ifdefs to allow compiling kernel mode
submit without deterministic feature enabled.

Jira NVGPU-4661

Change-Id: I4aa678715824e8981d39bd8db0c5ae61ef3a675c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310325
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
cc043e1506 gpu: nvgpu: cond. compilation of tegra dvfs code 
Protect the code dependent on tegra dvfs and bpmp dvfs code under the
config flags CONFIG_TEGRA_DVFS and CONFIG_NV_TEGRA_BPMP.

Also, update clk_config_dvfs and clk_program_na_gpc_pll to handle the
error value returned from g->ops.clk.predict_mv_at_hz_cur_tfloor.

Bug 2834141

Change-Id: I124d29f22e59fd6af7801ca859c4470483c8f7d8
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306433
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
bf353cea6c gpu: nvgpu: sim_pci: reconcile sim escape paths between RM and nvgpu 
SIM models are getting updated to have same escape read path
for RM and nvgpu. Updated nvgpu driver code to have same escape
read mechanism as RM for dgpu.

Required for dgpu to work on NET23.

Bug 2539889
Bug 200582707

Change-Id: Ied05dae00928d44249df695429fb5029331f1286
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2256665
Reviewed-by: Lakshmanan M <lm@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Abdul Salam
53bd199e30 gpu: nvgpu: Seperate clk monitor from clk unit 
Clock monitor is for monitoring clk status.
This is separated from clk unit which manages the clk.

NVGPU-4491

Change-Id: If83434db7970f1b024f545672a6f1e92ee66dbbc
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313201
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 2020-12-15 14:13:28 -06:00
Seeta Rama Raju
5ce7d5acff gpu: nvgpu: Add fault injection variable for clock UT 
Bug 2861451

Change-Id: Ie51c1524c47934e44cde06515f5daccd8e1e7dd9
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
(cherry picked from commit d57a51ba6db7b6c2df28d1770727506214b85e08)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2310971
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
7aa9e90bfc gpu: nvgpu: update gops.cg 
Update gops.cg to include following runlist level cg ops:
- blcg_runlist_load_gating_prod
- slcg_runlist_load_gating_prod

Jira NVGPU-5048

Change-Id: Ia2a3f887d5c2fd6f1dd35d606afd19d117468c2c
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300448
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Sagar Kamble
490e1ee06c gpu: nvgpu: conditional compile of tegra powergate 
Include tegra bpmp and powergate headers under the config flag
CONFIG_NV_TEGRA_BPMP.
tegra186-powergate.h included by tegra powergate header defines
TEGRA186_POWER_DOMAIN_GPU that can be used to conditionally
compile the railgate code similar to t194.

Bug 2834141

Change-Id: Ib52923ec02438f0f10ea78d6a8874f387e17ee2c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306435
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Sagar Kamble
59c6947fc6 gpu: nvgpu: add CONFIG_NVGPU_TEGRA_FUSE 
Encapsulate the tegra fuse functionality under the config flag
CONFIG_NVGPU_TEGRA_FUSE.

Bug 2834141

Change-Id: I54c9e82360e8a24008ea14eb55af80f81d325cdc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306432
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 2020-12-15 14:13:28 -06:00
Sagar Kamble
3748be5792 gpu: nvgpu: move timer functions from soc files 
Move following timer functions from soc header and c file to timer
header and c file:
1. nvgpu_delay_usecs
2. nvgpu_us_counter
3. nvgpu_get_cycles

Bug 2834141

Change-Id: I04cf7229a0d35c90a320bbe64e80912b08cccefb
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306431
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00