g->ops.gr.enable_cde_in_fecs and g->ops.gr.update_boosted_ctx
are no longer required since we can directly call
g->ops.gr.ctxsw_prog.set_cde_enabled and
g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies
respectively
remove those functions and the ops
Jira NVGPU-1526
Change-Id: Idb0ad5f634e78aac44ec325ba2b7f59c612b29e8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972184
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Commit ca611e4d0e (gpu: nvgpu: verify usermode mapping is at least
PAGE_SIZE) was not quite the right thing to do; do_mmap() rounds the
length up to a page boundary anyway, but the length must not be longer
than the size of the usermode region which is 64 KB to avoid leaking
access to other registers.
Bug 2441531
Change-Id: Ib1c88a6725db62c8276b6e8b880631227a4fc8cd
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971339
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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MISRA rule 16.3 states all switch clause to have break statement.
Fixing the missing break statement for default case.
Two consecutive labels without statement need not have break.
So no break is added for case without any statement.
This also makes the switch statement well-formed covering 16.1.
JIRA NVGPU-1510
JIRA NVGPU-1536
Change-Id: I2c16888cbcb429f49f1f260e18b7c6eba55aa83c
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1964328
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Icb724f3424c8161c12b69d373ff08c7648f79e56
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1834225
GVS: Gerrit_Virtual_Submit
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Remove gp106 and add gv100 unit test
This is as a part of removing gp106 support
This adds testing for gv100 to the fuse unit test
Removes check_sec/non_sec as they are not used
Removes delta SRAM fuse as they are not present in GV100
Bug 200457373
Change-Id: I9bb4b714500eae01d0df00bb9f6842d4d4fbfd12
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1960034
GVS: Gerrit_Virtual_Submit
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GSPLITE falcon base address was being set without invoking hal api.
This patch defines gpu_ops.gsp.falcon_base_addr hal api to get this
base address.
JIRA NVGPU-1587
Change-Id: Id187b34d022f90c09b8762cdab7769323b607cc0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969432
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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GPCCS falcon base address was being set without invoking hal api. Remove
FALCON_GPCCS_BASE. This patch defines gpu_ops.gr.gpccs_falcon_base_addr
hal api to get this base address.
JIRA NVGPU-1587
Change-Id: Icfa7a26d1bb2d67c81f05a43f6ce906f59706b3d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969431
Reviewed-by: Automatic_Commit_Validation_User
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FECS falcon base address was being set without invoking hal api. Remove
FALCON_FECS_BASE. This patch defines gpu_ops.gr.fecs_falcon_base_addr hal
api to get this base address.
JIRA NVGPU-1587
Change-Id: I9c8e60be4ee81a154020c982893725a12ebb72ef
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969430
Reviewed-by: Automatic_Commit_Validation_User
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SEC2 falcon base address was being set without invoking hal api. Remove
FALCON_SEC_BASE. This patch defines gpu_ops.sec2.falcon_base_addr hal api
to get this base address.
Also, don't initialize the base for non-supported falcons.
JIRA NVGPU-1587
Change-Id: Iad19a9987416076cf9090d30a48ff83369cf73c2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969429
Reviewed-by: Automatic_Commit_Validation_User
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PMU falcon base address was being set without invoking hal api. Remove
FALCON_PWR_BASE. This patch defines gpu_ops.pmu.falcon_base_addr hal api
to get this base address.
JIRA NVGPU-1587
Change-Id: I5c3f27e89bdcc775025bc8d4fa9cf0af11ceb002
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969428
Reviewed-by: Automatic_Commit_Validation_User
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NVDEC falcon base address was being set without invoking hal api. Remove
FALCON_NVDEC_BASE. This patch defines gpu_ops.fb.falcon_base_addr hal api
to get this base address. Currently gp106 and tu104 have these
implemented. gv100 uses the gp106 hal interface.
Also, don't initialize the base for non-supported falcons.
JIRA NVGPU-1587
Change-Id: I0be759b8462ede9b85690a70431480afdee9602c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969427
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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For gk20a & gp106, nvgpu driver currently hardcodes base address for FECS,
GPCCS, NVDEC falcons. Instead, emit those register in the hw headers. Base
address is the address of IRQSSET register.
JIRA NVGPU-1587
Change-Id: I710c4006b5ef6ded7980491ac157f8c03399b831
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966643
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This unit test verifies that the PD cache is capable of packing
multiple PD allocations into a single page. The verification works
by using the DMA fault injection method to prevent more than one
DMA alloc from happening in the pd_cache code.
If an OOM error is detected by the pd_cache code before the max
number of PDs per page is allocated by the pd_cache then there's
a failure in the packing code.
The correct number of PDs per page is easy to calculate: it's
just PAGE_SIZE / pd_size.
JIRA NVGPU-1323
Change-Id: I2c5b58ecf32da48d503c576012d9e564a270144c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1970876
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Added gpc_ppc_count, pes_tpc_count and pes_tpc_mask to constants so they
are used to init the according structure in gr.
They are needed to support get_nonpes_aware_tpc.
Bug 200452721
Jira GVSCI-91
Change-Id: Idbb59daab58c9877eab373439771b19c28cbcef1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1967997
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PMU counters #0 and #4 are used to count total cycles and busy cycles.
These counts are used by podgov to estimate GPU load.
PMU idle intr status register is used to monitor overflow. Overflow
rarely occurs because frequency governor reads and resets the counters
at a high cadence. When overflow occurs, 100% work load is reported to
frequency governor.
Bug 1963732
Change-Id: I046480ebde162e6eda24577932b96cfd91b77c69
Signed-off-by: Peng Liu <pengliu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1939547
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NVGPU_CTXSW_IOCTL_RING_SETUP can be used to setup a custom ring buffer
and it accepts size via arguments. nvgpu driver will return an error
if size requested is greater than 128 * 4096 but this value is hardcoded
and not exposed anywhere.
Add characteristics field in nvgpu.h to expose this size so that corresponding
nvrm_gpu API can use it.
Bug 2169674
Change-Id: Icf9465d4eec6ba3a307ea9490bd5da563944e4f6
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1967596
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We had to force allocation of physically contiguous memory for
USERD in nvlink case, as a channel's USERD address is computed as
an offset from fifo->userd address, and nvlink bypasses SMMU.
With 4096 channels, it can become difficult to allocate 2MB of
physically contiguous sysmem for USERD on a busy system.
PBDMA does not require any sort of packing or contiguous USERD
allocation, as each channel has a direct pointer to that channel's
512B USERD region. When BAR1 is supported we only need the GPU VAs
to be contiguous, to setup the BAR1 inst block.
- Add slab allocator for USERD.
- Slabs are allocated in SYSMEM, using PAGE_SIZE for slab size.
- Contiguous channels share the same page (16 channels per slab).
- ch->userd_mem points to related nvgpu_mem descriptor
- ch->userd_offset is the offset from the beginning of the slab
- Pre-allocate GPU VAs for the whole BAR1
- Add g->ops.mm.bar1_map() method
- gk20a_mm_bar1_map() uses fixed mapping in BAR1 region
- vgpu_mm_bar1_map() passes the offset in TEGRA_VGPU_CMD_MAP_BAR1
- TEGRA_VGPU_CMD_MAP_BAR1 is called for each slab.
Bug 2422486
Bug 200474793
Change-Id: I202699fe55a454c1fc6d969e7b6196a46256d704
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959032
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This adds APIs to the POSIX sgt module to allow unit tests to create
sgt's and sgl's more easily. The new APIs allow the caller to pass in a
table of sgl's and creates the new sgt/sgl as needed.
Since this there is a new API to create an sgl, this also includes a new
nvgpu_sgl_free() API.
JIRA NVGPU-1563
Change-Id: I27ab7654289cbd2212a75625b6dd24d2b742e3bf
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966151
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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There were several places were nvgpu_mem structs were declared on the
stack and not initialized. Some fields could be used erroneously by
underlying APIs.
To allow the initialization of an array of nvgpu_mem in
test_dma_alloc_fi_delayed_enable(), the array length had to be changed
from a const to a macro.
JIRA NVGPU-1563
Change-Id: I6c23445af7d932710898df2e23a8fd892bee77b3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1967966
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Add separate new unit gr/ctxsw_prog that provides interface to access
h/w header files hw_ctxsw_prog_*.h
Add below chip specific files that access above h/w unit and provide
interface through g->ops.gr.ctxsw_prog.*() HAL for rest of the units
common/gr/ctxsw_prog/ctxsw_prog_gm20b.c
common/gr/ctxsw_prog/ctxsw_prog_gp10b.c
common/gr/ctxsw_prog/ctxsw_prog_gv11b.c
Remove all the h/w header includes from rest of the units and code.
Remove direct calls to h/w headers ctxsw_prog_*() and use HALs
g->ops.gr.ctxsw_prog.*() instead
In gr_gk20a_find_priv_offset_in_ext_buffer(), h/w header
ctxsw_prog_extended_num_smpc_quadrants_v() is only defined on gk20a
And since we don't support gk20a remove corresponding code
Add missing h/w header ctxsw_prog_main_image_pm_mode_ctxsw_f() for
some chips
Add new h/w header ctxsw_prog_gpccs_header_stride_v()
Jira NVGPU-1526
Change-Id: I170f5c0da26ada833f94f5479ff299c0db56a732
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966111
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals or casting operands
to have same type of operands when an arithmetic operation is
performed.
This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I27e3e59c3559c377b4bd3cbcfced90fdf90350f2
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921459
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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This is part of a move to 64KiB for usermode mapping to fix failures
when the system page size is 64KiB. When remapping or zapping the
vma, use the existing size, not hardcoded size. Also change the
verification of the size when creating the mapping to verify it is at
least as big as PAGE_SIZE. This allows 4KiB mappings to continue to
work until nvrm_gpu is changed to use 64KiB mappings.
Bug 2441531
Change-Id: I447ef8e9f84e6d70bbe96b527e267ec41c5630b8
Signed-off-by: Allen Martin <amartin@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1964687
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With MSI enabled and kernel 4.14, there are some occurrences of
interrupts not being launched (no issue on kernel 4.9). If
an interrupt is not served for a software method, we end up most
of the time with PBDMA busy, while engine is idle.
Disable MSI for dGPU on kernel 4.14
Bug 200460636
Change-Id: I3c5657d63195de5c714f44d331ac992199811d9f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968073
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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MISRA Rule 10.1 states that operands shall not be of an
inappropriate essential type.
For example, the use of bitwise OR on signed values is not
permitted.
This patch restructures return status assignment in the
gr_tu104_init_sw_bundle64() routine to eliminate the use
of bitwise OR when constructing the return value.
Rather than continue to attempt to submit bundles after an
idle failure the routine instead now returns immediately on
the first error.
This seems like a reasonable/better approach given the contents
of the context buffer are in a questionable state after the
first error anyway and the client that issued ALLOC_OBJ_CTX will
continue to properly see the error.
Also, this patch changes the type of the return variable
('err') from u32 to int to match the function prototype.
JIRA NVGPU-650
Change-Id: I2aae0f85d0373ddf95b5899ce8c452352c6aa670
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1965496
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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In nvgpu_sim_esc_readl() we prepare a message, issue RPC and then copy back
the response from offset "data_offset + 0xc"
But while configuring the message we incorrectly set the response offset as
just "data_offset"
Fix this by correctly configuring the response offset as "data_offset + 0xc"
Jira NVGPUT-41
Change-Id: I855e140b97e7128367446d0962eec283b069f514
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756844
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If enabled, fecs trace updating happens from ucode
side even when there is no fecs trace dumper application
to consume it. Due to this, trace buffer will get
eventually full and ucode will trigger ctxsw_intr0.
Reset fecs_trace buffer to handle timestamp buffer full
ctxsw_intr0.
Bug 2361571
Bug 200472922
Change-Id: Ia26a17635fc6bd6e8663b8af983acc91839ecfcd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1965370
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ctxsw_intr0 is triggered by ucode even if it
is not enabled by driver. Add handling
for processing ctxsw_intr0. fecs mailbox(6)
is used to report fecs/gpccs misc error codes.
Also dump falcon stats for unhandled fecs intr.
Bug 2361571
Bug 200472922
Change-Id: Iefb3c0d46ad1d08db07fd3c08cff91a77835908c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966984
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MISRA Rule 5.7 Definition: A tag name shall be a unique identifier.
Rule 5.7 violations can occur if a variable has the same name as a
struct. bios.c defines a "struct bit". "bit" is a very common name for
variables which causes a name conflict with "struct bit". Therefore,
change "struct bit" to "struct bios_bit" to resolve rule 5.7 violations.
Jira NVGPU-845
Change-Id: I02f2fa6cf1701c7de2e365635b18ecee0f8296fa
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1965693
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Add a flag that let's userspace enable the unified VM functionality
on a selective bassis. This feature is working for all cases except
a single MODS trace. This will allow test coverage to be selectively
added in certain userspace tests as well to help prevent this feature
from bit rotting (as it has historically done).
Also update the unit test for the page table management in the GMMU
to reflect this new flag. It's been set to false since the target
platform for safety is currently not using unified address spaces.
Bug 200438879
Change-Id: Ibe005472910d1668e8372754be8dd792773f9d8c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951864
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The pd_cache header declarations were oriignally part of the
gmmu.h header. This is not good from a unit isolation perspective
so this patch moves all the pd_cache specifics over to a new
header file: <nvgpu/pd_cache.h>.
Also a couple of static inlines that were possible when the code
was part of gmmu.h were turned into real, first class functions.
This allowed the pd_cache.h header to not include the gmmu.h
header file.
Also fix an issue in the nvgpu_pd_write() function where the data
was being passed as a size_t for some reason. This has now been
changed to a u32.
JIRA NVGPU-1444
Change-Id: Ib9e9e5a54544de403bfcd8e11c30de05721ddbcc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966352
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MISRA Rule 10.3 states that the value of an expression shall not
be assigned to an object with a narrower essential type or of a
different esseential type category.
For example, assigning an unsigned 32bit value (u32) to a signed
32bit value (int) is not permitted.
This patch modifies the gr_gk20a_init_golden_ctx_image() and
gk20a_init_sw_bundle() routines to use an int (instead of u32)
for return status handling making them consistent with the other
gr routines used in this part of the gr object allocation path.
JIRA NVGPU-647
Change-Id: I53c47d9a169bd0d4cdbce107bd4ad8e7978ae01d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1965735
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule 11.8 states that a cast shall not remove any const or
volatile qualification from the type pointed to by a pointer.
The linux kernel's container_of() macro contains such a violation as
it generates a pointer to a caller-specified (and so possibly non-const
qualified) type by casting an internally declared const pointer.
The gk20a_from_pmu() uses the container_of() macro to convert
from a struct nvgpu_pmu pointer to a struct gk20a pointer.
The struct nvgpu_pmu has a back pointer to struct gk20a already
however and so this change modifies gk20a_from_gpu() to just
return this back pointer rather than use container_of().
JIRA NVGPU-862
Change-Id: If0e2481c1cf104c2fa6b89334e20e75705bf9c44
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1955540
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
All the 16.x MISRA rules are relevant to switch statement
formatting and hence addressed in single patch
As per MISRA 16.1, all switch statements should be well formatted.
16.3 fixes:
Add unconditional break statements to all the switch-clauses
to adhere to MISRA rule 16.3. Also do not allow fall-through
(even the intentional ones) from one switch-clause to next one.
16.4 fixes:
Make sure all "default" clauses in the switch statements are
non-empty.
16.6 fixes:
Fix all switch statement formatting to fix MISRA 16.6 violations
which requires all the switch clauses to be conforming.
JIRA NVGPU-1496
JIRA NVGPU-1533
JIRA NVGPU-1550
JIRA NVGPU-1558
Change-Id: I7f373e99491eb860ca7c9edfeb43a32ad0b07baa
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1961694
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
