Add below two new APIs to set preemption buffer in graphics context or
subcontext respectively
nvgpu_gr_ctx_set_preemption_buffer_va()
nvgpu_gr_subctx_set_preemption_buffer_va()
Remove g->ops.gr.set_preemption_buffer_va() hal and use above APIs to
set preemption buffer VA.
Jira NVGPU-1887
Change-Id: I38fb76eaf01d3fc73fd8104f30bcd89be9fa45b6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076272
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Add new hals in unit hal.gr.init to commit RTV circular buffer
g->ops.gr.init.commit_rtv_cb()
g->ops.gr.init.commit_gfxp_rtv_cb()
Remove tu104 hal to commit global ctx buffers
gr_tu104_commit_global_ctx_buffers() since we have specific hals to
commit RTB circular buffer
Update gr_gk20a_commit_global_ctx_buffers() to directly call
hal.gr.init hals to commit RTV buffers
Jira NVGPU-2961
Change-Id: I12a53386654ebfeb98bf187385bb8b839070d569
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075230
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Add a new hal.gr.init unit hal g->ops.gr.init.get_rtv_cb_size() to
retrieve RTV buffer size
Update gr_gk20a_alloc_global_ctx_buffers() to initialize RTV buffer
size if g->ops.gr.init.get_rtv_cb_size hal is present
Remove gr_tu104_alloc_global_ctx_buffers() since it is no longer
required
Jira NVGPU-2961
Change-Id: I44be8dfdda5c813eac445192635a3a6c2b867b3a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075229
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Move g->ops.gr.commit_global_timeslice() hal operation to hal.gr.init
unit as g->ops.gr.init.commit_global_timeslice()
Drop channel pointer in parameter list since it was unused
Also change return type to void since it never returns error
Move corresponding gm20b and gv11b hal operations to hal.gr.init unit
Jira NVGPU-2961
Change-Id: I68deef45af1d52149eb354a1478cc2b5f2e4ec2a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075228
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Add a new hal operation g->ops.gr.init.load_method_init() in hal.gr.init
unit that reads method init netlist bundle and writes those values to
h/w appropriately
Use new hal in gr_gk20a_init_golden_ctx_image() instead of direct
register accesses
Jira NVGPU-2961
Change-Id: If1edd09445e55b5ad9cb1ec7b0f32cab9bfd6f05
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075227
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nvrm_gpu_tests uses dGPU detach/attach APIs to test
GCOFF sequence. This results in a timeout on tu104 while
detaching dGPU.
...snip...
[start: NvRmGpuTest_Lib_AttachDevice]
Detaching dGPU at index 2001...
[ 89.933604] -- nvrm_gpu_tests: Ended subtest
NvRmGpuTest_Device_ChooseKind_Color_Incompressible
[ 91.473919] nvgpu: 0001:01:00.0 __nvgpu_timeout_expired_msg_retry:118 [ERR]
No more retries @ gk20a_mm_fb_flush+0xd4/0x328 [nvgpu]
[ 91.474280] nvgpu: 0001:01:00.0 gm20b_fb_dump_wpr_info:240 [ERR]
WPR: 08000080 08000081 01c00002 01c01e03 1ffffe04 00000005
...snip...
Increase retries from 2000 to 2500 which seems to be sufficient.
Bug 200491474
Change-Id: I7bab4e39c677361d3642e034f5bdb9ba75d4c450
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019432
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The fb APIs compression_page_size() and compression_align_mask() were
returning u32s, but the users all really need u64s.
This also eliminates MISRA Rule 10.3 violations for implicit casts to
smaller size objects.
JIRA NVGPU-2954
Change-Id: I8dc2b434d9564c89c0e8a1b19c4acbe167e339c1
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075595
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Native and vgpu were using different paths for fifo
init/deinit code.
Use same nvgpu_fifo_init_support for init code:
nvgpu_fifo_init_support
g->ops.fifo.setup_sw
vgpu_fifo_setup_sw (NEW)
Use same nvgpu_fifo_remove_support for deinit code:
nvgpu_fifo_remove_support (NEW)
g->ops.fifo.cleanup_sw (NEW)
vgpu_fifo_cleanup_sw (NEW)
Also implemented gk20a_fifo_cleanup_sw for native case.
Jira NVGPU-1306
Jira NVGPU-2855
Change-Id: Iefe303cc224f804a206422e2efffda9da1616d89
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029649
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gr_ctx->gfxp_rtvcb_ctxsw_buffer buffer is already being released in
nvgpu_gr_ctx_free() and there is no need for this tu104 specific hal
Remove gr_tu104_free_gr_ctx() and re-use gr_gk20a_free_gr_ctx() for
tu104
Jira NVGPU-1887
Change-Id: Iee2bc04d3911e0f030170a032f3f457b67ce7e74
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075234
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Move code used for transitioning between link and sublink modes
into a separate unit called 'link_mode_transition' under subelement
'nvlink'.
Also aggregate all the link/sublink mode related ops under
g->ops.nvlink.link_mode_transitions.
JIRA NVGPU-2862
Change-Id: I289faa10fd1c83b6b8d028b44fe244531ca42b15
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2035794
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Moved cbc related code and data from gr to cbc unit.
Ltc and cbc related data is moved from gr header:
1. Ltc related data moved from gr_gk20a -> gk20a and it
will be moved eventually to ltc unit:
u32 slices_per_ltc;
u32 cacheline_size;
2. cbc data moved from gr_gk20a -> nvgpu_cbc
u32 compbit_backing_size;
u32 comptags_per_cacheline;
u32 gobs_per_comptagline_per_slice;
u32 max_comptag_lines;
struct gk20a_comptag_allocator comp_tags;
struct compbit_store_desc compbit_store;
3. Following config data moved gr_gk20a -> gk20a
u32 comptag_mem_deduct;
u32 max_comptag_mem;
These are part of initial config which should be available
during nvgpu_probe. So it can't be moved to nvgpu_cbc.
Modified code to use above updated data structures.
Removed cbc init sequence from gr and added in
common cbc unit. This sequence is getting called
from common nvgpu init code.
JIRA NVGPU-2896
JIRA NVGPU-2897
Change-Id: I1a1b1e73b75396d61de684f413ebc551a1202a57
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033286
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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To avoid the other hal calls from gr_gv11b_init_fs_state
and gr_gm20b_init_fs_state hal, move the load_tpc_mask and
load_smid_config hal to nvgpu_gr_init_fs_state common gr function.
bes_zrop_setting and bes_crop_setting for active_ltcs is moved before
the nvgpu_gr_init_fs_state call from those hals.
replace gk20a_writel and gk20a_readl in modified hal function with
nvgpu_writel and nvgpu_readl.
JIRA NVGPU-1885
Change-Id: Ic0bf4a4bfa4da032f33bbe4af89031bbbdd9cd94
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072414
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Add new hal operation g->ops.gr.init.fe_go_idle_timeout() in hal.gr.init
unit to enable/disable fe_go_idle timeout
Use this hal in gr_gk20a_init_golden_ctx_image() instead of direct
register access
Remove timeout disable/enable code in gk20a_init_sw_bundle() since
parent API gr_gk20a_init_golden_ctx_image() is already taking care of
that
Jira NVGPU-2961
Change-Id: Ice72699059f031ca0b1994fa57661716a6c66cd2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072550
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Move GR HAL operation g->ops.gr.init_preemption_state() to hal.gr.init
unit as g->ops.gr.init.preemption_state()
Create hal.gr.init unit files for gp10b and gv11b and copy over
corresponding functions to new files
This API now takes gfxp_wfi_timeout_unit and gfxp_wfi_timeout_count as
parameter
Define gfxp_wfi_timeout_unit in struct gr_gk20a as a boolean flag named
gfxp_wfi_timeout_unit_usec
Remove GFXP_WFI_TIMEOUT_UNIT_SYSCLK/USEC macros
Jira NVGPU-2961
Change-Id: I4347b1e30c86c231e44cf274adccd8c70addcdab
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072549
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Move g->ops.fecs_trace.*() HAL operations under gr operations as
g->ops.gr.fecs_trace.*()
Also rename gk20a_ctxsw_*() functions used in common code to the
format nvgpu_gr_fecs_trace_*()
Jira NVGPU-1880
Change-Id: Idf2f8fb3d7ba2832bf1837fd97b70b3cee412123
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070767
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We have 3 header files for FECS tracing support
include/nvgpu/gr/fecs_trace.h : common header
include/nvgpu/ctxsw_trace.h : header that includes both common and
os-specific functions
os/linux/ctxsw_trace.h : linux specific header
Remove the second header since it is not needed.
Move all structures that are needed in common code to
include/nvgpu/gr/fecs_trace.h
Move all function declarations that are needed in common code to
include/nvgpu/gr/fecs_trace.h
Move all linux specific declarations in os/linux/ctxsw_trace.h and
rename this file as os/linux/fecs_trace_linux.h
Also rename os/linux/ctxsw_trace.c to os/linux/fecs_trace_linux.c
Jira NVGPU-1880
Change-Id: I05cc4489c4b6a64880b7d59c02b22cd2244d5e22
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070766
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Access to falcon's EMEM has to be synchronized to ensure atomic access
to EMEM control and data registers. Add this locking.
Not all falcons support EMEM hence handle mutex based on the enabled
flag emem_supported that is set only for TU104 currently.
JIRA NVGPU-1993
Change-Id: Idaedfb564ea0068d4690a2717d7983eb2384a69f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030618
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Earlier falcon HAL ops were embedded in the falcon structure. For clear
separation of common and HAL these ops will have to be accessed through
g->ops.falcon interfaces.
With these changes nvgpu_falcon_* functions directly call falcon gpu
ops functions for falcon. Falcon registers and HAL functions are
exported from falcon_gk20a.h. HAL files per platform are now
updated with base falcon functions.
Falcon software state such as is_falcon_supported, is_interrupt_enabled
and flcn_base are set from software init functions defined per chip.
JIRA NVGPU-2038
Change-Id: Ib1729d2833cd2c6c7b2c8ed7cbc17d4d6daeba73
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2023077
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This struct was earlier moved to falcon_priv.h to give exclusive access
to only falcon unit. However with HAL unit needing access to this we
need to move it public header nvgpu/falcon.h.
JIRA NVGPU-1993
Change-Id: Ia3b211798009107f64828c9765040d628448812a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069688
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Add fifo sub-unit to common.fifo to handle init/deinit code
and global support functions.
Split init into:
- nvgpu_channel_setup_sw
- nvgpu_tsg_setup_sw
- nvgpu_fifo_setup_sw
- nvgpu_runlist_setup_sw
- nvgpu_engine_setup_sw
- nvgpu_userd_setup_sw
- nvgpu_pbdma_setup_sw
Split de-init into
- nvgpu_channel_cleanup_sw
- nvgpu_tsg_cleanup_sw
- nvgpu_fifo_cleanup_sw
- nvgpu_runlist_cleanup_sw
- nvgpu_engine_cleanup_sw
- nvgpu_userd_cleanup_sw
- nvgpu_pbdma_cleanup_sw
Added the following HALs
- runlist.length_max
- fifo.init_pbdma_info
- fifo.userd_entry_size
Last 2 HALs should be moved resp. to pbdma and userd sub-units,
when available.
Added vgpu implementation of above hals
- vgpu_runlist_length_max
- vgpu_userd_entry_size
- vgpu_channel_count
Use hals in vgpu_fifo_setup_sw.
Jira NVGPU-1306
Change-Id: I954f56be724eee280d7b5f171b1790d33c810470
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029620
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In the commit "gpu: nvgpu: unit: update misc atomics to use gcc
builtins" the cmpxchg macro used by the "POSIX" build changed and
introduced a MISRA 17.3 violation for a macro parameter that needed
parentheses. This updates the macro to resolve this violation.
Change-Id: I16927ecaa751964f8c397c95086c663a683f8241
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070064
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Register write from gr_gk20a_init_fs_state function are moved to hal.
New hal added for setting the pd_tpc_per_gpc, pd_skip_table_gpc and
cwd_gpcs_tpcs_num.
pd_tpc_per_gpc helps to describe the number of tpcs in each logical
gpc.
pd_skip_table helps to skip certain TPCs during distribution.
cwd_gpcs_tpcs_num helps to set number of tpcs and gpcs in CWD.
remove write for depreciated NV_PBE_PRI_ZROP_SETTING_NUM_ACTIVE_FBPS
and NV_PBE_PRI_CROP_SETTINS_NUM_ACTIVE_FBPS fields from
BES_ZROP_SETTINGS and BES_CROP_SETTINGS registers. Both these fields
changed to NUM_ACTIVE_LTCS from gm20b onwards and those are being
set in existing hal functions.
JIRA NVGPU-2951
Change-Id: I905b98356e8eadaf7e2481850de841c050ea50c5
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072249
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create new hals for wait_idle and wait_fe_idle under gr.init.
modify functions to following hals and use same hals for all chips.
gr_gk20a_wait_idle -> gm20b_gr_init_wait_idle
gr_gk20a_wait_fe_idle -> gm20b_gr_init_wait_fe_idle
JIRA NVGPU-2951
Change-Id: Ie60675a08cba12e31557711b6f05f06879de8965
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072051
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Add VM unit tests for the following requirements:
- NVGPU-RQCD-45.C1: A valid GPU virtual address is/is not generated
for the buffer passed into nvgpu_vm_map().
- NVGPU-RQCD-45.C2: When a GPU virtual address is passed into the
nvgpu_vm_map() function the resulting GPU virtual address of the
map does/does not match the requested GPU virtual address.
JIRA NVGPU-1927
Change-Id: I7c9f7204772a611ff7baa56b6434a70d5b70cd27
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2036213
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
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Some chips bypass the IOMMU on tegra. Essentially any chip using
nvlink will fall into this category.
This imposes certain oddities in the memory management for these
chips. For these chips we do not want nor need IOMMU mappings
and the overhead that comes with doing that. Instead nvgpu can
manage allocation of pages itself.
For contiguous memory nvgpu still does need to rely on the CMA.
As such this flag can be used for determining whether to use the
special nvgpu managed page allocation (for normal allocs) or the
DMA API (and therefor the CMA) for contiguous allocs.
Bug 200444660
Change-Id: I3dc4ba6ea9523f2a59966b13527d5a416aaa761a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071090
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The latest GPU uses nvlink and its own MMU to access memory,
instead of SMMU like others. So it doesn't go through IOMMU
framework to allocate physically non-contiguous memory. The
DMA API had a pair of downstream functions to allocate the
memory for this situation, but it is removed since it's not
likely acceptable for upstream kernel.
In order not to hack the dma-direct ops that by its meaning
is supposed to provide contiguous memory, this patch adds a
pair of memory-allocation functions inside the gpu driver,
since nvgpu is the only user.
This pair of functions are only used when GPU driver doesn't
go through either dma-direct (FORCE_CONTIGUOUS) or iommu. It
also requires GPU driver to map the non-contiguous pages.
Bug 200444660
Change-Id: I26678a3f8d63bba340872beeecbb7b0e1e7a35fa
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029680
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The flag NVGPU_DMA_FORCE_CONTIGUOUS simply means that the memory
or the pages should be forced contiguous. Meanwhile, the other
flag NVGPU_DMA_PHYSICALLY_ADDRESSED means that the memory should
be contiguous from GPU perspective, either physically contiguous
when IOMMU is not used, or virtually contiguous by IOMMU.
Thus the NVGPU_DMA_FORCE_CONTIGUOUS flag is now redundant.
This patch cleans up the NVGPU_DMA_FORCE_CONTIGUOUS flag.
Bug 200444660
Change-Id: I63bb06fea728b34ec2c6f831504392d42c426d55
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2035403
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The original free routine has three options:
if (NVGPU_DMA_NO_KERNEL_MAPPING)
dma_free_attrs(d, mem->aligned_size, mem->priv.pages,
else if (other flags)
dma_free_attrs(d, mem->aligned_size, mem->cpu_va,
else /* No flags */
dma_free_coherent(d, mem->aligned_size, mem->cpu_va,
The last dma_free_coherent() can be unwrapped to dma_free_attrs
with its dma_attrs=0, while the former two are identical except
cpu_addr. So this patch merges these three into one single call
but differentiate the cpu_addr and dma_attrs parameters.
Note that the dma_free_attrs returns 0 when flags is not set.
Bug 200444660
Change-Id: I92ec0390138c79c5109973e476ea0ea719d4e2b9
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029679
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vgpu_vm_init and vgpu_vm_remove are called directly from
common code if virtualization is supported. Introduce mm
HAL ops vm_as_alloc_share and vm_as_free_share and call
these functions through these HAL ops. Also rename these functions
from vgpu_vm_init to vgpu_vm_as_alloc_share and vgpu_vm_remove to
vgpu_vm_as_free_share as these function names are too generic and
rename to reflect their actual functionality.
For now these HAL ops are initialized only for vgpu.
Jira GVSCI-517
Change-Id: I7c5af1ab5a64ce562092f75b1488524e93e8f53f
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2032310
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
gr_gk20a_init_golden_ctx_image() right now resets sys/gpc/be units by
directly accessing gr_fecs_ctxsw_reset_ctl_r() register
Move this register write/read sequence to common.hal.gr.init unit
through HAL operation g->ops.gr.init.override_context_reset()
Use new HAL in gr_gk20a_init_golden_ctx_image()
Also fix the delay() operations. delay() should be added before we read
back gr_fecs_ctxsw_reset_ctl_r() register and not after
Jira NVGPU-2961
Change-Id: I70d3a61b5aa60846815dee52ecac544066542695
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070608
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
