Reduce code complexity of following functions in gr.ecc unit
gp10b_ecc_init(complexity : 17)
gp10b_ecc_detect_enabled_units(complexity : 15)
gv11b_ecc_init(complexity : 23)
gv11b_ecc_detect_enabled_units(complexity : 30)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create four sub functions from gp10b_ecc_init function for
sub units init.
gp10b_ecc_init_lts(complexity : 2)
gp10b_ecc_init_tpc(complexity : 2)
gp10b_ecc_init_tpc_tex(complexity : 8)
gp10b_ecc_init_tpc_sm(complexity : 5)
and reduce gp10b_ecc_init complexity to 3
Create four sub functions from gp10b_ecc_detect_enabled_units function
gp10b_ecc_enable_ltc(with complexity : 4)
gp10b_ecc_enable_tex(with complexity : 4)
gp10b_ecc_enable_smshm(with complexity : 4)
gp10b_ecc_enable_smlrf(with complexity : 4)
and reduce gp10b_ecc_detect_enabled_units complexity to 3
Create four sub functions from gv11b_ecc_init function for
sub units init.
gv11b_ecc_init_tpc(complexity : 10)
gv11b_ecc_init_gpc(complexity : 6)
gv11b_ecc_init_fb(complexity : 6)
gv11b_ecc_init_other_units(complexity : 6)
and reduce gv11b_ecc_init complexity to 5
Create six sub functions from gv11b_ecc_detect_enabled_units function
gv11b_ecc_enable_smlrf(with complexity : 4)
gv11b_ecc_enable_sml1data(with complexity : 4)
gv11b_ecc_enable_sml1tag(with complexity : 4)
gv11b_ecc_enable_smicache(with complexity : 6)
gv11b_ecc_enable_ltc(with complexity : 4)
gv11b_ecc_enable_smcbu(with complexity : 4)
and reduce gv11b_ecc_detect_enabled_units complexity to 3
Jira NVGPU-3662
Change-Id: Id10be4f9a500c300f66756ebae41bfff3b734aea
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159050
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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MISRA Advisory Rule 12.3 states that the comma operator should
not be used.
This change fixes several violations of this rule in gr falcon
code.
The remaining violations of this advisory rule will be covered
in a rule-specific deviation record.
JIRA NVGPU-3798
Change-Id: Iea579356ac1da03c6730f738f5316b57e26afa7c
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155616
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Following common and corresponding hal functions are non-safe. They are
either required for intr handling or for debug. Compile them out for
igpu safety release. Moved corresponding HALs to falcon_gk20a.c.
nvgpu_falcon_copy_from_emem
nvgpu_falcon_copy_to_emem
nvgpu_falcon_clear_halt_intr_status
nvgpu_falcon_set_irq
nvgpu_falcon_copy_from_dmem
nvgpu_falcon_copy_from_imem
nvgpu_falcon_print_dmem
nvgpu_falcon_print_imem
nvgpu_falcon_get_ctls
nvgpu_falcon_dump_stats can be used in the safety debug build.
JIRA NVGPU-898
JIRA NVGPU-2214
Change-Id: Icb7f904b088aa74b976f75a6a0ecdb783486bab3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152978
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Rule 10.x necessitates operands to have essential type; left and right
operands are required to be of same width and type.
Rule 12.2 requires right hand operand of shift operator to be within
range 0 to 1 less than width of left hand operand.
Rule 20.7 requires macro parameters to be enclosed in parentheses.
This patch fixes above listed MISRA rule violations in
nvgpu/hal/fifo/ramin_gv11b_fusa.c.
Jira NVGPU-3821
Change-Id: I2d85cf8c4599e6d6f7bab1a2c3ce161d4ec93826
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153720
Reviewed-by: Automatic_Commit_Validation_User
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Reduce code complexity of following functions in gr.config unit
gv100_gr_config_init_sm_id_table(complexity : 13)
gr_gv100_scg_estimate_perf(complexity : 23)
Create sub functions by moving the control statement codes
from the function which has high complexity above 10.
Create two sub functions from gv100_gr_config_init_sm_id_table function
gr_gv100_scg_estimate_perf_for_all_gpc_tpc(complexity : 5)
gv100_gr_config_set_sminfo(complexity : 3)
and reduce gv100_gr_config_init_sm_id_table complexity to 8
Create four sub functions from
gv100_gr_config_init_sm_id_table function
gr_gv100_find_max_gpc(with complexity : 2)
gr_gv100_remove_logical_tpc(with complexity : 4)
gr_gv100_calc_valid_pes(with complexity : 6)
gr_gv100_scg_calculate_perf(with complexity : 7)
and reduce gr_gv100_scg_estimate_perf complexity to 10
Jira NVGPU-3661
Change-Id: Iaaef1a98f2c6c55cd7b0a1a57d1c74eb09d43869
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156744
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reduce code complexity of following functions in gr.intr unit
gm20b_gr_intr_handle_exceptions(complexity : 13)
tu104_gr_intr_log_mme_exception(complexity : 13)
gv11b_gr_intr_handle_icache_exception(complexity : 17)
gv11b_gr_intr_handle_gpc_gpccs_exception(complexity : 13)
gv11b_gr_intr_handle_l1_tag_exception(complexity : 15)
gv11b_gr_intr_handle_gpc_gpcmmu_exception(complexity : 15)
Create sub functions by moving the control statement codes
from the function which has high complexity above 10.
Create following 8 sub functions for handling each exception from
gm20b_gr_intr_handle_exceptions function
gr_gm20b_intr_check_gr_fe_exception(complexity : 2)
gr_gm20b_intr_check_gr_memfmt_exception(complexity : 2)
gr_gm20b_intr_check_gr_pd_exception(complexity : 2)
gr_gm20b_intr_check_gr_scc_exception(complexity : 2)
gr_gm20b_intr_check_gr_ds_exception(complexity : 2)
gr_gm20b_intr_check_gr_ssync_exception(complexity : 4)
gr_gm20b_intr_check_gr_mme_exception(complexity : 3)
gr_gm20b_intr_check_gr_sked_exception(complexity : 2)
and reduce gm20b_gr_intr_handle_exceptions complexity to 3.
Create following 2 sub functions from tu104_gr_intr_log_mme_exception
function
gr_tu104_check_dma_exception(complexity : 6)
gr_tu104_check_ram_access_exception(complexity : 3)
and reduce tu104_gr_intr_log_mme_exception complexity to 6
Create following 2 sub functions for corrected and uncorrected error
reporting from gv11b_gr_intr_handle_icache_exception function
gv11b_gr_intr_report_icache_uncorrected_err(complexity : 5)
gv11b_gr_intr_report_icache_corrected_err(complexity : 5)
and reduce gv11b_gr_intr_handle_icache_exception complexity to 9
Create following 2 sub functions for corrected and uncorrected error
reporting from gv11b_gr_intr_handle_l1_tag_exception function
gv11b_gr_intr_report_l1_tag_uncorrected_err(complexity : 4)
gv11b_gr_intr_report_l1_tag_corrected_err(complexity : 4)
and reduce gv11b_gr_intr_handle_l1_tag_exception complexity to 9
Create following 1 sub function for error reporting from
gv11b_gr_intr_handle_gpc_gpccs_exception function
gv11b_gr_intr_report_gpccs_ecc_err(complexity : 5)
and reduce gv11b_gr_intr_handle_gpc_gpccs_exception complexity to 9
Create following 1 sub function for error reporting from
gv11b_gr_intr_handle_gpc_gpcmmu_exception function
gv11b_gr_intr_report_gpcmmu_ecc_err(complexity : 5)
and reduce gv11b_gr_intr_handle_gpc_gpcmmu_exception complexity to 9
Jira NVGPU-3661
Change-Id: I855b9ba055f3a8578c7b62cd59e249017ec31936
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155852
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Rule 8.6 requires each identifier with external linkage to have exactly
one external definitions.
Rule 10.x necessitates operands to have essential type; left and right
operands should be of same width and type.
This patch fixes above mentioned in nvgpu/hal/fifo/channel_gk20a.h,
nvgpu/hal/fifo/channel_gm20b.h and nvgpu/hal/fifo/channel_gv11b_fusa.c
Jira NVGPU-3827
Change-Id: I17a1d1bc4b04404b223f73e49330bf1a41d35129
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2154362
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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Moved gv11b_fb_intr_inject_hubmmu_ecc_error from fb_intr_ecc_gv11b.c to
fusa version and deleted that file. Moved debugger related functions
from fb_gm20b.c to fusa version. Updated arch yaml to reflect the fusa
and non-fusa fb units.
JIRA NVGPU-3690
Change-Id: I929169e9aac62e8377e4ea7e8353caa970999299
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156879
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Moved gv11b_ltc_inject_ecc_error from ltc_gv11b to fusa version.
Moved debugger related functions from ltc_gm20b to fusa version.
Updated the arch yaml to reflect the non-fusa and fusa units
for ltc units.
JIRA NVGPU-3690
Change-Id: I48e360f18da760907e733023e013bd039ba5cca4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156878
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Moved debugger/cilp functions from gr ctxsw prog hal files for various
platforms to corresponding fusa files as currently they are enabled in
the safety build. Updated the arch yaml to reflect the non-fusa and
fusa units for gr ctxsw_prog.
JIRA NVGPU-3690
Change-Id: I188d3de223aa65816b5f511b776eb8278e221219
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156877
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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MISRA Advisory Rule 10.5 states that the value of an expression should
not be cast to an inappropriate essential type.
This change removes five violations of this rule that involve casting
boolean results to unsigned values:
* pass 1/0 (instead of true/false) to nvgpu_atomic operations
* fix skip_mask handling in gm20b_gr_init_pd_skip_table_gpc()
* fix l3_alloc flags check in nvgpu_gmmu_map_locked()
This change also eliminates several MISRA Advisory Rule 4.6 violations.
JIRA NVGPU-3798
Change-Id: I707da8a812bfb32eaeb2200463885c0961b197b3
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153070
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
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This patch adds SWUD (SW Unit Design) document for SDL unit. In addition,
it re-names err_type to err_id in error reporting APIs related to ECC, GR,
PRI and MMU, to keep the name consistent with other APIs.
JIRA NVGPU-3758
Change-Id: I968218574aa78144497fc12bd6dab20d1be7aa1c
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2151092
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There were following stale hw header files as their source script
changes were not present. These still had the static inline
functions.
Deleted below files as they are not used:
gk20a/hw_pri_ringstation_fbp_gk20a.h
gp106/hw_gc6_gp106.h
Regenerated with updated script changes:
gv11b/hw_usermode_gv11b.h
JIRA NVGPU-3733
Change-Id: I40b79b43b7f085c01858f3584fcf2c8928d62d13
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152825
GVS: Gerrit_Virtual_Submit
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MISRA Advisory Rule 2.3 states that a project should not contain
unused type declarations.
The justification for this rule is that a code reviewer may not
know if such a declaration was left behind inadvertently.
The nvgpu deviation record for Advisory Rule 2.3 states that no such
violations will remain that fit this description.
This change removes several unreferenced typedefs so that this
requirement is met.
JIRA NVGPU-3798
Change-Id: I852b5d1fe8d6beb12e6b93219e3101d806a88a39
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150415
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule 8.6 requires that an identifier with external linkage
shall have exactly one external definition. Fix violation of
Rule 8.6 in kmem unit by moving the prototype of fault injection
related function under respective define.
Jira NVGPU-3293
Change-Id: Iac7099fb4a6e396b97edd1ef10b8dfca3c5df760
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152166
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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Fix MISRA errors in hal/mm/gmmu/gmmu_gp10b_fusa.c
Rule 10.6 forbids assignment of u32 expression to u64 target.
This patch fixes this rule by casting the expression to u64.
Rule 20.6 doesn't allow use of preprocessor directives within a macro.
To resolve this patch moves the preprocessor directive before the macro
function call.
Jira NVGPU-3806
Change-Id: Ib7ddf746c801be62d3dd90a6ab7e27c690a60dc6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152065
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Add BLCG and SLCG clock gating support for HSHUB unit on gv11b and tu104
Register list for BLCG and SLCG is auto generated with scripts.
Add HAL operations to enable/disable HSHUB clock gating
Re-generate gv11b reglist so that all the manually commented registers
are automatically deleted. Some of the unicast registers are also
deleted. We already have corresponding broadcast registers present.
Bug 2526212
Change-Id: I2654f158daa802bcf992e103ed4a44675aa5fd4d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150199
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Using functional macros instead of static inline functions for defining
hw registers, fields, constants etc lets us not compile the dead code
in the build (non-gv11b for igpu safety build for instance).
This patch updates the all nvgpu hw headers to use define_style instead
of inline_style.
JIRA NVGPU-3733
Change-Id: I2d5d596fcfa0a75ce09444edad0a8c2851ee00dc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150879
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
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VBIOS version is only available if dGPU has already been
powered on. Make sure dGPU is powered-on before accessing
VBIOS version information.
Bug 200528528
Change-Id: I80915d61245a622f7d5273c5fbddb03cc22885e2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150447
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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A number of HAL files have been split between FUSA and non-FUSA in a
previous patch. Now this patch remove the un-needed HAL source files
from the FUSA build (host unit test, target unit test and QNX)
JIRA NVGPU-3690
Change-Id: Ic82513d06491f16ad8c512289bff7daa55694fe5
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2147806
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