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372 Commits

Author SHA1 Message Date
Alex Waterman
3f05901828 Revert "gpu: nvgpu: clear pbdma intr after recovery" 
This reverts commit 6554696006.

Change-Id: Ifd86f0d75e309c3593b69cdd042e6cb49a1c53bc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125117
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
 2019-05-24 13:32:04 -07:00
Peng Liu
6554696006 gpu: nvgpu: clear pbdma intr after recovery 
pbdma fault recovery function reads pbdma status info to retrieve
channel id, tsg id and engine id. pbdma interrupts can only be cleared
after that information has been read otherwise because pbdma exits
from stall state, channel/tsg/engine could have changed and fault
recovery function reads information different from that when interrupt
is issued.

Bug 2123866

Change-Id: Ia0e0462ae02ec89a333c81bd933a74fbae8ae1e7
Signed-off-by: Peng Liu <pengliu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123774
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-24 10:05:42 -07:00
Vinod G
dfb23f0b20 gpu: nvgpu: Fix CERT-C errors in hal.gr.config unit 
Fix CERT-C errors in hal.gr.config unit.

cert_violation: Unsigned integer operation may wrap.

Add safe_ops macros for addition, subtraction and multiplication
which do the wrap checks.

Jira NVGPU-3408

Change-Id: I9b0993a4c7b698f57ce03d9ebf277de2dc58c334
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124450
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-23 23:36:32 -07:00
Sagar Kamble
08add88e1d gpu: nvgpu: remove dgpu hal and sw from the safety build 
Since dGPU support is not required for initial safety release, compile
out dGPU sw and hal implementations except below files that are used
by gv11b currently: acr_sw_gv100.c, engine_status_gv100.c, gr_gv100.c
gr_config_gv100.c and hwpm_map_gv100.c.

JIRA NVGPU-3062

Change-Id: I8a6bc8b235e7e5eac5b0e76147b8bd12f9abbd2d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119586
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2019-05-23 10:07:31 -07:00
Sagar Kamble
17607e6bc9 gpu: nvgpu: remove sec2 from the safety build 
Since dGPU support is not required for initial safety release, disable
features from dGPU. Remove sec2 to start.

JIRA NVGPU-3062

Change-Id: I4448ab0fde603bc749dfdec5646308490971e18f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119585
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2019-05-23 10:07:22 -07:00
Sagar Kamble
96268cb631 gpu: nvgpu: disable nvlink support in safety build 
Since nvlink support is not required for initial safety release, disable
corresponding functionality.
nvgpu_mss_nvlink_init_credits defn. and call is now compiled out using
CONFIG_TEGRA_NVLINK config option.

JIRA NVGPU-3062

Change-Id: I402ed123f07f96125d640fb340957da4828d714a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119584
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2019-05-23 10:07:12 -07:00
Debarshi Dutta
47dc0b9ebd gpu: nvgpu: move chip specific channel HAL files to hal/fifo/ 
Moved the channel HAL files from common/fifo/ to hal/fifo

Jira NVGPU-3248

Change-Id: Ibb85b7c0e71422dbd774a518e4f0bba0b97ef807
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123399
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2019-05-23 02:19:47 -07:00
Mahantesh Kumbar
3d1169544f gpu: nvgpu: alloc space for PMU's struct nvgpu_pmu at runtime 
Allocating space for struct nvgpu_pmu at run time as part of
nvgpu_pmu_early_init() stage and made required changes to
dependent fiels as needed.

JIRA NVGPU-1972

Change-Id: I2d1c86d713e533c256ba95b730aa2e9543a66438
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110109
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2019-05-23 00:56:55 -07:00
Mahantesh Kumbar
0a64f6cb2d gpu: nvgpu: PMU pmu.c/h header include cleanup 
Some headers are not required to include in pmu.c/h as
lot of PMU code restructure happened, so removed headers
which not required anymore.

JIRA NVGPU-1972

Change-Id: Iead7f049d167cdaaaf7c75c2a5e19ae7b068fe6b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110108
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2019-05-23 00:56:45 -07:00
Seshendra Gadagottu
4992baf104 gpu: nvgpu: fix CERT INT30-C in hal.gr.falcon 
Fixed CERT INT30-C violations in hal gr falcon driver
by using nvgpu_safe ops for u32 arithmetic operations.

JIRA NVGPU-3413

Change-Id: I91bb143f89177eb25e4d6e00a6c042f65266ce6d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123821
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2019-05-22 17:54:59 -07:00
Vinod G
5ab6f3a593 gpu: nvgpu: Fix CERT INT30-C errors in gr.intr unit 
Fix CERT INT30-c errors in gr.intr unit.

cert_violation: Unsigned integer operation may wrap.

Use nvgpu_safe_ops macros for addition

Jira NVGPU-3412

Change-Id: I49d08318fde54d4de36501b8ea2a413edd0f30ff
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123051
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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 2019-05-22 10:46:58 -07:00
Antony Clince Alex
b60dca5e0a gpu: nvgpu: fix MISRA violations in clk frequency macros 
- Fix Misra rule 20.7: Macro parameter expands into an expression without being
  wrapped by parentheses.
- Following two macros has been updated to fix the above violation,
  HZ_TO_MHZ_ULL and MHZ_TO_HZ_ULL.

Jira NVGPU-3176

Change-Id: I03f7d8f7d5c91ca33fcc594fed0359d5c62eea6b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120192
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2019-05-22 10:46:30 -07:00
Vaibhav Kachore
854e861ad0 gpu: nvgpu: fix CERT-C violations 
This patch fixes following CERT-C violations for power management unit:
- CERT INT31-C

NVGPU-3403

Change-Id: I4eb2374cc720c6d0bb81d6a4d9750348d4e5a670
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117659
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2019-05-22 03:16:56 -07:00
Seshendra Gadagottu
9ea398d956 gpu: nvgpu: fix CERT INT30-C in hal.gr.falcon 
Fixed CERT INT30-C violations in hal gr falcon driver
by using nvgpu_safe_add_u32 and nvgpu_safe_sub_u32
for u32 arithmetic operations.

JIRA NVGPU-3413

Change-Id: I3f39792a668bf1af66cd522c005573aea6ad0f6a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122491
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2019-05-21 16:25:58 -07:00
Vinod G
cd02e4d70f gpu: nvgpu: Fix CERT INT30-C errors in gr intr unit 
Fix CERT INT30-C error in gr interrupt units

cert_violation: Unsigned integer operation may wrap.

Use nvgpu_safe_ops macros for addition and subtraction.

Jira NVGPU-3412

Change-Id: Id2d936e77959005616faf069aff6701789342456
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122474
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-21 15:15:59 -07:00
Vinod G
d652c16fa3 gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.init unit 
Add fixes for CERT INT30-C errors in hal.gr.init unit

cert_violation: Unsigned integer operation may wrap.

Use safe_ops macros to perform addition, subtraction, multiplication
and u64 to u32 casting

Jira NVGPU-3411

Change-Id: Ib7d472c7a5903263ab50c2769387f2a68bf7c695
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122289
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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 2019-05-21 15:15:50 -07:00
Vinod G
1f85c3190b gpu: nvgpu: Fix CERT INT31-C errors in hal.gr.init 
Fix CERT INT31-C errors in hal.gr.init unit.
cert-violation: Casting "array_size" from "unsigned long" to "int"
without checking its value may result in lost or misinterpreted data.

Use nvgpu_safe_cast_u64_to_u32 macro to covert size_t to u32

Jira NVGPU-3411

Change-Id: Ib160e43af683d5ca6a1cc86c4b9ee3322ddc971d
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119847
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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 2019-05-21 15:15:41 -07:00
Deepak Nibade
dfdd05a3d6 gpu: nvgpu: disable fecs trace support for safety builds 
Compile all files with fecs trace support only if flag
NVGPU_FECS_TRACE_SUPPORT is set

remove CONFIG_GK20A_CTXSW_TRACE checks from within the files

add POSIX file for fecs trace support for compilation with
make command

Jira NVGPU-3414

Change-Id: I205e3494ce94138ab6c6fccf7fbcefc41f953c77
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120276
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-21 10:36:04 -07:00
Debarshi Dutta
f39a5c4ead gpu: nvgpu: rename gk20a_channel_* APIs 
Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.

Jira NVGPU-3248

Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-21 09:26:16 -07:00
Nitin Kumbhar
1bf55ec715 gpu: nvgpu: rename secure ops to safe ops 
Change secure_ops.h to safe_ops.h and rename unsigned
type operations from nvgpu_secure_* to nvgpu_safe_*.

NVGPU-3432

Change-Id: I395896405ee2e4269ced88f251b097c5043cdeef
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122571
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2019-05-21 04:37:57 -07:00
Deepak Nibade
646b08a032 gpu: nvgpu: add flag for fecs trace support in rest of the units 
Add CONFIG_GK20A_CTXSW_TRACE flag for fecs trace support in rest of
the units like common.gr.utils and common.hal.gr.ctxsw_prog

Jira NVGPU-3414

Change-Id: I8f56bc38defd49a5fc30f79a35047afa7db2ffdf
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120277
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-20 15:46:30 -07:00
Nitin Kumbhar
4c2cee1429 gpu: nvgpu: fix ctxsw_prog CERT-C INT violations 
Error: CERT INT31-C:
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c:281:
cert_violation: Casting "ts >> 32" from "unsigned long long" to
 "unsigned int" without checking its value may result in lost
 or misinterpreted data.

Error: CERT INT31-C:
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c:186:
cert_violation: Casting "enable" from "bool" to "unsigned int"
 without checking its value may result in lost or misinterpreted data.

JIRA NVGPU-3410

Change-Id: I4879c8e09d8498bb2377b166035ae0e79adf8870
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119397
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2019-05-20 04:37:18 -07:00
Thomas Fleury
3f9ea7dfd8 gpu: nvgpu: enable MMU_DEBUG_MODE for gv11b 
NV_PGPC_PRI_MMU_DEBUG_CTRL is now context switched in gv11b
FECS ucode. Enable NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, so that
userspace can use NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE
ioctl for gv11b.

Bug 2515097

Change-Id: Ia9fb36cffc9e67cf96c31c50ffa4c59997258ce2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115019
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-17 12:55:06 -07:00
Seshendra Gadagottu
5fce81ea6d gpu: nvgpu: remove gr_priv.h dependnecy from hal gr falcon 
Removed gr_priv.h dependency in gr_falcon by using gr_utils.h
API for getting nvgpu_gr_falcon pointer.

JIRA NVGPU-3218

Change-Id: I4f02e8f76b13312b024ff95bf22019725fcf4c98
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120693
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-17 11:56:08 -07:00
Vaibhav Kachore
11630ad56f gpu: nvgpu: add support for TEGRA_VGPU_CMD_GET_TPC_EXCEPTION_EN_STATUS 
This patch adds support for TEGRA_VGPU_CMD_GET_TPC_EXCEPTION_EN_STATUS
in vgpu.

Bug 2555113

Change-Id: I9c822e09e1b4ec84ccaa3110b6f500b26eec6490
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118328
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-17 06:36:33 -07:00
Debarshi Dutta
4c30bd599f gpu: nvgpu: rename tsg_gk20a*/gk20a_tsg* functions. 
rename the functions with the prefixes tsg_gk20a*/gk20a_tsg*
to nvgpu_tsg_*

Jira NVGPU-3248

Change-Id: I9f5f601040d994cd7798fe76813cc86c8df126dc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120165
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-17 01:49:27 -07:00
Seshendra Gadagottu
b2980b0c22 gpu: nvgpu: fix MISRA 10.3 issues in hal.ltc 
Change following ltc hal prototype from:
int (*determine_L2_size_bytes)(struct gk20a *gk20a);
to
u64 (*determine_L2_size_bytes)(struct gk20a *gk20a);

JIRA NVGPU-3422

Change-Id: I53cbd7f37cad3c6851e3c5b46af6cdc04013d690
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119996
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-16 16:26:22 -07:00
Seshendra Gadagottu
80adcd99e8 gpu: nvgpu: fix MISRA 10.6 in hal ltc driver 
Fixes issues related to MISRA 10.6 in hal ltc driver.

JIRA NVGPU-3422

Change-Id: Ic2ebd879d35619a92d7354490cff605ea22c43b0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119972
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 16:26:07 -07:00
Seshendra Gadagottu
71ec37ac46 gpu: nvgpu: Fix MISRA 13.5 in hal ltc driver 
Fixed 13.5 misra violation by moving nvgpu_timeout_expired_msg_impl
outside of while and added error value check.

JIRA NVGPU-3422

Change-Id: I49df330d005efd64be3b4914c0338dd41bfb5b70
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119971
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 16:25:58 -07:00
Seshendra Gadagottu
51a86f81bb gpu: nvgpu: fix MISRA 17.7 in hal ltc driver 
Add error check for return value from function nvgpu_timeout_init.

JIRA NVGPU-3422

Change-Id: Ie89f689539086c5990f0856022aa4e5c4099e190
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119970
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 16:25:49 -07:00
Seema Khowala
6f5cd4027c gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below functions
gk20a_enable_channel_tsg
gk20a_disable_channel_tsg

Rename
gk20a_disable_channel_tsg -> nvgpu_channel_disable_tsg
gk20a_enable_channel_tsg -> nvgpu_channel_enable_tsg

JIRA NVGPU-3388

Change-Id: I0c18c4a14a872cecb12ae3089da886be9da43914
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115211
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 16:25:22 -07:00
Vedashree Vidwans
54e179ddad gpu: nvgpu: fix MISRA 13.5 nvgpu.hal.nvlink 
MISRA rule 13.5 doesn't allow right-hand operand of logical && or ||
operator to have persistent side effects. The reason is right-hand
operand is executed or checked depending on the left-hand operand value.
That means side effects in the right-hand operand may or may not occur,
contrary to programmer's expectation. Hence, this rule is implemented to
avoid unexpected behavior.

This patch divides if condition with logical && operator to nested if
conditions to resolve this violation.

Jira NVGPU-3277

Change-Id: I9f4387d71427821278db6bbda2eb53bd4d8ea543
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119684
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 15:16:00 -07:00
Thomas Fleury
af2ccb811d gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl 
Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.

Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.

Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.

Bug 2515097

Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 15:15:18 -07:00
Philip Elcan
78c7e601f8 gpu: nvgpu: debug: fix MISRA 5.7 violation 
MISRA 5.7 requires tag names be unique. Rename the struct
gk20a_debug_output to nvgpu_debug_context to avoid name collision with
the function of the same name.

JIRA NVGPU-3346

Change-Id: I9566b9dc6a7d090e87d9a09f6b8faf688589fbbd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116877
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 11:57:32 -07:00
Thomas Fleury
99bdda5846 gpu: nvgpu: fix MISRA 21.2 violations in nvgpu.hal.mm.gmmu 
Renamed the following functions to fix MISRA 21.2 violations:
- __update_pte -> update_pte
- __update_pte_sparse -> update_pte_sparse

Jira NVGPU-3284

Change-Id: Ic2281254f362ca261ab66562a4160acd3bf7ebc2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119617
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 10:58:11 -07:00
Thomas Fleury
56718737d9 gpu: nvgpu: fix MISRA 15.7 violations in nvgpu.hal.mm.gmmu 
Refactored if / else statements in nvgpu.hal.mm.gmmu
to avoid "else if" with no terminating "else" statement.

Jira NVGPU-3284

Change-Id: Id0a5901f6e74ab1b6539f8b907a4e8fdf3c1396c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119616
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 10:58:01 -07:00
Thomas Fleury
8a9d329468 gpu: nvgpu: fix MISRA 10.3 violations in nvgpu.hal.mm.gmmu 
Fixed MISRA 10.3 violations by using explicit casts, and
changing essential types.

Jira NVGPU-3284

Change-Id: If16c09a5100a9437e3e22bc53a81d3d1687d5cb1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119615
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 10:57:52 -07:00
Thomas Fleury
16d98af02b gpu: nvgpu: fix MISRA 17.7 violations in nvgpu.hal.mm.mm 
Below MISRA 17.7 violations are reported in nvgpu.hal.mm.mm,
for nvgpu_timeout_init functions:
misra_c_2012_rule_17_7: The return value of a non-void function
"nvgpu_timeout_init" is unused.

Fix this by asserting that nvgpu_timeout_init is successful, since
it should never fail with NVGPU_TIMER_RETRY_TIMER flag.

Jira NVGPU-3283

Change-Id: I89a6afa5d024683a50dfa5dc277da7fe4a6478bb
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119606
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 21:35:43 -07:00
Thomas Fleury
62aa562cfb gpu: nvgpu: fix MISRA 16.x violations in nvgpu.hal.mm.mm 
MISRA mandates switch clauses to end with an unconditional break
statement. Refactor switch/case in gv100_mm_get_flush_retries
function to set retries in each clause, then return result
at the end of the function.

Refactoring of the switch/case solves MISRA 16.1, 16.3 and 16.6
violations.

Jira NVGPU-3314

Change-Id: Ie051a8f2df805b63a7bef6a55fea3ae011603a0e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118887
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-14 18:40:52 -07:00
Mahantesh Kumbar
25364895fd gpu: nvgpu: PMU RTOS fw init update 
Allocate space at runtime for PMU RTOS fw struct, this helps
to reduce the size of nvgpu_pmu struct when LS_PMU support
is not required.

Allocation happens at pmu early init stage & will deinit at
remove_support stage.

JIRA NVGPU-1972

Change-Id: I1452b085f8d3a76e12186f788c2d999a8b4b202d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111072
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 2019-05-14 04:56:34 -07:00
Mahantesh Kumbar
118381411a gpu: nvgpu: replace gk20a_from_pmu() with pmu->g 
removed gk20a_from_pmu() & used pmu->g to remove
circular dependency within PMU units.

JIRA NVGPU-1972

Change-Id: I5fd1eae30a81cea5a50dd04c1fdfdb7fd4d0e1b8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111071
GVS: Gerrit_Virtual_Submit
Reviewed-by: Abdul Salam <absalam@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-14 04:56:18 -07:00
Seema Khowala
f453f66fc4 gpu: nvgpu: fifo MISRA fix for Rule 15.7 
Add terminating else statement

JIRA NVGPU-3383

Change-Id: I3ceb15de502d3927452713765a83076837904624
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115899
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-13 14:11:13 -07:00
Seema Khowala
50d4421dc2 gpu: nvgpu: fifo MISRA fix for Rule 10.3 
JIRA NVGPU-3383

Change-Id: Ic1b30cd4b8c5dba0ea75ff0de316d0d5dcc99ae4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116730
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-13 14:10:57 -07:00
Seema Khowala
7054643749 gpu: nvgpu: fifo MISRA fix for Rule 10.3 
JIRA NVGPU-3383

Change-Id: Ice279ee436b1f54c3aa2279f1129aa6de11f1315
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115860
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-13 14:10:47 -07:00
Seema Khowala
42c2ea552d gpu: nvgpu: fifo MISRA fix for Rule 10.1 
JIRA NVGPU-3383

Change-Id: I18ab3ebd4728ff798c0cc47f6cb84d1dda225b53
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116729
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-13 14:10:37 -07:00
Rajesh Devaraj
8090e2d5eb gpu: nvgpu: report PFIFO CTXSW timeout error 
During code review, it has been found that PFIFO CTXSW timeout error related
callback has been removed while restructuring PFIFO unit. Hence, we are
introducing the callback to report PFIFO CTXSW timeout error to 3LSS.

Jira NVGPU-3439

Change-Id: I3c4b9a25215fb7692470ac43f0ea8fc21720c376
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115186
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-12 21:45:20 -07:00
Vinod G
5c60645cfa gpu: nvgpu: gr_priv header include cleanup 
Add more apis in gr_utils for accessing variables within gr struct.
This helps to avoid including gr_priv.h outside gr files and
derefencing gr struct.

Jira NVGPU-3218

Change-Id: I6f24cc302f10aa1da14a981d80c400a027c9a115
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115930
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 2019-05-10 20:15:36 -07:00
Vinod G
e615e8f0ff gpu: nvgpu: gr/init MISRA fixes for Rule 10.3 
Fix MISRA violations for Rule 10.3 in gr.init unit
Implicit conversion from essential type "unsigned 64-bit int"
to different or narrower essential type "unsigned 32-bit int"

Jira NVGPU-3389

Change-Id: I00bc876f271242a513371477c781e78b2ee42b6a
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116733
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-10 19:05:25 -07:00
Seshendra Gadagottu
76aac6b183 gpu: nvgpu: MISRA 21.6 fixes in hal netlist 
Use strcpy/strcat instead of sprintf to fix MISRA 21.6
violations.

JIRA NVGPU-3420

Change-Id: I70314bc9b407370961bd46434bb355ebb8d1df7d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115925
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-10 13:21:25 -07:00
Seshendra Gadagottu
62a7fde536 gpu: nvgpu: MISRA 16.x fixes for hal netlist 
Fixes issues with switch formatting and missing break statements
in hal netlist driver.

JIRA NVGPU-3420

Change-Id: Iae59ac80d6f780cfc6144977f14e85e15dc53ace
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114896
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-10 13:20:31 -07:00