Move the get_litter() functions out of the main hal init to its own
source file for each device. This allows removal of the hw_proj_*.h
files in the main hal init file. This reduces the number of hw header
includes per file creating better code isolation.
JIRA NVGPU-3274
Change-Id: I9e04294434acf274ccc2236646f0f15f710a6976
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107751
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create a new unit common.fbp which initializes fbp support and provides
APIs to retrieve fbp data.
Create private header with below data
struct nvgpu_fbp {
u32 num_fbps;
u32 max_fbps_count;
u32 fbp_en_mask;
u32 *fbp_rop_l2_en_mask;
};
Expose below public APIs to initialize/remove fbp support:
nvgpu_fbp_init_support()
nvgpu_fbp_remove_support()
vgpu_fbp_init_support() for vGPU
Expose below APIs to retrieve fbp data
nvgpu_fbp_get_num_fbps()
nvgpu_fbp_get_max_fbps_count()
nvgpu_fbp_get_fbp_en_mask()
nvgpu_fbp_get_rop_l2_en_mask()
Use above APIs to retrieve fbp data in all the code.
Remove corresponding fields from struct nvgpu_gr since they are no
longer referred from that structure
Jira NVGPU-3124
Change-Id: I027caf4874b1f6154219f01902020dec4d7b0cb1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108617
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA Rule 13.5 mandates that the right hand operand of a
logical && or || operator does not contain persistent side effects.
Removed use of nvgpu_readl from the if condition.
Jira NVGPU-3378
Change-Id: Ia5d7c083d6827f8a7db152757e683a4a06418b21
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109477
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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channel.c calling nvgpu_gr_flush_channel_tlb() creating circular
dependency between gr and fifo. Avoid this by moving channel tlb
related data to struct nvgpu_gr_intr in gr_intr_priv.h and
initialized this data in gr_intr.c.
Created following new gr intr hal and called this new hal from channel.c
void (*flush_channel_tlb)(struct gk20a *g);
JIRA NVGPU-3214
Change-Id: I2d259bf52db967273030680f50065af94a17f417
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109274
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Remove gr_priv.h from outside gr files.
Add hal function in gr.init for get_no_of_sm. This helps
to avoid dereferencing gr in couple of files for g->gr->config and
avoid gr_priv.h include in those files.
Replace nvgpu_gr_config_get_no_of_sm call with
g->ops.gr.init.get_no_of_sm for files outside gr unit.
Jira NVGPU-3218
Change-Id: I435bb233f70986e31fbfcb900ada3b3bda0bc787
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109182
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There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.
Much of this is fairly straightforward copy/paste and updates to the
HAL init files.
The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.
JIRA NVGPU-2042
Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
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The alloc_insty_block() function in the MM HAL is not a HAL. It does
not abstract any HW accesses; instead it just wraps a dma allocation.
As such remove it from the HAL and move the single gk20a implementation
to common/mm/mm.c as nvgpu_alloc_inst_block().
JIRA NVGPU-2042
Change-Id: I0a586800a11cd230ca43b85f94a35de107f5d1e1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109049
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- Create nvlink_bios.c/.h files to separate out nvlink
related bios code.
- Create bios_sw_<chip speciific>.c/.h files to separate
out chips specific bios code.
- Create hal files for bios under hal/bios/ and move
hardware specific code there.
- Move hardware accessing hal files from common/top
to hal/top
JIRA NVGPU-2071
Change-Id: Ia466f1cd8947540b07b237e891312123df2c6b46
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107371
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Move remaining chip specific gr hal files to hal.gr.gr unit.
Remove unused headers include from hal files in hal.gr.gr unit
Update gr hal headers include location in the files currently
using these headers.
Jira NVGPU-3219
Change-Id: Ic632020a90ac4b8ac1e0359e979864b42f0ef2c0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105489
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gk20a_pmu_isr & gk20a_pmu_bar0_error_status CCM values were higher than
10. Address by prepared function gk20a_pmu_handle_interrupts for sub-
task. Prepare functions for getting the etypes for various pmu bar0
errors.
JIRA NVGPU-3194
Change-Id: I83239d97a264e04bea6f736155ccde664df537fe
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101945
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Renamed
- gk20a_tsg_set_runlist_interleave -> nvgpu_tsg_set_interleave
Moved set_interleave from runlist to tsg
- runlist.set_interleave -> tsg.set_interleave
Existing HAL was only setting tsg->interleave, and was not
accessing any register. This is now done in nvgpu_tsg_set_interleave
and tsg.set_interleave is only used in vgpu case.
Jira NVGPU-3156
Change-Id: I5dac1305afcbd950214316289cf704ee8b43fc89
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100610
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Moved the following HALs from fifo to tsg
- set_timeslice
- default_timeslice_us
Renamed
- gk20a_tsg_set_timeslice -> nvgpu_tsg_set_timeslice
- min_timeslice_us -> tsg_timeslice_min_us
- max_timeslice_us -> tsg_timeslice_max_us
Scale timeslice to take into account PTIMER clock in
nvgpu_runlist_append_tsg.
Removed gk20a_channel_get_timescale_from_timeslice, and
instead moved timeout and scale computation into runlist HAL,
when building TSG entry:
- runlist.get_tsg_entry
Use ram_rl_entry_* accessors instead of hard coded values
for default and max timeslices.
Added #defines for min, max and default timeslices.
Jira NVGPU-3156
Change-Id: I447266c087c47c89cb6a4a7e4f30acf834b758f0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100052
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MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. This patch contains fixes for all 17.7 violations
in the following units:
- nvgpu.common.hal.pmu.perf
- nvgpu.common.hal.pmu.pmu
JIRA NVGPU-3152
Change-Id: I540eb87b1b441737d1683bb007b52f0c48313cb5
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099829
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Currently max_css_buffer_size is incorrectly stored in struct nvgpu_gr
Add a new hal g->ops.css.get_max_buffer_size() to get the size and
remove the variable from struct nvgpu_gr
Jira NVGPU-3125
Change-Id: If78fd86559526b84031051e281a98327a46fc11d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105652
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Move the gk20a_init_mm_setup_hw to common code. This function just
calls HALs to initialize various bits of HW. However, since this
code assumes that (some of) the HALs are present this code is treated
as a vGPU HAL (that is it's NULL for vGPU).
This patch also renames the MM HW init HAL.
Sicne the gv11b variant of this setup_hw HAL did have some differences
from the gk20a version the new common version required some work. The
gv11b code was copied into the common function but now the gv11b
specific calls were HAL'ified (since they will need to be anyway for
the MMU fault buf code) and protected by an if-condition.
JIRA NVGPU-2042
Change-Id: I959293394ee8793923d858ee37b7ce346096654f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104541
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This "HAL" exists to handle the vGPU specific bind channel operation.
This patch moves the native function implementation to common/mm/vm.c
and renames the gk20a to nvgpu to follow the convention for vGPU vs
native HAL functions.
JIRA NVGPU-2042
Change-Id: I02b9ebf0d53d58a6d2ede544e34f2b8ff1b1eb42
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104540
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Move the remaining GMMU HAL related code from the gm20b/, gp10b/,
and gv11b/ directories to new gmmu hal source files.
Also update all makefiles and HAL init code to refelct the new
location of the headers and source code.
JIRA NVGPU-2042
Change-Id: Ic9b85cc547bd0f994ad11042fc4093c517327399
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103672
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Moved nvgpu_clk_pmupstate structure from gk20a to
nvgpu_pmu.The aim is to have single pmu structure inside
gk20a, that is "nvgpu_pmu" struct and all the global
structures of all units in PMU should be included in
"nvgpu_pmu" struct.
NVGPU-3220
Change-Id: I531aab568a692c55e640ca2c33aa7508b83a9593
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104129
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MISRA rule 11.3 states that a cast shall not be performed between
a pointer to object type and a pointer to a different object type.
The following gr context routines convert a gr context buffer pointer
in the form of a u8 * to a u32 * before referencing the context buffer's
contents:
* gm20b_ctxsw_prog_check_main_image_header_magic
* gm20b_ctxsw_prog_check_local_header_magic
* gm20b_ctxsw_prog_get_num_gpcs
* gm20b_ctxsw_prog_get_num_tpcs
* gm20b_ctxsw_prog_get_extended_buffer_size_offset
* gm20b_ctxsw_prog_get_ppc_info
* gm20b_ctxsw_prog_get_local_priv_register_ctl_offset
Because the gr context buffer pointer starts out as a u32 * the
conversion to a u8 * isn't strictly necessary.
So this patch eliminates the conversion and the 11.3 rule violations
accordingly.
JIRA NVGPU-782
Change-Id: I0d24b539ad6ee8e56318287ce8640764285ed54d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102986
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Move chip specific recovery code for volta onwards
architecture to hal/rc/rc_gv11b.c
Rename
fifo.teardown_ch_tsg -> fifo.recover
gk20a_runlist_update_locked -> nvgpu_runlist_update_locked
Remove
Unused h/w headers from fifo_gv11b.c
Use local variable f instead of g->fifo
JIRA NVGPU-1314
Change-Id: Ia535bbe4780e7241fdd911a8f577c6b98cf0fe53
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102897
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gr_gk20a.ctx_vars struct right now stores sizes for golden_image, zcull,
pm_ctxsw, and gfxp_preemption_buffer.
but these sizes should be really owned by respective units and should
be assigned to units as soon as they are queried from FECS
Add new structure to nvgpu_gr_falcon to hold sizes that will be queried
from FECS
struct nvgpu_gr_falcon_query_sizes {
u32 golden_image_size;
u32 pm_ctxsw_image_size;
u32 preempt_image_size;
u32 zcull_image_size;
};
gr.falcon unit now queries sizes from FECS and fills this structure.
gr.falcon unit also exposes below APIs to query above sizes
u32 nvgpu_gr_falcon_get_golden_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_pm_ctxsw_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_preempt_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_zcull_image_size(struct nvgpu_gr_falcon *falcon);
gr.gr unit now calls into gr.falcon unit to initailize sizes, and then
uses above exposed APIs to set sizes into respective units
vGPU will too fill up struct nvgpu_gr_falcon_query_sizes with all the sizes
and then above APIs will be used to set sizes into respective units
All of above means size variables in gr_gk20a.ctx_vars struct are no more
being referred. Delete them.
Jira NVGPU-3112
Change-Id: I8b8e64ee0840c3bdefabc8ee739e53a30791f2b3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103478
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struct gr_gk20a defines boolean flag golden_image_initialized to
indicate if golden_image is initialized or not
common.gr.obj_ctx also added a flag of its own to check if golden_image
is ready
Add new API nvgpu_gr_obj_ctx_is_golden_image_ready() in
common.gr.obj_ctx unit to get status of golden_image
Use this new API everywhere to check if golden image is ready
Remove g->gr.ctx_vars.golden_image_initialized
Also remove ctx_mutex from struct gr_gk20a
Add new flag golden_image_initialized to struct nvgpu_pmu_pg and set it
when golden image is initialized. This is needed to avoid circular
dependency between GR and PMU
Jira NVGPU-3112
Change-Id: Id391294cede6424e15a9a9de29c40d013b509534
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099400
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Only one h/w header is allowed per hal file. ramfc_*.c uses both
hw_ramfc_*.h and hw_pbdma_*.h. The pbdma dependencies are removed from
the HAL unit of ramfc by constructing new HAL functions for pbdma unit.
The HAL ops functions added are listed below.
get_gp_base
get_gp_base_hi
get_fc_formats
get_fc_pb_header
get_fc_subdevice
get_fc_target
get_ctrl_hce_priv_mode_yes
get_userd_aperture_mask
get_userd_addr
get_userd_hi_addr
get_fc_runlist_timeslice
get_config_auth_level_privileged
set_channel_info_veid
config_userd_writeback_enable
allowed_syncpoints_0_index_f
allowed_syncpoints_0_valid_f
allowed_syncpoints_0_index_v
These HAL ops uses the following new implementations.
gm20b_pbdma_get_gp_base
gm20b_pbdma_get_gp_base_hi
gm20b_pbdma_get_fc_formats
gm20b_pbdma_get_fc_pb_header
gm20b_pbdma_get_fc_subdevice
gm20b_pbdma_get_fc_target
gm20b_pbdma_get_ctrl_hce_priv_mode_yes
gm20b_pbdma_get_userd_aperture_mask
gm20b_pbdma_get_userd_addr
gm20b_pbdma_get_userd_hi_addr
gp10b_pbdma_get_fc_runlist_timeslice
gp10b_pbdma_get_config_auth_level_privileged
gp10b_pbdma_allowed_syncpoints_0_index_f
gp10b_pbdma_allowed_syncpoints_0_valid_f
gp10b_pbdma_allowed_syncpoints_0_index_v
gv11b_pbdma_get_fc_pb_header
gv11b_pbdma_get_fc_target
gv11b_pbdma_set_channel_info_veid
gv11b_pbdma_config_userd_writeback_enable
Jira NVGPU-3195
Change-Id: I849f16650046eca38c67b0d6e0e43cd2ab1ac224
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102576
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Created PMU fw unit to hold PMU RTOS f/w specific ops, images,
flags & command arguments needed for PMU RTOS ucode support.
Moved PMU fw ops from gk20a.gpu_ops to pmu.fw.ops as these ops
are needed to support different version of PMU fw version for
different chips
JIRA NVGPU-1955
Change-Id: I51385d8c20524431f07cba3378676464663deb20
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090769
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