The type for the timeout parameter to the NVGPU_COND_WAIT and
NVGPU_COND_WAIT_INTERRUPTIBLE macros was too weak. This updates these
macros to require a u32 for the timeout.
Users of the macros are updated to be compliant as necessary.
This addresses MISRA 10.3 violations for implicit conversions of types
of different size or essential type.
JIRA NVGPU-1008
Change-Id: I12368dfa81b137c35bd056668c1867f03a73b7aa
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017503
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FECS ucode does a priv holdoff around the assertion of context
reset. So, priv transactions (e.g. mailbox1 register write) might
fail due to this. Hence, do write with ack i.e. write and read
it back to make sure write happened for mailbox1.
Bug 200417403
Change-Id: I463be1cb8fdd477106b87786cb0603327a22cebe
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2023494
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Add zbc stencil as chip feature. This help to remove the
hals added for stencil feature, instead use common functions.
Removed hals
stencil_query_table
load_stencil_default_tbl
add_type_stencil
load_stencil_tbl
JIRA NVGPU-1882
Change-Id: Iae410a8dd879660ecfd2d2a5ebf28b2cc8309be4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022385
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Create new gr/fecs_trace unit with common/gr/fecs_trace/fecs_trace.c
as common source file and include/nvgpu/gr/fecs_trace.h as common
header file
This unit will be common between Linux and QNX
Corresponding HAL files will be added under common/gr/fecs_trace/
as more functionality is moved to new unit
For now move struct gk20a_fecs_trace_hash_ent to new unit and
rename it as struct nvgpu_fecs_trace_context_entry
Add vmid field to this struct since it is required for QNX
Remove use of hashtables and simply use linked list to simplify
the code. FECS tracing is not a performance sensitive use case
so perf hit could be ignored
Rename hash_lock mutex to list_lock
struct gk20a_fecs_trace and mutex list_lock are still declared in
gk20a/fecs_trace_gk20a.c, hence they cannot be used in new unit yet
Rename and update all gk20a_fecs_trace_hash_*() APIs to appropriate
nvgpu_gr_fecs_trace_*() APIs
Remove gk20a_fecs_trace_hash_dump() since it is not being used
Jira NVGPU-1880
Change-Id: I89c2715baa770dbbd864ea70ab43d83d98ba693c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022903
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gk20a_fecs_trace_poll() right now calls gk20a_fecs_trace_ring_read()
to read the trace ring buffer written by FECS
gk20a_fecs_trace_ring_read() returns number of trace entries written
to local buffer if successful, otherwise returns error
In case there is really an invalid entry, gk20a_fecs_trace_poll()
will just stop reading more entries, write current read pointer to
h/w and return
When gk20a_fecs_trace_poll() is called next time, we again read that
invalid entry, and again skip it, and again return
This keeps happening, and we never move on to read new entries
Fix this by always continuing to read next entry irrespective
of current entry is valid or not
gk20a_fecs_trace_poll() now just prints a debug message instead of
breaking the loop
Bug 200491708
Change-Id: I8cf823d7dc5f72ebd70cab2f115af32f3d20ac78
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2020167
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Renamed gr_gk20a zbc hal functions which involve register access as
gk20a_gr_zbc* hal functions.
gr_gk20a_add_zbc_color -> gk20a_gr_zbc_add_color
gr_gk20a_add_zbc_depth -> gk20a_gr_zbc_add_depth
gr_gk20a zbc hal functions without any register access are renamed as
common function as nvgpu_gr_zbc*
gk20a_gr_zbc_set_table -> nvgpu_gr_zbc_set_table
gr_gk20a_query_zbc -> nvgpu_gr_zbc_query_table
Renamed gr_gp10b zbc hal functions as gp10b_gr_zbc* hal functions.
gr_gp10b_add_zbc_color -> gp10b_gr_zbc_add_color
gr_gp10b_add_zbc_depth -> gp10b_gr_zbc_add_depth
gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg ->
gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg
gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg ->
gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg
common code added for nvgpu_gr_zbc_add_color and
nvgpu_gr_zbc_add_depth which update ltc, update local copy
and call add_color or add_depth hal function
All these functions will be moved to common/gr/zbc location
in future updates.
gk20a_writel replaced with nvgpu_writel function.
JIRA NVGPU-1882
Change-Id: I717739e0b20c243e8f5ed3e00f8f76755587bcee
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018737
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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As part of creating zbc as gr subunit, move pmu_save hal function
from zbc to pmu hal.
This hal function is used to pass the information to gpmu
firmware, which should reside as part of pmu.
remove pmu_save hal from zbc.
add save_zbc hal under pmu.
remove unused function gr_gk20a_pmu_save_zbc
JIRA NVGPU-1882
Change-Id: I132dbc7a9ee9755043cd08f288344df447e28af6
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018581
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nvgpu driver uses the h/w headers for reading pbdma_status registers
directly in the common code path. Replace the use of the H/W headers by
using the APIs of the pbdma_status unit. Use the HAL ops functions
read_pbdma_status_info() to do a read of the pbdma status register.
Jira NVGPU-1311
Change-Id: I4b492e675ce2561bb1e132b518023f9933d8c510
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019977
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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The following changes are done in this patch.
1) gk20a_fifo_get_engine_info() is moved to common/fifo/engine.c
and is renamed to gk20a_fifo_get_active_engine_info() to reflect
accurately the purpose of the function.
2) move the definition of enum fifo_engine to <nvgpu/engines.h> and
add the prefix NVGPU_
3) move the following functions related to engines in fifo_gk20a.c to
common/fifo/engines.c and replace their signature by adding the prefix
nvgpu_engine and removing gk20a_fifo.
gk20a_fifo_get_active_engine_info
gk20a_fifo_engine_enum_from_type
gk20a_fifo_get_engine_ids
gk20a_fifo_is_valid_engine_id
gk20a_fifo_get_gr_engine_id
gk20a_fifo_act_eng_interrupt_mask
gk20a_fifo_engine_interrupt_mask
gk20a_fifo_get_all_ce_engine_reset_mask
Jira NVGPU-1315
Change-Id: I63d9dcd905a0bebcc9a4c65776cf6ec7a0837acf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011298
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Drop the "runlist_" part in the runlist section of the HAL ops. For
example:
- old: g->ops.runlist.runlist_wait_pending
- new: g->ops.runlist.wait_pending
At the same time, drop the "fifo_" part from the function names. For
example:
- old: gk20a_fifo_runlist_wait_pending
- new: gk20a_runlist_wait_pending
Also rename eng_runlist_base_size to count_max. The size of the
eng_runlist_base register array depicts the maximum possible number of
runlists in the chip for which count_max is more descriptive.
Jira NVGPU-1309
Change-Id: Ie9e94b9f65cd10d3e682d19954f240adb6e311be
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017403
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Refactor read accesses to the ccsr_channel register for channel state to
be done via a channel HAL op for all chips. A new op called read_state
is added for this; information needed by other units is collected in a
new struct nvgpu_channel_hw_state.
Jira NVGPU-1307
Change-Id: Iff9385c08e17ac086d97f5771a54b56b2727e3c4
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017266
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Extract out the HAL ops' implementation that now belongs to the channel
unit. This unit is responsible for channel register accesses and the
like (ccsr_*).
Rename channel_gm20b_bind to gm20b_fifo_channel_bind to match with the
rest of the naming. Same with channel_gv11b_unbind.
Jira NVGPU-1307
Change-Id: I58b9d96dbdaf36bdb163a5729544a41faec828ab
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017262
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Split out ops that belong to channel unit to a new section called
channel. Channel is a broad concept; this includes just the code that
accesses channel registers (ccsr_*). This is effectively just renaming;
the implementation still stays put.
The word "channel" is also dropped from certain HAL entries to avoid
redundancy (e.g., channel.disable_channel -> channel.disable).
fifo.get_num_fifos gets an entirely new name: channel.count.
Jira NVGPU-1307
Change-Id: I9a08103e461bf3ddb743aa37ababee3e0c73c861
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017261
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Make the APIs nvgpu_channel_sync_get_syncpt_id() and
channel_sync_syncpt_get_id() return u32s rather than converting to
ints and back.
Also define FIFO_INVAL_SYNCPT_ID to use for invalid syncpt IDs rather
than using magic numbers.
JIRA NVGPU-1008
Change-Id: I4dde6b15fd3708fb0126b46c6fea8ac1b447c7ce
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014821
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In __gr_gk20a_exec_ctx_ops(), we right now call gr_gk20a_ctx_patch_smpc()
even if operations are on pm_ctx image which is incorrect since this is
only required for SMPC operations on main context image
Fix this by not calling gr_gk20a_ctx_patch_smpc() for pm_ctx image
Jira NVGPU-1527
Jira NVGPU-1613
Change-Id: I5111fb0e6ea1f329750b42a37a98f5c006b47deb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011095
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gr_gk20a_update_hwpm_ctxsw_mode() right now validates the incoming
hwpm mode, checks if it is already set, and if not, it will go ahead
and set the new hwpm mode by calling g->ops.gr.ctxsw_prog HALs
Instead of programming hwpm mode in gr_gk20a.c, move the programming
to gr/ctx and gr/subctx units by adding below APIs
nvgpu_gr_ctx_prepare_hwpm_mode() - validate the incoming mode and
check if it is already set
nvgpu_gr_ctx_set_hwpm_mode() - set pm mode in graphics context
nvgpu_gr_subctx_set_hwpm_mode() - set pm mode in subcontext
Add gpu_va field to struct pm_ctx_desc to store the gpu_va to be
programmed into context
Rename NVGPU_DBG_HWPM_CTXSW_MODE_* to NVGPU_GR_CTX_HWPM_CTXSW_MODE_*
and move them to gr/ctx.h
Remove below HALs since they are no longer used
g->ops.gr.ctxsw_prog.set_pm_mode_no_ctxsw()
g->ops.gr.ctxsw_prog.set_pm_mode_ctxsw()
g->ops.gr.ctxsw_prog.set_pm_mode_stream_out_ctxsw()
Jira NVGPU-1527
Jira NVGPU-1613
Change-Id: Id2a4d498182ec0e3586dc7265f73a25870ca2ef7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011093
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In gr_gk20a_ctx_zcull_setup(), we configure context/subcontext with
zcull details
This API now does it directly by calling g->ops.gr.ctxsw_prog HAL
Move all context/subcontext setup to gr/ctx and gr/subctx units
respectively
Define and use below new APIs for same
gr/ctx : nvgpu_gr_ctx_zcull_setup()
gr/subctx : nvgpu_gr_subctx_zcull_setup()
Jira NVGPU-1527
Jira NVGPU-1613
Change-Id: I1b7b16baea60ea45535c623b5b41351610ca433e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011090
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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A comment for gk20a_fifo_update_runlist() says:
/* add/remove a channel from runlist
special cases below: runlist->active_channels will NOT be changed.
(ch == NULL && !add) means remove all active channels from runlist.
(ch == NULL && add) means restore all active channels on runlist. */
Those special cases call for a new function, so add that. Delete the
update_runlist HAL op and add update_for_channel (like update_runlist
without the special cases) and reload (no channel to add or remove, just
the special cases).
While at it, rename gk20a_fifo_update_runlist_ids to
nvgpu_runlist_reload_ids. It's common across chips and does what the
reload HAL does but for a list of several IDs.
Jira NVGPU-1922
Change-Id: I9a99ab03a636a1214c021faad359d2b304a9472f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2013058
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Add new unit gr/config to initialize GR configuration like GPC/TPC
count, MAX count and mask
Create new structure nvgpu_gr_config that stores all the configuration
and that is owned by the new unit
Move below fields from struct gr_gk20a to nvgpu_gr_config in gr/config.h
Struct gr_gk20a now only holds the pointer to struct nvgpu_gr_config
u32 max_gpc_count;
u32 max_tpc_per_gpc_count;
u32 max_zcull_per_gpc_count;
u32 max_tpc_count;
u32 gpc_count;
u32 tpc_count;
u32 ppc_count;
u32 zcb_count;
u32 pe_count_per_gpc;
u32 *gpc_tpc_count;
u32 *gpc_ppc_count;
u32 *gpc_zcb_count;
u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC];
u32 *gpc_tpc_mask;
u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC];
u32 *gpc_skip_mask;
u8 *map_tiles;
u32 map_tile_count;
u32 map_row_offset;
Remove gr->sys_count since it was already no longer used
common/gr/config/gr_config.c unit now exposes the APIs to initialize
the configuration and also to query the configuration values
nvgpu_gr_config_init() is called to initialize GR configuration from
gr_gk20a_init_gr_config() and gr_gk20a_init_map_tiles() is simply
renamed as nvgpu_gr_config_init_map_tiles()
Expose new API nvgpu_gr_config_deinit() to deinit the configuration
Expose nvgpu_gr_config_get_*() APIs to query above configuration
fields stored in nvgpu_gr_config structure
Update vgpu_gr_init_gr_config() to initialize the configuration
from gr->config structure
Chip specific HALs that access GR register for initialization
are implemented in common/gr/config/gr_config_gm20b.c
Set these HALs for all GPUs
Jira NVGPU-1879
Change-Id: Ided658b43124ea61b9f273b82b73fdde4ed3c8f0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012167
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Add new unit common/gr/subctx.c to manage GR subcontext
This unit provides interfaces to allocate/free/load GR subcontext
Add new header file include/nvgpu/gr/subctx.h to declare all the
interfaces.
Right now channel_gk20a structure directly includes a nvgpu_mem
for context header.
Declare a new structure nvgpu_gr_subctx for subcontext and include
this from channel_gk20a
Make all necessary changes to refer ctx_header from subctx instead
of directly referencing it from channel
Jira NVGPU-1613
Change-Id: I9eb1ee8f26fa88d2881f9b294935b65e9cbcc9b4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990129
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When an engine faults due to unbound instance block, all
active TSGs are currently aborted. This includes the TSG
used by vidmem-clear task to clear vidmem buffers. From
this point nvgpu_vidmem_clear cannot submit jobs anymore.
Define TSG in MM CE context as non-abortable, and skip it
when aborting active TSGs.
Bug 2486146
Change-Id: I221259aec468e8ee3a24e80fab8d8fb7ee8607b0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008954
(cherry picked from commit 6f2444dc5e128aa2b870796bd1e9dee7853f90af)
Reviewed-on: https://git-master.nvidia.com/r/2008942
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- Remove handling for channels that are no more bound to tsg
as channel could be referenceable but no more part of a tsg
- Use tsg_gk20a_from_ch to get pointer to tsg for a given channel
- Clear unhandled gr interrupts
Bug 2429295
JIRA NVGPU-1580
Change-Id: I9da43a2bc9a0282c793b9f301eaf8e8604f91d70
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972492
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gv11b_mm_l2_flush was not checking error codes from the various
functions it was calling. MISRA Rule-17.7 requires the return value
of all functions to be used. This patch now checks return values and
propagates the error upstream.
JIRA NVGPU-677
Change-Id: I9005c6d3a406f9665d318014d21a1da34f87ca30
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1998809
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Add new hal to log the mme exception register information. Support
added for Turing only. On mme exception interrupt, read the
mme_hww_esr register and log the error based on esr register bits.
JIRA NVGPU-1241
Change-Id: Ied3db0cc8fe6e2a82ecafc9964875e2686ca0d72
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2005807
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A naked channel ID does not carry good information about the channel
validity and is a very low level construct for an API of this level.
Refactor the runlist updating fifo APIs to take a channel pointer.
While at it, delete the channel and wait_for_finish parameters from
gk20a_fifo_update_runlist_ids() - the only caller is suspend and resume
and the parameters were always null for channel and true for wait.
Jira NVGPU-1309
Jira NVGPU-1737
Change-Id: Ied350bc8e482d8e311cc708ab0c7afdf315c61cc
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1997744
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sema cmdbuf specific functions are only for the sync functionality
of nvgpu and do not belong to fifo.
construct files sema_cmdbuf_gk20a.h and sema_cmdbuf_gk20a.c
under common/sync to contain the syncpt specific cmdbuf functions
for arch gk20a.
Jira NVGPU-1308
Change-Id: Iebeebe7a3de627f2de08d4ced74bb1aabf1eb53c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975922
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syncpt cmdbuf specific functions are only for the sync functionality of
nvgpu and donot belong to fifo.
construct files syncpt_cmdbuf_gk20a.h and syncpt_cmdbuf_gk20a.c under
common/sync to contain the syncpt specific cmdbuf functions for arch
gk20a.
The word 'fifo' is also removed from the name of these functions.
Jira NVGPU-1308
Change-Id: I1a1fd1d31f7decd1398f8e2ff625f95cf1f55033
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975920
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The function gk20a_fifo_set_runlist_state was moved to another place
some time ago but the declaration didn't follow the implementation move.
Move it from fifo_gk20a.h to runlist.h.
Jira NVGPU-1309
Change-Id: Ib939a5243cee4be1c1092a553cb81b81adc6e5ce
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1997825
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MISRA Rule 10.1 states that operands shall not be of an inappopriate
essential type. For example, shift and bitwise operations should only
be performed on operands of essentially unsigned type.
This patch modifies gr exception handling to no longer use bitwise OR
when generating return status values.
Instead, the first non-zero status value is saved off and returned.
This has the added benefit of not potentially ORing together errno
values and generating an undefined status code.
JIRA NVGPU-650
Change-Id: If725a560c122d2cbf12e79b58161402da2023b5b
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1999098
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Move regops (gk20a/regops_gk20a.c) to separate unit common/regops/regops.c
Move corresponding header (gk20a/regops_gk20a.h) to include/nvgpu/regops.h
Move rest of the platform HAL files to common/regops/ as well
Fix all the header includes to include new public header
Remove *_apply_smpc_war() declarations from headers. Corresponding
functions were cleaned up already, and declarations were left somehow
Jira NVGPU-620
Change-Id: I8b8065b9c91f69809bdeb1b4caecdc7582c8a992
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1998723
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gk20a_remove_gr_support() is freeing the local_golden_image and
local_golden_image->context. But there are instances where
local_golden_image is not allocated since freeing an
unallocated golden context image accesses the contents of
local_golden_image causes a fault.
Check golden_image_initialized flag before freeing
local_golden_image->context.
Jira NVGPU-1648
Bug 2461665
Change-Id: I19235d2ec9d77ba4ef00257f43436448f5f70b25
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1997665
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