Moved below hals from {chip}/fifo_{chip}.[ch] to hal/fifo
get_mmu_fault_info
get_mmu_fault_desc
get_mmu_fault_client_desc
get_mmu_fault_gpc_desc
Moved gk20a_fifo_handle_dropped_mmu_fault to hal/fifo
JIRA NVGPU-1313
Change-Id: I949bcd482156c6e381006387372f13770277e8c5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083287
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gr_gk20a_commit_global_ctx_buffers() is h/w independent, hence move it
to common unit common.gr.obj_ctx and rename it as
nvgpu_gr_obj_ctx_commit_global_ctx_buffers()
Delete g->ops.gr.commit_global_ctx_buffers hal
Jira NVGPU-1887
Change-Id: If1c840237b8ba2c13bed40a4315810073756aeb9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088506
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Following functions are moved from gr_gk20a.c to common gr_falcon.c
gr_gk20a_disable_ctxsw -> nvgpu_gr_falcon_disable_ctxsw
gr_gk20a_enable_ctxsw -> nvgpu_gr_falcon_enable_ctxsw
gr_gk20a_halt_pipe -> nvgpu_gr_falcon_halt_pipe
Added new gr falcon hal to control ctxsw:
int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
u32 data, u32 *ret_val)
Parameters:
fecs_method: will be specified by a generic define provided in gr_falcon.h
header.
data: input data parameter (if any), set it to zero, if method did not
require any data input.
ret_val: pointer to expected output.
Added following ops for gr falcon:
int (*halt_pipe)(struct gk20a *g); -> this is moved from gr
int (*disable_ctxsw)(struct gk20a *g);
int (*enable_ctxsw)(struct gk20a *g);
JIRA NVGPU-1881
Change-Id: Idb3b7355b5a0bd3b9bb01f9f424c5d607616f540
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081308
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Move handle_gpc_gpccs_exception hal to hal.gr.intr
Pass g->ecc.gr.gpccs_ecc_corrected_err_count[gpc].counter and
g->ecc.gr.gpccs_ecc_uncorrected_err_count[gpc].counter variable address
as parameter to function to avoid dereferencing g->ecc variable
inside hal function.
Update g->ops.gr.handle_gpc_gpcss_exception call to
g->ops.gr.intr.handle_gpc_gpcss_exception
JIRA NVGPU-3016
Change-Id: I6cab6428eb6785261f34ca21f2ce055a9995b408
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087197
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Add new hal to get_tpc_exception to hal.gr.intr
This hal helps to avoid register read from the
common handle_tpc_exception function. Add a new struct to report the
tpc_exception type back to the common code to handle the exception.
JIRA NVGPU-3016
Change-Id: Ib504ade0b06b85cd38ccf166328784bab072573e
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085387
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The exec_regops() API was using a u64 for the num_ops parameter. The
lower level APIs used by exec_regops() expect u32s for this value.
Update the interface to use u32.
This eliminates MISRA Rule 10.3 violations for assignment of objects of
different essential or narrower types.
JIRA: NVGPU-3023
Change-Id: I5a2a22916f81d8b3d882d224d07eedffcde1e3ee
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084207
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Add new unit common.gr.setup that provides runtime setup interfaces to
other units outside of GR unit or to OS-specific code
Move zcull setup call to this unit.
New unit now exposes nvgpu_gr_setup_bind_ctxsw_zcull() to setup zcull
This API internally calls common.gr.zcull API nvgpu_gr_zcull_ctx_setup()
Add new hal g->ops.gr.setup.bind_ctxsw_zcull() and remove
g->ops.gr.zcull.bind_ctxsw_zcull()
Remove nvgpu_channel_gr_zcull_setup() from channel unit
Also remove ctx/subctx header includes sicne channel code need not
configure zcull
Remove gm20b_gr_bind_ctxsw_zcull() since binding is done from common
code
Jira NVGPU-1886
Change-Id: I6f04d19a8b8c003734702c5f6780a03ffc89b717
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2086602
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There is nothing h/w specific in gr_gv11b_update_ctxsw_preemption_mode
anymore. Delete it and re-use gp10b specific hal for volta/tu104
Update gr_gp10b_update_ctxsw_preemption_mode to call platform specific
hals if defined
Jira NVGPU-1887
Change-Id: Idae9ebf780b1e76abf847d8b39aa40c0e0560084
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084751
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Add new hal g->ops.gr.init.gfxp_wfi_timeout() in hal.gr.init unit
to commit gfxp timeout
Define gv11b chip specific operation
Use new hal in gr_gv11b_update_ctxsw_preemption_mode() instead of
directly committing using register accessors
Jira NVGPU-2961
Change-Id: I7694e3128920d9a2856faecf2e3d10a11f0f986e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084750
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Add new hal g->ops.gr.init.commit_cbes_reserve() in hal.gr.init unit
to commit cbes reserve
Define gp10b and gv11b chip specific operations
Use new hals in gr_gp10b_update_ctxsw_preemption_mode() and
gr_gv11b_update_ctxsw_preemption_mode() instead of directly committing
using register accessors
Jira NVGPU-2961
Change-Id: Iea2032ea61264c286b1fab46435ff5a84c90d3da
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084749
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Add new hal g->ops.gr.init.commit_ctxsw_spill() in hal.gr.init unit
to commit spill ctxsw buffer
Define gp10b and gv11b operations
Use new hals in gr_gp10b_update_ctxsw_preemption_mode() and
gr_gv11b_update_ctxsw_preemption_mode() instead of directly committing
using register accessors
Jira NVGPU-2961
Change-Id: Iced02d304f12bcb4e78ea31a7728baa04081e325
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084748
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Below hals are used to get preemption buffer sizes
g->ops.gr.get_ctx_spill_size()
g->ops.gr.get_ctx_pagepool_size()
g->ops.gr.get_ctx_betacb_size()
g->ops.gr.get_ctx_attrib_cb_size()
Move them to hal.gr.init unit
Copy over corresponding gp10b/gv11b definitions
Remove pagepool and attrib_cb size hals from gv11b since gv11b can
re-use gp10b hals
Add spill size and betacb size hals for gv100 and tu104 too since
register values are different on those chips
Remove g->ops.gr.init_gfxp_rtv_cb() hal and replace it by
g->ops.gr.init.get_gfxp_rtv_cb_size() which returns the size of RTV
cb size
Jira NVGPU-2961
Change-Id: I3f2f973c120dbfd22067366f87d06b5c9162defb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084747
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Moved enable/disable HALs from fifo to tsg:
- tsg.enable
- tsg.disable
gk20a_tsg_enable and gv11b_tsg_enable are moved to HAL,
since they are chip specific, even though they do not
directly access chip registers.
Removed vgpu_gv11b_tsg_enable as it was identical to
gv11b_tsg_enable.
Changed gv11b_fifo_locked_abort_runlist_active_tsgs and
gv11b_fifo_teardown_ch_tsg to use tsg.enable HAL instead
of calling directly gk20a_disable_tsg HAL implementation.
Jira NVGPU-2979
Change-Id: I721650c64dcf8cd158652e362292af45df43819f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083156
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Move handle_tex_exception hal function to hal.gr.intr
Move hal function for gm20b and gp10b chips.
Removed the null implementation in gv11b hal.
Modify ops->gr.handle_tex_exception call to
ops->gr.intr.handle_tex_exception
JIRA NVGPU-3016
Change-Id: Ifd88ab6f35301525f7a58e8ccf2f4796dda640bf
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084387
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RC_TYPE_PBDMA_FAULT is the only recovery type for all the pbdma intr
functions. Thus, rc_type variable is changed to a boolean type
in all implementations of handle_pbdma_intr* functions.
"handled" variable is unused and removed from all the implementations of
handle_pbdma_intr* functions.
handle_pbdma_intr* HAL ops are renamed to handle_intr*.
Jira NVGPU-2950
Change-Id: I9605d930225a38ed76f25b6a94cb02d855f522dd
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083748
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Code for secure/non-secure ctxsw booting spread across gr_gk20a.c
and gr_gm20b.c. With this change this code is move to gr falcon unit.
Ctxsw loading is now supported with 2 supported common functions:
1.Non secure boot:
int nvgpu_gr_falcon_load_ctxsw_ucode(struct gk20a *g);
2.Secure boot:
int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g);
Now gr ops function "int (*load_ctxsw_ucode)(struct gk20a *g);" is moved to
gr falcon ops and in chip hals it is set with secure/non-secure booting.
Non-secure booting: nvgpu_gr_falcon_load_ctxsw_ucode support ctxsw loading
in 2 methods: bit-banging uode or booting with bootloader
A. Common and hal functions for non-secure bit-banging ctxsw loading:
Common: static void nvgpu_gr_falcon_load_dmem(struct gk20a *g) ->
Hals: void (*load_gpccs_dmem)(struct gk20a *g,i
const u32 *ucode_u32_data, u32 size);
void (*load_fecs_dmem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
Common: static void nvgpu_gr_falcon_load_imem(struct gk20a *g) ->
Hals: void (*load_gpccs_imem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
void (*load_fecs_imem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
Other basic HALs:
void (*configure_fmodel)(struct gk20a *g); -> configure fmodel for ctxsw loading
void (*start_ucode)(struct gk20a *g); -> start running ctxcw ucode
B.Common and hal functions for non-secure ctxsw loading with bootloader
First get the ctxsw ucode using: nvgpu_gr_falcon_init_ctxsw_ucode, then
Common: static void nvgpu_gr_falcon_load_with_bootloader(struct gk20a *g)
void nvgpu_gr_falcon_bind_instblk((struct gk20a *g) ->
Hal: void (*bind_instblk)(struct gk20a *g, struct nvgpu_mem *mem, u64 inst_ptr);
Common: nvgpu_gr_falcon_load_ctxsw_ucode_segments ->
nvgpu_gr_falcon_load_ctxsw_ucode_header ->
nvgpu_gr_falcon_load_ctxsw_ucode_boot for both fecs and gpccs ->
Hals: void (*load_ctxsw_ucode_header)(struct gk20a *g, u32 reg_offset,
u32 boot_signature, u32 addr_code32, u32 addr_data32,
u32 code_size, u32 data_size);
void (*load_ctxsw_ucode_boot)(struct gk20a *g, u64 reg_offset, u32 boot_entry,
u32 addr_load32, u32 blocks, u32 dst);
Other basic HAL to get gpccs start offset:
u32 (*get_gpccs_start_reg_offset)(void);
C.Secure booting is support with gpmu and acr and with following additional
common function in gr falcon.
static void nvgpu_gr_falcon_load_gpccs_with_bootloader(struct gk20a *g) ->
nvgpu_gr_falcon_bind_instblk and nvgpu_gr_falcon_load_ctxsw_ucode_segments
Additional basic hals:
void (*start_gpccs)(struct gk20a *g);
void (*start_fecs)(struct gk20a *g);
Following ops from gr is removed, since it is not required to set by chip hals:
void (*falcon_load_ucode)(struct gk20a *g, u64 addr_base,
struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset);
Now this is handled by static common function:
static int nvgpu_gr_falcon_copy_ctxsw_ucode_segments( struct gk20a *g,
struct nvgpu_mem *dst, struct gk20a_ctxsw_ucode_segments *segments,
u32 *bootimage, u32 *code, u32 *data)
JIRA NVGPU-1881
Change-Id: I895a03faaf1a21286316befde24765c8b55075cf
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083388
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Add new hal g->ops.gr.init.load_sw_bundle_init() in hal.gr.init unit
and move corresponding code from gk20a_init_sw_bundle()
Add this hal to all the supported chips
Move g->ops.gr.init_sw_veid_bundle() hal to hal.gr.init unit
Move definition of hal to gv11b chip file of hal.gr.init
Add this hal for gv11b/gv100/tu104
Move g->ops.gr.init_sw_bundle64() hal to hal.gr.init unit
Move definition of hal to tu104 chip file of hal.gr.init
Add this hal for tu104
Jira NVGPU-2961
Change-Id: I560c2ba95fb820275d5ccb46939007c58481ccbb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083631
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fifo_pbdma_isr is moved to fifo_intr_gk20a HAL unit and renamed to
gk20a_fifo_pbdma_isr.
The pbdma specific handling part of the function
gk20a_fifo_handle_pbdma_intr is now separated into a top level HAL
function named handle_pbdma_intr. This HAL function is implemented
for GM20B and all the other architectures use the same implementation.
handle_pbdma_intr can accept NULL values for the parameters handled and
error_notifier.
gk20a_fifo_handle_pbdma_intr is called from
gv11b_fifo_poll_pbdma_chan_status and gk20a_fifo_pbdma_isr.
The call to gk20a_fifo_handle_pbdma_intr from
gv11b_fifo_poll_pbdma_chan_status doesn't progress to recovery.
Thus, the function gk20a_fifo_handle_pbdma_intr is removed to decouple
pbdma handling from recovery. gv11b_fifo_poll_pbdma_chan_status now
directly calls the HAL handle_pbdma_intr. For gk20a_fifo_pbdma_isr,
rc_type is used to proceed to recovery by calling
gk20a_fifo_pbdma_fault_rc.
gk20a_fifo_pbdma_fault_rc is changed to public from static.
Jira NVGPU-2950
Change-Id: I4f3597aca2317d4b745cd47bab9dd95c927160a9
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2073535
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- "tsg->tgid" is used for getting "pid" of contexts
in FECS trace support.
- "tsg->tgid" was unitialized for virtualized platforms
which was resulting in "pid" to be "0" for all contexts.
- This patch initializes tgid to fix this issue.
Jira NVGPU-1880
Change-Id: I59c30aca4609d61d09c465b7ec39983095af669b
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081759
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On gp10b, ramfc contains information related to syncpoint
protection, which restricts the syncpoint increment operation
to a safe set of syncpoints. This information must be
updated when a syncpoint is assigned to a channel.
Added the following ramfc HALs
- ramfc.get_syncpt
- ramfc.set_syncpt
And replaced
- fifo.resetup_ramfc
With
- channel.set_syncpt
Use new ramfc HALs, move resetup_ramfc implementation
from fifo to common channel code:
- nvgpu_channel_set_syncpt
NVGPU-1750
Change-Id: I036a0b7b2d9fd6ccd9f30094ae33e6c38a96e0cc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075938
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Created sub-unit for ltc interrupt handling.
Following 2-hals are moved from ltc to ltc intr unit:
void (*isr)(struct gk20a *g, u32 ltc);
void (*en_illegal_compstat)(struct gk20a *g, bool enable)
Added new hal in ltc intr sub-unit for configuring ltc interrupts:
void (*configure)(struct gk20a *g);
Moved ltc interrupt related code from ltc to ltc intr unit.
Chip ltc.intr hals are populated with updated function names
created in ltc intr unit.
Converted all "unsigned int" usage to "u32" in ltc and ltc intr units
to match with hardware 32 bit register read/write.
JIRA NVGPU-3042
JIRA NVGPU-2044
Change-Id: I8684dfcc8ae343e4588b93f2b0ccde0e227635df
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081140
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Move g->ops.gr.commit_global_cb_manager() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_cb_manager()
Move hal definitions to gm20b/gp10b hal files appropriately
Add nvgpu_gr_config pointer to the parameter list of this hal so that
it does not have to dereference struct gr_gk20a in hal.gr.init unit
Jira NVGPU-2961
Change-Id: Iaff476648fa6abdf5a79be500f65a40eb90c0b08
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077219
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Move g->ops.gr.commit_global_attrib_cb() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_attrib_cb()
Remove register header accessor from gr_gk20a_commit_global_ctx_buffers()
and move it to hal functions
Move hal definitions to gm20b/gp10b/gv11b hal files appropriately
Jira NVGPU-2961
Change-Id: I5437a190a9e027997f63ef0e741d99e6bbebab3f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077218
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Move g->ops.gr.commit_global_pagepool() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_pagepool()
Also move g->ops.gr.pagepool_default_size() hal to
g->ops.gr.init.pagepool_default_size()
Add global_ctx boolean flag as parameer to
g->ops.gr.init.commit_global_pagepool() to distinguish between
committing global pagepool v/s ctxsw pagepool buffers
Remove register header accessors from gr_gk20a_commit_global_ctx_buffers()
and move them to hal functions
Move hal definitions to gm20b/gp10b hal files appropriately
Remove g->ops.gr.pagepool_default_size() hal for gv11b since gv11b can
re-use gp10b hal
Jira NVGPU-2961
Change-Id: Id532defe05edf2e5d291fec9ec1aeb5b8e33c544
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077217
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Delete apply_ctxsw_timeout_intr ops and add
ctxsw_timeout_enable ops
Move chip specific sched_error and ctxsw_timeout
functions to hal/fifo/fifo_intr_* and hal/fifo/ctxsw_timeout_*
Add nvgpu_rc_ctxsw_timeout function under common/rc/rc.c
Do not check ctxsw timeout for channels that are no more
bound to tsg.
JIRA NVGPU-1312
Change-Id: Ide977fb60b3b72a27d9f22873f7a416c3bd1181d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075734
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common.fifo.userd unit has both safe as well as non-safe functions.
The build flag NVGPU_USERD is used to restrict the use of
non-safe functions of the userd unit in safety builds.
Jira NVGPU-2713
Change-Id: Idf3b244b24816789892ea802c2dcb42ca92649e1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075928
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move init_gpc_mmu hal to hal.gr.init and update the
g->ops.gr.init_gpc_mmu call as g->ops.gr.init.gpc_mmu
Add new hal, pes_vsc_stream which will enable the master bit to
take floorsweep into consideration.
Modify the disable_rd_coalesce hal as su_coalesce hal and
set_rd_coalesce call as lg_coalesce hal and move to hal.gr.init
su_coalesce hal function touches only the surface read coalesce bit.
lg_coalesce hal function touches only the lg read coalesce bit.
JIRA NVGPU-2951
Change-Id: Ifc5e36f7e75d3b74142a83a3c78a9cb2b81752eb
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079532
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Remove use of struct gk20a and struct gr_gk20a from common.gr.config
hal functions.
This requires a reference to struct gk20a *g for many nvgpu_* ops. Also,
nvgpu_gr_config is updated to include sm_count_per_tpc.
JIRA NVGPU-1884
Change-Id: I874c2b3970d97ef3940b74d8ef121a7261061670
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075681
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
