Move the gv11b MMU fault handling code into a new mm.mmu_fault HAL.
Also move the existing gmmu_mmu_fault HAL code into this HAL as they
are basically the same logical entity.
JIRA NVGPU-2042
JIRA NVGPU-1313
Change-Id: I41d3e180c762f191d4de3237e9052bdc456f9e4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109693
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Fix MISRA 5.3 violation for hiding the variable "ret."
Fix MISRA 10.1 violation in the NVGPU_COND_WAIT() macro. The timeout
value was being used as a boolean for the ? operator. Compare to 0
instead.
Fix MISRA 14.3 violation for invariant condition.
Fix MISRA 14.4 violation for using 0 for a boolean in the while
condition.
JIRA NVGPU-3329
Change-Id: I874aa66abb8771f9855ba4312ea068603d5b2e7b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109471
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Fix MISRA error for Rule 14.3
The switch governing value "offset" cannot reach the default case.
Execution cannot reach this statement "default:".
Change switch statement with if else checking
Jira NVGPU-3227
Change-Id: Ib1ccfe2d3bef94ffaf3e0f963bc21260844d0c91
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110759
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Fix for MISRA Rule 14.2.
Using a comma operator in the first clause of the for loop.
The first clause should either be empty or assign a value to the loop counter.
Don't update the loop counter within the loop body.
Jira NVGPU-3227
Change-Id: I6bee94c0ce7198d6ff4e465e2e0d982d3d358161
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110758
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MISRA rule 10.4 prohibits operator operands having different essential
type. The POSIX ffs() and fls() implementations were subtracting a
signed value of 1 from a unsigned long. The 1 is updated to be 1ULL to
fix the violation.
JIRA NVGPU-3337
Change-Id: I57d64705a3069c05c02635f4dd70902e96046d7d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109645
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Create a new unit for pramin. This is used for handling the HAL init for
pramin. Move the setup of the pramin gops for to the new pramin HAL.
This eliminates the need for the nvgpu.common.hal.init unit from having
to include the HW header file for pramin.
JIRA NVGPU-3274
Change-Id: I4e2402cf3e4eeb53e0fa5b6428624f8f3668fcd0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108805
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Currently, bitmap allocator reuses identifier "nvgpu_bitmap_alloc" for
an allocation function and as bitmap rbtree node struct. Renaming the
allocation function to "nvgpu_bitmap_balloc". Also, renaming fixed
allocation function to "nvgpu_bitmap_balloc_fixed" for consistency.
Jira NVGPU-3335
Change-Id: I6fe616db5137b2d4e2795a84ae5eafd527f0dba5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110714
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA 20.7 rule requires macro paramaters to be wrapped in
parantheses when the parameter expands into an expression.
Fix the MISRA rule 20.7 violation in posix cond unit.
Jira NVGPU-3139
Change-Id: Iae1f90a905e73cc0b3104ccab98bcabc81605452
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110264
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Check return code for nvgpu_pmu_lock_release,
g->ops.runlist.reschedule_preempt_next_locked and
g->ops.runlist.wait_pending and throw an
error message in case of failure.
Jira NVGPU-3379
Change-Id: If8a88e54f3dc769c70b772dfc93acfffb4b38d4d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109684
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Using u32 with bitops like for_each_set_bit results in MISRA
violation as bitops internally uses unsigned long.
Define tsgid as unsigned long an use (u32) cast when needed.
Jira NVGPU-3379
Change-Id: I99f9dae18ee74223de40dd5990bfad4eee2f4559
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109680
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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MISRA rule 2.2 defines dead code as "operations which are executed but
removal of these operations has no effect on program behavior".
Variable initializations violate this rule if initialized value is not
used and replaced.
This patch fixes some of these reported violations.
Jira NVGPU-858
Change-Id: I694517ace8884c78c63f6346e455078d19b70b4d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110459
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Move the get_litter() functions out of the main hal init to its own
source file for each device. This allows removal of the hw_proj_*.h
files in the main hal init file. This reduces the number of hw header
includes per file creating better code isolation.
JIRA NVGPU-3274
Change-Id: I9e04294434acf274ccc2236646f0f15f710a6976
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107751
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create a new unit common.fbp which initializes fbp support and provides
APIs to retrieve fbp data.
Create private header with below data
struct nvgpu_fbp {
u32 num_fbps;
u32 max_fbps_count;
u32 fbp_en_mask;
u32 *fbp_rop_l2_en_mask;
};
Expose below public APIs to initialize/remove fbp support:
nvgpu_fbp_init_support()
nvgpu_fbp_remove_support()
vgpu_fbp_init_support() for vGPU
Expose below APIs to retrieve fbp data
nvgpu_fbp_get_num_fbps()
nvgpu_fbp_get_max_fbps_count()
nvgpu_fbp_get_fbp_en_mask()
nvgpu_fbp_get_rop_l2_en_mask()
Use above APIs to retrieve fbp data in all the code.
Remove corresponding fields from struct nvgpu_gr since they are no
longer referred from that structure
Jira NVGPU-3124
Change-Id: I027caf4874b1f6154219f01902020dec4d7b0cb1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108617
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Identifier names used were already used to represent types. Fix those.
for e.g. pwr_channel in nv_pmu_pmgr_pwr_channel_union.
pmu_init_msg identifier name changed to init_msg as that is used to
represent a type.
JIRA NVGPU-3272
Change-Id: I887b66f08df1e00803d872873f6447f563675d44
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108548
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MISRA Rule 13.5 mandates that the right hand operand of a
logical && or || operator does not contain persistent side effects.
Removed use of nvgpu_readl from the if condition.
Jira NVGPU-3378
Change-Id: Ia5d7c083d6827f8a7db152757e683a4a06418b21
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109477
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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channel.c calling nvgpu_gr_flush_channel_tlb() creating circular
dependency between gr and fifo. Avoid this by moving channel tlb
related data to struct nvgpu_gr_intr in gr_intr_priv.h and
initialized this data in gr_intr.c.
Created following new gr intr hal and called this new hal from channel.c
void (*flush_channel_tlb)(struct gk20a *g);
JIRA NVGPU-3214
Change-Id: I2d259bf52db967273030680f50065af94a17f417
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109274
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Remove gr_priv.h from outside gr files.
Add hal function in gr.init for get_no_of_sm. This helps
to avoid dereferencing gr in couple of files for g->gr->config and
avoid gr_priv.h include in those files.
Replace nvgpu_gr_config_get_no_of_sm call with
g->ops.gr.init.get_no_of_sm for files outside gr unit.
Jira NVGPU-3218
Change-Id: I435bb233f70986e31fbfcb900ada3b3bda0bc787
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109182
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- To enable FECS trace support, nvgpu should set the MSB
of the read pointer (MAILBOX1).
- The ucode will check if the feature is enabled/disabled
before writing a record into the circular buffer. If the
feature is disabled, it will not write the record.
- If the feature is enabled and the buffer is not allocated,
HW will throw a page fault error.
Bug 2459186
Change-Id: I8080b21d21259e863c099883d6be737e9a869e50
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109286
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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