MISRA rule 20.7 requires macro paramaters to be wrapped in parantheses
when the parameter expands into an expression. Fix violations of rule
20.7 in atomic unit.
MISRA rule 10.3 prohibits the assignment of the value of an expression
to an object with narrower essential type or of a different essential
type category. Fix violations of rule 10.3 in atomic unit.
Jira NVGPU-3296
Change-Id: I087a6d15c5d03885aea29f22853e5bbde7880014
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116306
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Avoid use of local variable "max" by renaming it to "max_netlist_num"
JIRA NVGPU-3420
Change-Id: Ie0a49aa6c24617d22efe401ae883d0a9c8b1dff0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116066
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Use uintptr_t casting to avoid following error:
The object pointer expression "netlist_fw->data" of type "u8 *"
is cast to type "struct netlist_image *"
JIRA NVGPU-3420
Change-Id: Ice2e22eefc40c1f33ee9be68f460d3f8b3a2225c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116065
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Below MISRA 10.3 violation is reported in hal.gr.config unit
Error: MISRA C-2012 Rule 10.3:
nvgpu/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c:174:
misra_violation: Implicit conversion of "pix_scale * min_scg_gpc_pix_perf + world_scale *
scg_world_perf + tpc_scale * tpc_balance" from essential type "unsigned 32-bit int" to different
or narrower essential type "signed 32-bit int".
Fix this by declaring corresponding variables u32.
This should have no functional impact as such
Jira NVGPU-3406
Change-Id: I5b66c8db25c33afec3ab622a8d45997d5c8e6daa
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115591
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 10.3 violation is reported in hal.gr.config unit
Error: MISRA C-2012 Rule 10.3:
nvgpu/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c:150:
misra_violation: Implicit conversion of "(int)average_tpcs - scale_factor * num_tpc_gpc[gpc_id]"
from essential type "unsigned 32-bit int" to different or narrower essential type "signed 32-bit int".
Fix this by converting "diff" variable to u32 and checking for greater
value before doing subtraction operation
Jira NVGPU-3406
Change-Id: I27695db5bd3a4f20db878888dc87dc78ff04888a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115590
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 10.3 violations are reported in hal.gr.config unit
Error: MISRA C-2012 Rule 10.3:
nvgpu/drivers/gpu/nvgpu/hal/gr/config/gr_config_gv100.c:72:
misra_violation: Implicit conversion of "gpc_tpc_mask[gpc_id]" from essential type
"unsigned 64-bit int" to different or narrower essential type "unsigned 32-bit int".
gpc_tpc_mask[] and tpc variables should really be u32, hence declare
them as u32 everywhere
for_each_set_bit() takes parameters as unsigned long
Use temporary unsigned long variables in above macro and then
explicitly cast them to/from u32
Jira NVGPU-3406
Change-Id: Idd1dc2ba95bd1f6a3968a0103f0ec4914101f629
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115589
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule 13.5 states that the right hand operand of a logical && or ||
operator shall not have persistent side effects. Update the while loop
in gk20a_wait_for_idle() to comply.
JIRA NVGPU-3318
Change-Id: I3e51361914c298416bab1f2f7500d743ce409c8b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114658
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule 21.2 prohibits naming identifiers beginning with a double
underscore. This updates the function names __nvgpu_check_gpu_state()
and __gk20a_warn_on_no_regs() to comply.
JIRA NVGPU-3318
Change-Id: Ied2d168272a0f45fb8a08dda0e6fc798ebe3d22d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114656
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Fix MISRA violations for Rule 10.6 and 10.8 in gr.init unit
Assigning composite expression of width 32 to a target of width 64.
Cast from 32 bit width to a wider 64 bit type.
Jira NVGPU-3390
Jira NVGPU-3391
Change-Id: Id06fa9c90ae6cea1a7251b7834aca3f2c2f76e53
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116154
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix CERT-C error for translating size from "unsigned long" to
"unsigned int".
Error: CERT INT31-C:
nvgpu/drivers/gpu/nvgpu/common/gr/obj_ctx.c:300:
cert_violation: Casting "size" from "unsigned long" to "unsigned int"
without checking its value may result in lost or misinterpreted data.
JIRA NVGPU-3409
Change-Id: I304fe39049d4f15361b23970ca2bcaecd2050ca3
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114536
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix following misra violations in pmu ipc units:
1. Rule 10.4: msg->msg.init.msg_type was being set value from enum.
converted corresponding value PMU_INIT_MSG_TYPE_PMU_INIT to u8.
Other conversions from signed to unsigned. Conversion of the
enum PMU_RC_MSG_TYPE_UNHANDLED_CMD to unsigned value.
2. Rule 10.6: casted msg->hdr.size to U32 wherever required.
3. Rule 10.7: same as above.
4. Rule 13.5: nvgpu_timeout_expired() has side-effects of updating
the timer counts. Using it as first operand of && in if clause.
5. Rule 16.4: added non-empty default clause to switch.
6. Rule 17.7: return value of nvgpu_pmu_vidmem_surface_alloc,
nvgpu_falcon_copy_to_dmem, nvgpu_pmu_lsfm_int_wpr_region,
nvgpu_timeout_init, pmu_init_perfmon, pmu_handle_event,
pmu_response_handle and memset is handled.
7. Rule 2.2: removed unnecessary initialization of local variable.
JIRA NVGPU-3273
Change-Id: Ie5a53bcdf0d138cb02867a09dc42195449e146a0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112619
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Below MISRA 16.4 violations are reported in gr.obj_ctx unit
nvgpu/drivers/gpu/nvgpu/common/gr/obj_ctx.c:135:
misra_violation: The switch statement "switch (graphics_preempt_mode)"
does not have a non-empty default clause.
nvgpu/drivers/gpu/nvgpu/common/gr/obj_ctx.c:188:
misra_violation: The switch statement "switch (compute_preempt_mode)"
does not have a non-empty default clause.
Fix them by adding a debug print in default case
Jira NVGPU-3407
Change-Id: I0beabd020885f574f798a852008b5ccac919b450
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114366
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Below MISRA 17.7 violation is reported in common.gr.obj_ctx unit
nvgpu/drivers/gpu/nvgpu/common/gr/obj_ctx.c:603:
misra_c_2012_rule_17_7: The return value of a non-void function
"nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode" is unused.
Fix this by adding a check for return value of above function
Jira NVGPU-3407
Change-Id: I53467ab3e5ff9dc9dd7f194b3d67649f81fa0546
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114365
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 5.7 violation is reported in common.gr.obj_ctx unit
nvgpu/drivers/gpu/nvgpu/common/gr/obj_ctx.c:68:
identifier_reuse: Identifier "class" is already used to represent a type.
nvgpu/drivers/gpu/nvgpu/include/nvgpu/nvgpu_common.h:27:
type_declaration: Declaring a type with identifier "class".
Fix this by changing variable name "class" to "class_num"
Jira NVGPU-3407
Change-Id: Ic19aa4f1ff0adbe5d946ca18a165975e3af699fa
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114364
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 5.7 violation is reported in common.gr.setup unit
nvgpu/drivers/gpu/nvgpu/common/gr/gr_setup.c:218:
identifier_reuse: Identifier "class" is already used to represent a type.
nvgpu/drivers/gpu/nvgpu/include/nvgpu/nvgpu_common.h:27:
type_declaration: Declaring a type with identifier "class".
Fix this by changing variable name "class" to "class_num"
Jira NVGPU-3407
Change-Id: I7517995b105c65c2fa78f4959aad9e3f04585f02
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114363
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below MISRA 17.7 violation is reported in common.gr.fs_state unit
nvgpu/drivers/gpu/nvgpu/common/gr/fs_state.c:121:
misra_c_2012_rule_17_7: The return value of a non-void function
"*g->ops.gr.init.rop_mapping" is unused
This hal need not return any error hence convert return type to void
map_tiles are always allocated before calling this hal hence no need
to check if they are allocated in this hal
Jira NVGPU-3407
Change-Id: Ic78946fcc7b4780208c416c444d33aea2db20bfc
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114361
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Modified PMU subunits init sequence as they required during PMU RTOS
initialize stage, function nvgpu_pmu_early_init() allocates space for
all its subunit & its default values for further usage during runtime,
and function nvgpu_pmu_init() performs setup for sub units & starts
PMU-RTOS boot.
Deinit of all sub units allocated space will handled as part of
remove_support stage & also, during init stage upon failure of
init/setup sequence.
JIRA NVGPU-1972
Change-Id: I3ead9f9bb9e9c1178a02fc99eeec276660477325
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110154
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Some functions are not accessing hardware directly
but are being called using HAL ops: For example
g->ops.pmu.pmu_elpg_statistics,
g->ops.pmu.pmu_pg_init_param,
g->ops.pmu.pmu_pg_supported_engines_list,
g->ops.pmu.pmu_pg_engines_feature_list,
g->ops.pmu.pmu_is_lpwr_feature_supported,
g->ops.pmu.pmu_lpwr_enable_pg,
g->ops.pmu.pmu_lpwr_disable_pg,
g->ops.pmu.pmu_pg_param_post_init,
g->ops.pmu.save_zbc
Change the function access by using sw ops, like:
Create new functions:
int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
struct pmu_pg_stats_data *pg_stat_data);
void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries);
bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g,
u32 feature_id);
JIRA NVGPU-3209
Change-Id: I6db9b43c7c4a5054720a72487302b740b091044d
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110963
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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MISRA Rule 11.2 doesn't allow conversion to or from an incomplete type
pointer, as it may result incorrect point alignment and may further lead
to undefined behavior.
MISRA Rule 16.x requires all switch statements to be well-formed with
terminating break statement for every switch-clause.
This patch fixes 11.2 and 16.x violations in common.mm.nvgpu_mem.
Jira NVGPU-3339
Change-Id: I002393cc64d44826e6954d1bf6af71bd569e862f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113096
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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