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17486ec1f6da3db77ee63db5bf66a1c550576cb1
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6116 Commits

Author SHA1 Message Date
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs 
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-06 02:56:53 -07:00
Vinod G
f62fd1287e gpu: nvgpu: gr/init MISRA fix for Rule 14.2 
Fix for MISRA error Rule 14.2
Using a comma operator in the first clause of the for loop.
The first clause should either be empty or assign a value to the loop counter.

Jira NVGPU-3227

Change-Id: Ia46d8c9a8fb99f9e49be2eb56cabef6947c5b44b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111678
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-05 13:04:54 -07:00
Vinod G
e545a7b52e gpu: nvgpu: gr/init MISRA fix for Rule 15.7 
Fix misra_violation - No non-empty terminating else statement.

Jira NVGPU-3227

Change-Id: I1948f6f020de2e9e1f429820621bc403f1bc4d59
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111677
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-05 13:04:45 -07:00
Vinod G
b3603b9e16 gpu: nvgpu: gr/init MISRA fixes for Rule 8.3 
Fix Parameter name differ in function definition for
MISRA Rule 8.3

Jira NVGPU-3227

Change-Id: I596c713660bc36ce279280e023647f7e324ac8aa
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111622
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2019-05-05 13:04:36 -07:00
Thomas Fleury
0d1100f2de gpu: nvgpu: tsg MISRA fixes for Rule 17.7 
Check return value of channel_gk20a_update_runlist in
nvgpu_tsg_unbind_channel, and throw an error in case
of failure.

Jira NVGPU-3380

Change-Id: I1214b117d3d202fd805ae8c1fe00cdcc043e621f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111385
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 16:27:58 -07:00
Thomas Fleury
86859555f8 gpu: nvgpu: tsg MISRA fixes for Rule 15.7 
Refactored if / else statements in nvgpu_tsg_bind_channel and
nvgpu_tsg_check_ctxsw_timeout to avoid "else if" with no
terminating "else" statement.

Jira NVGPU-3380

Change-Id: I741cfbd49c7cb510fff03249e464bb4405ec903f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-03 16:27:43 -07:00
Thomas Fleury
e6638354e9 gpu: nvgpu: tsg MISRA fixes for Rule 14.2 
nvgpu_list_for_each_entry_safe violates MISRA Rule 14.2, as
it uses comma separator in the for clauses. Use a while loop
instead in nvgpu_tsg_release, as we want to empty the list.

Jira NVGPU-3380

Change-Id: I38211cc326e458d0912f374e3692328fb4e9b191
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111383
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-03 16:27:29 -07:00
Seshendra Gadagottu
e852ea6f2a gpu: nvgpu: fix MISRA directive 4.10 in gr falcon 
Use correct header files guard for gr_falcon_priv.h

JIRA NVGPU-3226

Change-Id: Ibdea01ba697017b70c23e0245ba7f9dbe33d7dac
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110735
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2019-05-03 16:27:14 -07:00
Seshendra Gadagottu
b2c634d1bb gpu: nvgpu: fix MISRA 16.x errors in gr falcon 
Fixed issues related to switch case formatting.

JIRA NVGPU-3226

Change-Id: I969ff3f56857ed0a523fb353ff07532ed50a114a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110734
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2019-05-03 16:27:05 -07:00
Seshendra Gadagottu
8a57a9d8f1 gpu: nvgpu: fix MISRA 15.7 errors in gr falcon 
Fixed issues related to no non-empty terminating
"else" statement.

JIRA NVGPU-3226

Change-Id: Iebb21ab0352bbdb02c44629f9cc7d06c75c11ab2
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110733
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2019-05-03 16:26:56 -07:00
Vinod G
fd79ecec05 gpu: nvgpu: Remove unused gr_priv header include 
Remove unused gr_priv.h and gr.h include from two files.

Jira NVGPU-3218

Change-Id: Ic3ec9a07d2e6928444490d3bc874702a76d0c2c8
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110725
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-03 16:26:46 -07:00
Alex Waterman
5003ccfa2e gpu: nvgpu: Move final gv100 and tu104 MM HALs to hal/mm/ 
Move the HALs under gv100 and tu104 to mm_gv100.c and mm_tu104.c
HAL files. Update the necessary makefiles and include directives
as well.

JIRA NVGPU-2042

Change-Id: I664e9d13e963bae826fc8f4b9b90cc4e1c231a90
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109695
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-03 16:26:31 -07:00
Alex Waterman
38c255c8a9 gpu: nvgpu: Rename gmmu_gmmu fault HALs 
Rename the gv11b_gmmu_* fault handling HALs to reflect their new
location under hal/mm/mmu_fault.

JIRA NVGPU-2042

Change-Id: I7ab8fe7ef922f36a907c45eeb210d72ff1447e4e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109694
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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 2019-05-03 16:26:17 -07:00
Alex Waterman
c053bc0226 gpu: nvgpu: Move gv11b MMU fault handling to HAL 
Move the gv11b MMU fault handling code into a new mm.mmu_fault HAL.
Also move the existing gmmu_mmu_fault HAL code into this HAL as they
are basically the same logical entity.

JIRA NVGPU-2042
JIRA NVGPU-1313

Change-Id: I41d3e180c762f191d4de3237e9052bdc456f9e4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109693
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 2019-05-03 16:26:07 -07:00
Seema Khowala
cfb4ff0bfb gpu: nvgpu: rename struct fifo_gk20a 
Rename
struct fifo_gk20a -> nvgpu_fifo

JIRA NVGPU-2012

Change-Id: Ifb5854592c88894ecd830da092ada27c7f05380d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109625
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 16:25:43 -07:00
Philip Elcan
fa59958e8a gpu: nvgpu: mm: fix misc MISRA violations in vidmem 
Fix MISRA violations for rules 14.x, 13.5, and 21.2 in
nvgpu.common.mm.vidmem unit.

JIRA NVGPU-3329

Change-Id: Ib45c8e1f2a427404e5506be7b7cf69b1c460297f
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109553
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 16:25:34 -07:00
Philip Elcan
25e87c40cf gpu: nvgpu: mm: fix MISRA 10.x violations in vidmem 
Fix MISRA 10.x violations in nvgpu.common.mm.vidmem. MISRA 10.x
violations are for inappropriate use of essential types.

JIRA NVGPU-3329

Change-Id: I0141a58c4afdfde3a2094932390150cca016452e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109472
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 16:25:25 -07:00
Philip Elcan
b93b30e411 gpu: nvgpu: posix: fix MISRA bugs in COND_WAIT 
Fix MISRA 5.3 violation for hiding the variable "ret."

Fix MISRA 10.1 violation in the NVGPU_COND_WAIT() macro. The timeout
value was being used as a boolean for the ? operator. Compare to 0
instead.

Fix MISRA 14.3 violation for invariant condition.

Fix MISRA 14.4 violation for using 0 for a boolean in the while
condition.

JIRA NVGPU-3329

Change-Id: I874aa66abb8771f9855ba4312ea068603d5b2e7b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109471
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 16:25:15 -07:00
Thomas Fleury
e61452ab5c gpu: nvgpu: tsg MISRA fixes for Rule 10.8 
roundup() violates MISRA Rule 10.8 when using operands
of different sizes. Use u32 operands.

Jira NVGPU-3259

Change-Id: Iff8983347cfef0d63fc6a51c2df1b2798eba48f9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111434
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 15:16:00 -07:00
Thomas Fleury
5b1b2b98aa gpu: nvgpu: tsg MISRA fixes for Rule 8.6 
Remove declaration of gk20a_tsg_event_id_post_event (which has
been renamed to nvgpu_tsg_event_id_post_event).

Jira NVGPU-3259

Change-Id: Ib0bdadefcd30e8b3063cb1da85aae352f182c6d0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111433
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-03 15:15:51 -07:00
Vinod G
03c6929f69 gpu: nvgpu: gr/init MISRA fix for Rule 14.3 
Fix MISRA error for Rule 14.3
The switch governing value "offset" cannot reach the default case.
Execution cannot reach this statement "default:".

Change switch statement with if else checking

Jira NVGPU-3227

Change-Id: Ib1ccfe2d3bef94ffaf3e0f963bc21260844d0c91
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110759
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 14:06:03 -07:00
Vinod G
b06d43e715 gpu: nvgpu: gr/init MISRA fix for Rule 14.2 
Fix for MISRA Rule 14.2.
Using a comma operator in the first clause of the for loop.
The first clause should either be empty or assign a value to the loop counter.
Don't update the loop counter within the loop body.

Jira NVGPU-3227

Change-Id: I6bee94c0ce7198d6ff4e465e2e0d982d3d358161
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110758
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 14:05:48 -07:00
Seema Khowala
2e912e13d0 gpu: nvgpu: priv_ring MISRA fix for rule 10.3 
JIRA NVGPU-3288

Change-Id: Icf0b91de37408be2c3d28c3cd442d2e4af2e13d1
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110651
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 14:05:21 -07:00
ajesh
e154c1c007 gpu: nvgpu: fix MISRA violations in bug unit 
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore.  Fix the violations of MISRA rule 21.2 in bug unit.

Jira NVGPU-3139

Change-Id: I2670f3745d09069a4d36beec4291c795a08f1c49
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111058
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 13:08:30 -07:00
ajesh
cfb17a1f9a gpu: nvgpu: fix MISRA violations in kmem unit 
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore.  Fix the violations of MISRA rule 21.2 in kmem unit.

Jira NVGPU-3139

Change-Id: I20f80e8bcdc8f802bd9aea34bbf050cafdfbd72e
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110524
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-03 13:08:00 -07:00
Philip Elcan
c6531d8b78 gpu: nvgpu: mm: fix MISRA 17.2 violation 
MISRA rule 17.2 prohibits functions calling themselves (recursion).
Remove recursion in the function buddy_coalesce().

JIRA NVGPU-3337

Change-Id: I03ec9751688f79b4bf704f5be1c43fce6e0dbaf5
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109647
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 13:07:45 -07:00
Philip Elcan
9f7b712e3a gpu: nvgpu: mm: fix MISRA 21.2 violation in buddy allocator 
The buddy allocator was defining a macro with double underscores which
is prohibited by MISRA rule 21.2. Update the name to something
acceptable.

JIRA NVGPU-3337

Change-Id: Ib08ae6f4bb5ef36e915d9f01e198655e35fcb8d0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109646
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 13:07:36 -07:00
Philip Elcan
8c9a9f735d gpu: nvgpu: posix: fix MISRA 10.4 violations with ffs & fls 
MISRA rule 10.4 prohibits operator operands having different essential
type. The POSIX ffs() and fls() implementations were subtracting a
signed value of 1 from a unsigned long. The 1 is updated to be 1ULL to
fix the violation.

JIRA NVGPU-3337

Change-Id: I57d64705a3069c05c02635f4dd70902e96046d7d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109645
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 13:07:27 -07:00
Philip Elcan
13b4314c46 gpu: nvgpu: create nvgpu.common.hal.pramin unit 
Create a new unit for pramin. This is used for handling the HAL init for
pramin. Move the setup of the pramin gops for to the new pramin HAL.
This eliminates the need for the nvgpu.common.hal.init unit from having
to include the HW header file for pramin.

JIRA NVGPU-3274

Change-Id: I4e2402cf3e4eeb53e0fa5b6428624f8f3668fcd0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108805
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 13:07:18 -07:00
Vedashree Vidwans
31b4dcf8ec gpu: nvgpu: mm: fix MISRA 5.7 in bitmap allocator 
Currently, bitmap allocator reuses identifier "nvgpu_bitmap_alloc" for
an allocation function and as bitmap rbtree node struct. Renaming the
allocation function to "nvgpu_bitmap_balloc". Also, renaming fixed
allocation function to "nvgpu_bitmap_balloc_fixed" for consistency.

Jira NVGPU-3335

Change-Id: I6fe616db5137b2d4e2795a84ae5eafd527f0dba5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110714
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 12:12:12 -07:00
ajesh
a2ff35ad9e gpu: nvgpu: fix MISRA violation in cond unit 
MISRA 20.7 rule requires macro paramaters to be wrapped in
parantheses when the parameter expands into an expression.
Fix the MISRA rule 20.7 violation in posix cond unit.

Jira NVGPU-3139

Change-Id: Iae1f90a905e73cc0b3104ccab98bcabc81605452
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110264
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 10:48:13 -07:00
Rajesh Devaraj
baa6fb3546 gpu: nvgpu: remove unused iGPU SDL service IDs 
Remove the following unused iGPU SDL related service IDs.
1. NVGUARD_SERVICE_IGPU_HOST_SWERR_PFIFO_ENG_SYNCPOINT_ERROR
2. NVGUARD_SERVICE_IGPU_HOST_SWERR_PTIMER_ERROR
3. NVGUARD_SERVICE_IGPU_FECS_SWERR_HOST_INT_EXCEPTION
4. NVGUARD_SERVICE_IGPU_PGRAPH_SWERR_GPC_EXCEPTION

Jira NVGPU-3238

Change-Id: I6e2faa737d047c1ca95a4844e59fdf8ca4574121
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110132
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:42:54 -07:00
ajesh
5290f3aed2 gpu: nvgpu: unify qnx bitops unit with posix 
Unify qnx bitops unit with posix implementation.  Move certain defines
from bitops unit to posix types unit as part of unification.

Jira NVGPU-2149

Change-Id: I4969f9c893bef511b222f173051815ed2a504da0
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109508
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:41:44 -07:00
Seema Khowala
170d7464d6 gpu: nvgpu: move fifo_gk20a.[ch] to hal/fifo 
Move fifo_gk20a struct to fifo.h
Move fifo_gk20a.[ch] to hal/fifo

Add missing includes for fifo subunits.

JIRA NVGPU-2012

Change-Id: I8bf5402bd5a9f8ff9f6a818cee553b57e117f3bc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109012
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-02 23:40:42 -07:00
Seema Khowala
39070c653f gpu: nvgpu: move FIFO_INVAL_* out of fifo_gk20a.h 
Move and rename
FIFO_INVAL_ENGINE_ID -> NVGPU_INVALID_ENG_ID
FIFO_INVAL_TSG_ID -> NVGPU_INVALID_TSG_ID
FIFO_INVAL_RUNLIST_ID -> NVGPU_INVALID_RUNLIST_ID
FIFO_INVAL_SYNCPT_ID -> NVGPU_INVALID_SYNCPT_ID
FIFO_INVAL_CHANNEL_ID -> NVGPU_INVALID_CHANNEL_ID

JIRA NVGPU-2012

Change-Id: Ic4cc16ece64d85e22f16e4d28dcfd0c187bb65f3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109011
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-02 23:40:26 -07:00
Seema Khowala
034d44311e gpu: nvgpu: move profile related struct and func 
Add include/nvgpu/profile.h

Move from fifo_gk20a.h to include/nvgpu/profile.h and rename

fifo_profile_gk20a -> nvgpu_profile
gk20a_fifo_profile_acquire -> nvgpu_profile_acquire
gk20a_fifo_profile_release -> nvgpu_profile_release
gk20a_fifo_profile_snapshot -> nvgpu_profile_snapshot

JIRA NVGPU-2012

Change-Id: I4f9fde9f0ccdeedec62d1f612046be14db334a89
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109010
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:40:09 -07:00
Seema Khowala
296ff58eb1 gpu: nvgpu: move engine related struct 
Move from fifo_gk20a.h to engines.h
fifo_pbdma_exception_info_gk20a
fifo_engine_exception_info_gk20a
fifo_engine_info_gk20a

Rename
fifo_pbdma_exception_info_gk20a -> nvgpu_pbdma_exception_info
fifo_engine_exception_info_gk20a -> nvgpu_engine_exception_info
fifo_engine_info_gk20a -> nvgpu_engine_info
NVGPU_ENGINE_GR_GK20A -> NVGPU_ENGINE_GR
NVGPU_ENGINE_GRCE_GK20A -> NVGPU_ENGINE_GRCE
NVGPU_ENGINE_ASYNC_CE_GK20A -> NVGPU_ENGINE_ASYNC_CE
NVGPU_ENGINE_INVAL_GK20A -> NVGPU_ENGINE_INVAL

JIRA NVGPU-2012

Change-Id: I665487721608ff9eacbdebff17d9dbef653de55e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109009
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:39:59 -07:00
Seema Khowala
3392a72d1a gpu: nvgpu: move runlist related struct and defines 
Move from fifo_gk20a.h to runlist.h
RUNLIST_DISABLED
RUNLIST_ENABLED
MAX_RUNLIST_BUFFERS
struct fifo_runlist_info_gk20a

Rename
fifo_runlist_info_gk20a -> nvgpu_runlist_info

JIRA NVGPU-2012

Change-Id: Ib7e3c9fbf77ac57f25e73be8ea64c45d4c3155ff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109008
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:39:42 -07:00
Seema Khowala
4b64b3556a gpu: nvgpu: add fifo.bar1_snooping_disable hal 
Add fifo.bar1_snooping_disable hal

Rename and move from fifo_gk20a.c to fifo.c
gk20a_fifo_suspend -> nvgpu_fifo_suspend

Rename
gk20a_readl -> nvgpu_readl
gk20a_writel -> nvgpu_writel

Remove unused defines and function prototypes
from fifo_gk20a.h

JIRA NVGPU-2012

Change-Id: If7eed93340c5c60802b1af40790482fd5e1b33c1
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109007
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:39:25 -07:00
ajesh
9e3c8895dd gpu: nvgpu: unify qnx bitops unit with posix 
Unify qnx bitops unit with posix implementation.  Move circular buffer
related functions from qnx bitops unit to circular buffer unit.

Jira NVGPU-2149

Change-Id: I98501d8b483b81a4a284ffc972fc17b4fd3da9d9
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108510
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:38:14 -07:00
Alex Waterman
93ad56e937 Revert "gpu: nvgpu: Enabling/disabling FECS trace support" 
This reverts commit c272264f54.

Bug 2586438

Change-Id: I76f4c584bcf9641070df095e9a191357f84eaf5a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110570
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-02 18:16:26 -07:00
Vinod G
83f873c95d gpu: nvgpu: MISRA fixes in gr_intr file 
Fix one violation for MISRA Rule-13.5
 - Expression after || has persistent side effect
Fix two violation for MISRA Rule-17.7
- Return value is unused

Jira NVGPU-3227

Change-Id: I29127914ffcf2b075c4ac515b3a998f98c779556
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109778
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 18:15:59 -07:00
Vinod G
61e2b47b21 gpu: nvgpu: remove unused gr_priv.h include 
Remove the unused gr_priv.h include from files outside gr unit.

Jira NVGPU-3218

Change-Id: I104c24fbd50523303ef1921a62c5dde99298a87e
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109711
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 18:15:44 -07:00
Thomas Fleury
bfafc8c4f1 gpu: nvgpu: runlist MISRA fixes for Rule 17.7 
Check return code for nvgpu_pmu_lock_release,
g->ops.runlist.reschedule_preempt_next_locked and
g->ops.runlist.wait_pending and throw an
error message in case of failure.

Jira NVGPU-3379

Change-Id: If8a88e54f3dc769c70b772dfc93acfffb4b38d4d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109684
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 17:05:54 -07:00
Thomas Fleury
6e83701982 gpu: nvgpu: runlist MISRA fixes for Rule 15.7 
All "if(expr) else if" constructs shall be terminated with
an else statement. Re-factored checks to avoid "else if"
statement.

Jira NVGPU-3379

Change-Id: Idf8a80a3f314fcf3f3b7a0c6f01bbb9d2202bdf2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109683
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 17:05:45 -07:00
Thomas Fleury
0d4ef5fa34 gpu: nvgpu: runlist MISRA fixes for Rule 14.3 
Removed (engine_info != NULL) test in nvgpu_init_runlist_enginfo,
as it cannot be NULL by construction.

Jira NVGPU-3379

Change-Id: I76392a1adf7d4d1c1438a67a0142f4e50ca68eab
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109682
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 17:05:36 -07:00
Thomas Fleury
af84bdaae8 gpu: nvgpu: runlist MISRA fixes for Rule 10.4 
Fixed essential type for flags argument (0ULL) passed to
nvgpu_dma_alloc_flags_sys.

Jira NVGPU-3379

Change-Id: I3ab97d98b19bf168ba7a1c2a9357e778b1a242d5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109681
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 17:05:27 -07:00
Thomas Fleury
c5f873fa31 gpu: nvgpu: runlist MISRA fixes for Rule 10.3 
Using u32 with bitops like for_each_set_bit results in MISRA
violation as bitops internally uses unsigned long.
Define tsgid as unsigned long an use (u32) cast when needed.

Jira NVGPU-3379

Change-Id: I99f9dae18ee74223de40dd5990bfad4eee2f4559
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109680
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 17:05:18 -07:00
Thomas Fleury
8052ce1d9f gpu: nvgpu: remove inclusion of top hw header in ce 
We now use g->ops.top.get_num_lce to retrieve number of logical
copy engines. Remove inclusion of top hw header.

Jira NVGPU-2013

Change-Id: If401d363776c21a3afec084e3fc440b2ba65bcb2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110489
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 15:57:05 -07:00
Vedashree Vidwans
c90fcbae2a gpu: nvgpu: fix MISRA Rule 2.2 no dead code 
MISRA rule 2.2 defines dead code as "operations which are executed but
removal of these operations has no effect on program behavior".
Variable initializations violate this rule if initialized value is not
used and replaced.

This patch fixes some of these reported violations.

Jira NVGPU-858

Change-Id: I694517ace8884c78c63f6346e455078d19b70b4d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110459
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-02 15:56:56 -07:00