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147 Commits

Author SHA1 Message Date
Debarshi Dutta
4c30bd599f gpu: nvgpu: rename tsg_gk20a*/gk20a_tsg* functions. 
rename the functions with the prefixes tsg_gk20a*/gk20a_tsg*
to nvgpu_tsg_*

Jira NVGPU-3248

Change-Id: I9f5f601040d994cd7798fe76813cc86c8df126dc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120165
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-17 01:49:27 -07:00
Philip Elcan
78c7e601f8 gpu: nvgpu: debug: fix MISRA 5.7 violation 
MISRA 5.7 requires tag names be unique. Rename the struct
gk20a_debug_output to nvgpu_debug_context to avoid name collision with
the function of the same name.

JIRA NVGPU-3346

Change-Id: I9566b9dc6a7d090e87d9a09f6b8faf688589fbbd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116877
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-16 11:57:32 -07:00
Seema Khowala
f453f66fc4 gpu: nvgpu: fifo MISRA fix for Rule 15.7 
Add terminating else statement

JIRA NVGPU-3383

Change-Id: I3ceb15de502d3927452713765a83076837904624
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115899
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-13 14:11:13 -07:00
Seema Khowala
50d4421dc2 gpu: nvgpu: fifo MISRA fix for Rule 10.3 
JIRA NVGPU-3383

Change-Id: Ic1b30cd4b8c5dba0ea75ff0de316d0d5dcc99ae4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116730
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-13 14:10:57 -07:00
Seema Khowala
7054643749 gpu: nvgpu: fifo MISRA fix for Rule 10.3 
JIRA NVGPU-3383

Change-Id: Ice279ee436b1f54c3aa2279f1129aa6de11f1315
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115860
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-13 14:10:47 -07:00
Seema Khowala
42c2ea552d gpu: nvgpu: fifo MISRA fix for Rule 10.1 
JIRA NVGPU-3383

Change-Id: I18ab3ebd4728ff798c0cc47f6cb84d1dda225b53
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116729
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-13 14:10:37 -07:00
Rajesh Devaraj
8090e2d5eb gpu: nvgpu: report PFIFO CTXSW timeout error 
During code review, it has been found that PFIFO CTXSW timeout error related
callback has been removed while restructuring PFIFO unit. Hence, we are
introducing the callback to report PFIFO CTXSW timeout error to 3LSS.

Jira NVGPU-3439

Change-Id: I3c4b9a25215fb7692470ac43f0ea8fc21720c376
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115186
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-12 21:45:20 -07:00
Seema Khowala
671f1c8a36 gpu: nvgpu: channel MISRA fix for Rule 21.2 
Rename
_gk20a_channel_get -> nvgpu_channel_get__func
gk20a_channel_get -> nvgpu_channel_get
_gk20a_channel_put -> nvgpu_channel_put__func
gk20a_channel_put -> nvgpu_channel_put
trace_gk20a_channel_get -> trace_nvgpu_channel_get
trace_gk20a_channel_put -> trace_nvgpu_channel_put

JIRA NVGPU-3388

Change-Id: I4e37adddbb5ce14aa18132722719ca2f73f1ba52
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114118
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-09 04:39:34 -07:00
Seema Khowala
26d13b3b6b gpu: nvgpu: channel MISRA fix for Rule 21.2 
Rename functions starting with '_' and '__'.
__gk20a_channel_kill -> nvgpu_channel_kill
_gk20a_channel_from_id -> nvgpu_channel_from_id__func
gk20a_channel_from_id -> nvgpu_channel_from_id

JIRA NVGPU-3388

Change-Id: I3b5f63bf214c5c5e49bc84ba8ef79bd49831c56e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114037
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-09 04:39:08 -07:00
Vinod G
8cc1cd1625 gpu: nvgpu: gr hal to read gr_status_r register 
Add gr hal "get_gr_status" to return gr_status_r register value.
Remove hw_gr_gk20a.h from mmu_fault_gk20a.c

Jira NVGPU-3427

Change-Id: I2090204c5e4319fe2d03efb8de959c849632e198
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114070
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-08 17:17:38 -07:00
Seema Khowala
0acc79be87 gpu: nvgpu: preempt MISRA fix for Rule 1.1 
Add missing newline at the end of the file.

JIRA NVGPU-3383

Change-Id: I2430a8da322acfd7900bb604d9b3abd0133a2869
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113119
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-07 20:28:01 -07:00
Seema Khowala
c9686156c1 gpu: nvgpu: preempt MISRA fix for Rule 17.7 
Check return value of nvgpu_pmu_lock_rlease and
spit error message.
Check return value of nvgpu_timeout_init and spit
error message. Also return to the calling function
upon timeout init error.

JIRA NVGPU-3383

Change-Id: I91636255d1f16fab4b2ab934df67149f5efca7fe
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113107
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2019-05-07 20:27:52 -07:00
Seema Khowala
3df5e43f53 gpu: nvgpu: change init_pbdma_map to void function 
Fix MISRA Rule 17.7. Change init_pbdma_map fn pointer
to return void.

JIRA NVGPU-3383

Change-Id: Id76522c22a9c85ccafff8bd7f9a93cab139f56d5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113212
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-07 09:46:27 -07:00
Thomas Fleury
2b165deba1 gpu: nvgpu: engines MISRA fixes for Rule 1.1 
Add missing newline at end of file.

Jira NVGPU-3386

Change-Id: Id62f99c1e9517932627949a65fe0b9e4fe802c49
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113038
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-06 14:24:50 -07:00
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs 
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-06 02:56:53 -07:00
Seema Khowala
cfb4ff0bfb gpu: nvgpu: rename struct fifo_gk20a 
Rename
struct fifo_gk20a -> nvgpu_fifo

JIRA NVGPU-2012

Change-Id: Ifb5854592c88894ecd830da092ada27c7f05380d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109625
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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 2019-05-03 16:25:43 -07:00
Thomas Fleury
e61452ab5c gpu: nvgpu: tsg MISRA fixes for Rule 10.8 
roundup() violates MISRA Rule 10.8 when using operands
of different sizes. Use u32 operands.

Jira NVGPU-3259

Change-Id: Iff8983347cfef0d63fc6a51c2df1b2798eba48f9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111434
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 15:16:00 -07:00
Thomas Fleury
5b1b2b98aa gpu: nvgpu: tsg MISRA fixes for Rule 8.6 
Remove declaration of gk20a_tsg_event_id_post_event (which has
been renamed to nvgpu_tsg_event_id_post_event).

Jira NVGPU-3259

Change-Id: Ib0bdadefcd30e8b3063cb1da85aae352f182c6d0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111433
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-03 15:15:51 -07:00
Seema Khowala
170d7464d6 gpu: nvgpu: move fifo_gk20a.[ch] to hal/fifo 
Move fifo_gk20a struct to fifo.h
Move fifo_gk20a.[ch] to hal/fifo

Add missing includes for fifo subunits.

JIRA NVGPU-2012

Change-Id: I8bf5402bd5a9f8ff9f6a818cee553b57e117f3bc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109012
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-05-02 23:40:42 -07:00
Seema Khowala
39070c653f gpu: nvgpu: move FIFO_INVAL_* out of fifo_gk20a.h 
Move and rename
FIFO_INVAL_ENGINE_ID -> NVGPU_INVALID_ENG_ID
FIFO_INVAL_TSG_ID -> NVGPU_INVALID_TSG_ID
FIFO_INVAL_RUNLIST_ID -> NVGPU_INVALID_RUNLIST_ID
FIFO_INVAL_SYNCPT_ID -> NVGPU_INVALID_SYNCPT_ID
FIFO_INVAL_CHANNEL_ID -> NVGPU_INVALID_CHANNEL_ID

JIRA NVGPU-2012

Change-Id: Ic4cc16ece64d85e22f16e4d28dcfd0c187bb65f3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109011
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:40:26 -07:00
Seema Khowala
296ff58eb1 gpu: nvgpu: move engine related struct 
Move from fifo_gk20a.h to engines.h
fifo_pbdma_exception_info_gk20a
fifo_engine_exception_info_gk20a
fifo_engine_info_gk20a

Rename
fifo_pbdma_exception_info_gk20a -> nvgpu_pbdma_exception_info
fifo_engine_exception_info_gk20a -> nvgpu_engine_exception_info
fifo_engine_info_gk20a -> nvgpu_engine_info
NVGPU_ENGINE_GR_GK20A -> NVGPU_ENGINE_GR
NVGPU_ENGINE_GRCE_GK20A -> NVGPU_ENGINE_GRCE
NVGPU_ENGINE_ASYNC_CE_GK20A -> NVGPU_ENGINE_ASYNC_CE
NVGPU_ENGINE_INVAL_GK20A -> NVGPU_ENGINE_INVAL

JIRA NVGPU-2012

Change-Id: I665487721608ff9eacbdebff17d9dbef653de55e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109009
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:39:59 -07:00
Seema Khowala
3392a72d1a gpu: nvgpu: move runlist related struct and defines 
Move from fifo_gk20a.h to runlist.h
RUNLIST_DISABLED
RUNLIST_ENABLED
MAX_RUNLIST_BUFFERS
struct fifo_runlist_info_gk20a

Rename
fifo_runlist_info_gk20a -> nvgpu_runlist_info

JIRA NVGPU-2012

Change-Id: Ib7e3c9fbf77ac57f25e73be8ea64c45d4c3155ff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109008
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:39:42 -07:00
Thomas Fleury
5d85d2607d gpu: nvgpu: runlist MISRA fix for rule 2.2 
Removed initialization of ret in tu104_runlist_wait_pending,
as it is immediately overwritten with ret value from
nvgpu_timeout_init.

Jira NVGPU-3378

Change-Id: Icb565c173ba1ab7ad13ef7393888ab7832257d26
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109478
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 03:06:08 -07:00
Thomas Fleury
7ff3d7d11c gpu: nvgpu: runlist MISRA fix for rule 13.5 
MISRA Rule 13.5 mandates that the right hand operand of a
logical && or || operator does not contain persistent side effects.

Removed use of nvgpu_readl from the if condition.

Jira NVGPU-3378

Change-Id: Ia5d7c083d6827f8a7db152757e683a4a06418b21
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109477
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 03:05:59 -07:00
Thomas Fleury
983b4018e2 gpu: nvgpu: userd MISRA fix for unused return value 
g->ops.userd.init_mem return value is unused.
Changed type to void to fix MISRA rule 17.7 violation

Jira NVGPU-3260

Change-Id: If1cc0248522162944b6c8cefcf9963d6b1a1101f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108839
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-01 12:35:53 -07:00
Seema Khowala
f160202dbb gpu: nvgpu: move fifo_tu104.[ch] to hal/fifo 
Move fifo_tu104.[ch] from tu104/fifo_tu104.[ch] to
hal/fifo

JIRA NVGPU-2012

Change-Id: Ibb28ce9a0eaead10078600ecad4ad172ca03c404
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107725
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-30 21:47:18 -07:00
Thomas Fleury
258a6141fd gpu: nvgpu: rename runlist functions 
Renamed:
- gk20a_runlist_reload -> nvgpu_runlist_reload
- gk20a_fifo_interleave_level_name -> nvgpu_runlist_interleave_level_name
- gk20a_runlist_update_for_channel -> nvgpu_runlist_update_for_channel
- nvgpu_fifo_lock_active_runlists -> nvgpu_runlist_lock_active_runlists
- nvgpu_fifo_unlock_active_runlists -> nvgpu_runlist_unlock_active_runlists
- nvgpu_fifo_get_runlists_mask -> nvgpu_runlist_get_runlists_mask
- nvgpu_fifo_unlock_runlists -> nvgpu_runlist_unlock_runlists
- gk20a_runlist_update -> nvgpu_runlist_update

Jira NVGPU-3198

Change-Id: Ifc5ad2aae546614667c174643ee07283d2716adc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108029
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-30 12:46:02 -07:00
Thomas Fleury
10b8458f7b gpu: nvgpu: rename runlist HALs for mem access 
Renamed
- runlist_gk20a.c -> runlist_ram_gk20a.c
- runlist_gk20a.h -> runlist_ram_gk20a.h
- runlist_gv11b.c -> runlist_ram_gv11b.c
- runlist_gv11b.h -> runlist_ram_gv11b.h
- runlist_tu104.c -> runlist_ram_tu104.c
- runlist_tu104.h -> runlist_ram_tu104.h

Updated makefiles and include files.

Jira NVGPU-3198

Change-Id: Id65654990470bbf0bc79655d2f5efcb226dae220
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107604
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-30 12:44:35 -07:00
Thomas Fleury
58167f6601 gpu: nvgpu: clean runlist dependencies 
Split existing runlist HALs into:
- runlist HALs depending on ram hw headers
- runlist HALs depending on fifo hw headers

hal/fifo/runlist_<chip>.c implement
- runlist.entry_size
- runlist.get_tsg_entry
- runlist.get_ch_entry

hal/fifo/runlist_fifo_<chip>.c implement
- runlist.reschedule
- runlist.count_max
- runlist.entry_size
- runlist.hw_submit

Renamed
- nvgpu_fifo_reschedule_runlist -> nvgpu_runlist_reschedule

Jira NVGPU-3198

Change-Id: Icf835b0a4a45e5987e3db9d0931a9f111f418137
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107603
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-30 12:44:20 -07:00
Debarshi Dutta
965062c2bc gpu: nvgpu: remove direct tsg retrieval from fifo 
Added
- nvgpu_tsg_check_and_get_from_id
- nvgpu_tsg_get_from_id

And removed direct accesses to f->tsg array.

Jira NVGPU-3156

Change-Id: I8610e19c1a6e06521c16a1ec0c3a7a011978d0b7
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101251
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-26 14:16:47 -07:00
Thomas Fleury
124cdb4509 gpu: nvgpu: move set_interleave to tsg 
Renamed
- gk20a_tsg_set_runlist_interleave -> nvgpu_tsg_set_interleave

Moved set_interleave from runlist to tsg
- runlist.set_interleave -> tsg.set_interleave

Existing HAL was only setting tsg->interleave, and was not
accessing any register. This is now done in nvgpu_tsg_set_interleave
and tsg.set_interleave is only used in vgpu case.

Jira NVGPU-3156

Change-Id: I5dac1305afcbd950214316289cf704ee8b43fc89
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100610
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-26 14:16:04 -07:00
Thomas Fleury
3fde3ae650 gpu: nvgpu: move set_timeslice to tsg 
Moved the following HALs from fifo to tsg
- set_timeslice
- default_timeslice_us

Renamed
- gk20a_tsg_set_timeslice -> nvgpu_tsg_set_timeslice
- min_timeslice_us -> tsg_timeslice_min_us
- max_timeslice_us -> tsg_timeslice_max_us

Scale timeslice to take into account PTIMER clock in
nvgpu_runlist_append_tsg.

Removed gk20a_channel_get_timescale_from_timeslice, and
instead moved timeout and scale computation into runlist HAL,
when building TSG entry:
- runlist.get_tsg_entry

Use ram_rl_entry_* accessors instead of hard coded values
for default and max timeslices.

Added #defines for min, max and default timeslices.

Jira NVGPU-3156

Change-Id: I447266c087c47c89cb6a4a7e4f30acf834b758f0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100052
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-26 14:15:49 -07:00
Thomas Fleury
0e1e142aa9 gpu: nvgpu: move pdb_cache_war to ramin HAL 
Removed dependency on ram tu104 hw header from fifo code.

Moved the following HALs from fifo to ramin
- init_pdb_cache_war
- deinit_pdb_cache_war

Jira NVGPU-2012

Change-Id: Ia1848c430b8d19861d92d14d3cd01c9119553002
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105351
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-26 12:04:03 -07:00
Thomas Fleury
157b43ed16 gpu: nvgpu: clean ramfc dependencies 
Remove ramfc dependencies on fifo hw header.

Added the following HALs:
- fifo.get_runlist_timeslice
- fifo.get_pb_timeslice

Jira NVGPU-3199

Change-Id: I1bdd4ee5e4008676df514b9d8563e862d1d68e33
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104539
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-25 16:26:57 -07:00
Seema Khowala
1094c4dcd5 gpu: nvgpu: remove gr h/w header from runlist file 
Replace
nvgpu_readl(g, gr_fecs_ctxsw_mailbox_r(0))

With
g->ops.gr.falcon.read_fecs_ctxsw_mailbox(g, NVGPU_GR_FALCON_FECS_CTXSW_MAILBOX0)

JIRA NVGPU-2012
JIRA NVGPU-3198

Change-Id: Ibbcf54967f8e54da0e671bb8d08ad16d9cc50a9a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104409
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-25 12:55:31 -07:00
Seema Khowala
85fe940bed gpu: nvgpu: clean up unused header in fifo 
Clean up unused headers in fifo module

JIRA NVGPU-2012

Change-Id: Iff4ad3e02a18167dd83904819d04a7eface56a3a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104400
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-25 12:55:21 -07:00
Seema Khowala
192b5c5569 gpu: nvgpu: move fifo_gv11b.[ch] to hal/fifo 
Move fifo_gv11b.[ch] to hal/fifo and clean up
include directives

JIRA NVGPU-1314

Change-Id: I42346ea93360e4b5023eda7538406275eb583d13
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102929
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-24 20:23:18 -07:00
Debarshi Dutta
8e96d56cee gpu: nvgpu: add ramfc specific pbdma hal functions 
Only one h/w header is allowed per hal file. ramfc_*.c uses both
hw_ramfc_*.h and hw_pbdma_*.h. The pbdma dependencies are removed from
the HAL unit of ramfc by constructing new HAL functions for pbdma unit.
The HAL ops functions added are listed below.

get_gp_base
get_gp_base_hi
get_fc_formats
get_fc_pb_header
get_fc_subdevice
get_fc_target
get_ctrl_hce_priv_mode_yes
get_userd_aperture_mask
get_userd_addr
get_userd_hi_addr
get_fc_runlist_timeslice
get_config_auth_level_privileged
set_channel_info_veid
config_userd_writeback_enable
allowed_syncpoints_0_index_f
allowed_syncpoints_0_valid_f
allowed_syncpoints_0_index_v

These HAL ops uses the following new implementations.

gm20b_pbdma_get_gp_base
gm20b_pbdma_get_gp_base_hi
gm20b_pbdma_get_fc_formats
gm20b_pbdma_get_fc_pb_header
gm20b_pbdma_get_fc_subdevice
gm20b_pbdma_get_fc_target
gm20b_pbdma_get_ctrl_hce_priv_mode_yes
gm20b_pbdma_get_userd_aperture_mask
gm20b_pbdma_get_userd_addr
gm20b_pbdma_get_userd_hi_addr

gp10b_pbdma_get_fc_runlist_timeslice
gp10b_pbdma_get_config_auth_level_privileged
gp10b_pbdma_allowed_syncpoints_0_index_f
gp10b_pbdma_allowed_syncpoints_0_valid_f
gp10b_pbdma_allowed_syncpoints_0_index_v

gv11b_pbdma_get_fc_pb_header
gv11b_pbdma_get_fc_target
gv11b_pbdma_set_channel_info_veid
gv11b_pbdma_config_userd_writeback_enable

Jira NVGPU-3195

Change-Id: I849f16650046eca38c67b0d6e0e43cd2ab1ac224
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102576
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-24 03:43:44 -07:00
Philip Elcan
f63a9f9e49 gpu: nvgpu: create nvgpu.common.hal.func unit 
Move chip specific func files to hal/func. Update Makefiles and include
directives to make new locations.

JIRA NVGPU-2036

Change-Id: If3d633a2cd71d531f3eafdd1f808b0fd3ee6a113
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102898
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-23 12:46:09 -07:00
Seema Khowala
509fd2c93a gpu: nvgpu: rename fifo_gv100.[ch] 
Rename
fifo_gv100.[ch] -> hal/fifo/fifo_intr_gv100.[ch]

JIRA NVGPU-3144

Change-Id: I0add5ac7889ba98d5cf53f939f704faf92aa20eb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101278
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-22 15:25:52 -07:00
Seema Khowala
df831c200b gpu: nvgpu: rename enable/disable sched 
Rename
gk20a_tsg_enable_sched -> nvgpu_tsg_enable_sched
gk20a_tsg_disable_sched -> nvgpu_tsg_disable_sched

JIRA NVGPU-3144

Change-Id: I569025ea96e64b2bf3f8216a6080a8496570acf3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101277
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-22 15:25:38 -07:00
Seema Khowala
bdfc26af8b gpu: nvgpu: move preempt code to common/fifo and hal/fifo 
Move chip specific preempt code to hal/fifo
Move non-chip specific preempt code to common/fifo

Remove fifo.get_preempt_timeout

Rename gk20a_fifo_get_preempt_timeout -> nvgpu_preempt_get_timeout
Rename gk20a_fifo_preempt -> nvgpu_preempt_channel

Add fifo.preempt_trigger hal for issuing preempt
Add fifo.preempt_runlists_for_rc hal for preempting runlists during rc
Add fifo.preempt_poll_pbdma hal

Add nvgpu_preempt_poll_tsg_on_pbdma to be called from rc

JIRA NVGPU-3144

Change-Id: Idb089acaa0c6ca08de17487c3496459a61f0bcd4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100819
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-22 15:25:29 -07:00
Nicolas Benech
0435ca4eb3 gpu: nvgpu: fix MISRA 17.7 in nvgpu.common.hal.fifo.* 
MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. This patch contains fixes for all 17.7 violations
in the following units:
- nvgpu.common.hal.fifo.runlist
- nvgpu.common.hal.fifo.fifo

JIRA NVGPU-3039

Change-Id: I9483f5cb623cfe36d6b26e41c33f124c24710c08
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098765
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-19 19:04:05 -07:00
Thomas Fleury
1160f083d4 gpu: nvgpu: move ce code to common/ce and hal/ce 
Merged gk20a_ce_delete_context and gk20a_ce_delete_context_priv.

Renamed
- gk20a_init_ce_support -> nvgpu_ce_init_support
- gk20a_ce_destroy -> nvgpu_ce_destroy
- gk20a_ce_suspend -> nvgpu_ce_suspend
- gk20a_ce_create_context -> nvgpu_ce_create_context
- gk20a_ce_delete_context -> nvgpu_ce_delete_context
- gk20a_ce_execute_ops -> nvgpu_ce_execute_ops
- gk20a_ce_prepare_submit -> nvgpu_ce_prepare_submit
- gk20a_ce_put_fences -> nvgpu_ce_put_fences
- gk20a_ce_delete_gpu_context -> nvgpu_ce_delete_gpu_context
- gk20a_ce_get_method_size -> nvgpu_ce_get_method_size
- gk20a_gpu_ctx -> nvgpu_ce_gpu_ctx
- gk20a_gpu_ctx_from_list -> nvgpu_ce_gpu_ctx_from_list
- gk20a_ce_app -> nvgpu_ce_app
- gk20a_ce_debugfs_init -> nvgpu_ce_debugfs_init
- gk20a_get_valid_launch_flags -> nvgpu_ce_get_valid_launch_flags
- gk20a_ce2_isr -> gk20a_ce2_stall_isr
- gp10b_ce_isr -> gp10b_ce_stall_isr
- gv11b_ce_isr -> gv11b_ce_stall_isr

Inlined
- ce*_nonblockpipe_isr
- ce*_blockpipe_isr
- ce*_launcherr_isr

Added ce_priv.h for ce private definitions.

Moved files to common/ce and hal/fifo/ce
- ce2.c -> common/ce2/ce.c
- ce2_gk20a.c -> hal/ce/ce2_gk20a.c
- ce2_gk20a.h -> hal/ce/ce2_gk20a.h
- ce_gp10b.c -> hal/ce/ce_gp10b.c
- ce_gp10b.h -> hal/ce/ce_gp10b.h
- ce_gv11b.c -> hal/ce/ce_gv11b.c
- ce_gv11b.h -> hal/ce/ce_gv11b.h

Updated makefiles and #include directives

Jira NVGPU-1992

Change-Id: Ia6064bf51b7a254085be43a112d056cb6fb6c3b2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093503
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-19 13:55:11 -07:00
Thomas Fleury
7fb397b0b3 gpu: nvgpu: add format_gpfifo_entry HAL for pbdma 
Removed dependency on pbdma hw headers in ce2, cde and submit.

Added the following HAL to format gpfifo entries:
- pbdma.format_gpfifo_entry

Jira NVGPU-1992
Jira NVGPU-1990

Change-Id: I322d6bcd832b0ea5bbe2c2871b8f96b2793d8a65
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093502
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-19 13:54:56 -07:00
Nicolas Benech
97d65cb60d gpu: nvgpu: fix MISRA 17.7 in nvgpu.hal.* 
MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. This patch contains fixes for all 17.7 violations
in the following units:
- nvgpu.hal.bus
- nvgpu.hal.fb
- nvgpu.hal.fifo
- nvgpu.hal.gr

JIRA NVGPU-3153

Change-Id: Iac9477ee7c36a0f2f8840e178dc5418e600f9c84
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100652
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-19 12:14:46 -07:00
Seema Khowala
da9dee85e2 gpu: nvgpu: move mmu fault handling to hal/fifo 
Move chip specific mmu fault handling from
fifo_gk20a.c to hal/fifo/mmu_fault_gk20a.c

Move gk20a_teardown_ch_tsg to hal/rc/rc_gk20a.c

JIRA NVGPU-1314

Change-Id: Idf88b1c312bc9f46c2508f2c63e948d71d622297
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094051
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-18 15:56:08 -07:00
Seema Khowala
6ba1f5db3b gpu: nvgpu: move chip specific teardown_mask/unmask_intr 
Move chip specific functions for teardown_mask_intr and
teardown_unmask_intr to hal/fifo/fifo_intr_[chip].[ch]

Renamed
teardown_mask_intr -> intr_set_recover_mask
teardown_unmask_intr -> intr_unset_recover_mask

JIRA NVGPU-1314

Change-Id: If233565cbdb09d77cfebd4346edcc3fe64584355
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093980
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-18 15:55:53 -07:00
Seema Khowala
ca628dfd6e gpu: nvgpu: move engine functions to engines.c 
Removed
fifo.runlist_busy_engines ops

Moved to engines.c and renamed
gk20a_fifo_get_failing_engine_data -> nvgpu_engine_find_busy_doing_ctxsw
gk20a_fifo_get_faulty_id_type -> nvgpu_engine_get_id_and_type
gk20a_fifo_runlist_busy_engines -> nvgpu_engine_get_runlist_busy_engines

JIRA NVGPU-1314

Change-Id: I89c81f331321d47a616a785082d66f9b4a51ff71
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093788
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-18 15:55:24 -07:00
Seema Khowala
c570ba99ed gpu: nvgpu: move sched error bad tsg recovery 
Move sched error bad tsg recovery from fifo_intr_gv11b.c
to common/rc/rc.c

JIRA NVGPU-1314

Change-Id: Ic731a3162cad2fe184d764f0b3ad98acc1f382cb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095621
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-16 17:05:49 -07:00