Moved zbc related files to common/gr/zbc location.
struct nvgpu_gr_zbc created for zbc variables.
common zbc functions are moved to gr_zbc.c file.
All zbc hal functions are moved with corresponding chip specific
filename.
JIRA NVGPU-1882
Change-Id: I1bdaa2d9416e6e77ab305f117647dc070438ee86
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019760
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MISRA rule 16.3 states all switch clause to have break statement.
Fixing the missing break statement for default case.
Two consecutive labels without statement need not have break.
So no break is added for case without any statement.
This also makes the switch statement well-formed covering 16.1.
Since the function is too long, created a new function to
calculate the slope.
JIRA NVGPU-1507
Change-Id: I22b02de81ac3f605a19bf773ee475c40e7a77c2b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022749
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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When nvgpu_vm_unmap_sync fails, nvgpu_unmap_sync currently bails
out without decreasing the buffer refcount. This prevents from
releasing the buffer, in case a deferred job completes after the
timeout (which was observed 2 times during overnight
stress tests). This also means that the fixed address is not
re-useable.
Throw out a warning when nvgpu_vm_unmap_sync fails, but proceed
with decreasing refcount.
Bug 200492802
Change-Id: I4b7c90ffac6fd479b91d96a3b82c36d17b85ecdc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2023097
(cherry picked from commit c8ccc87998afc599303857a85cd4553796034164)
Reviewed-on: https://git-master.nvidia.com/r/2024304
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Timeslice mode is always set to enabled. So, it is not
required to check for timeslice mode enable and done
following cleanup as part of this change.
1. Removed timeslice_mode field from struct gr_gk20a and
removed setting of this field from the function
gr_gk20a_init_gr_config.
2. Removed checks for timeslice_mode enable in
gr_gk20a_commit_global_timeslice function.
3. Removed unused kernel definitions from headers:
gr_gpcs_ppcs_cbm_cfg_r()
gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v()
JIRA NVGPU-2155
Change-Id: Id99f4b771c74f4cea763ea63441043e93def2347
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Id99f4b771c74f4cea763ea63441043e93def2347
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024320
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gm20b clocks is accessing thermal registers directly in several places.
Moved all this code to thermal unit and clock code is accessing these
through provided thermal hal functions.
Following new hal are defined in thermal unit for enabling/disabling
throttling and enabling/disabling idle slowdown:
void (*throttle_enable)(struct gk20a *g, u32 val);
int (*throttle_disable)(struct gk20a *g);
void (*idle_slowdown_enable)(struct gk20a *g, u32 val);
int (*idle_slowdown_disable)(struct gk20a *g);
At this moment, these hals are getting used only by gm20b code.
JIRA NVGPU-2001
Change-Id: I937a7c76dfae9aa7e86f23c53f84fae9a9dda13e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2023289
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The type for the timeout parameter to the NVGPU_COND_WAIT and
NVGPU_COND_WAIT_INTERRUPTIBLE macros was too weak. This updates these
macros to require a u32 for the timeout.
Users of the macros are updated to be compliant as necessary.
This addresses MISRA 10.3 violations for implicit conversions of types
of different size or essential type.
JIRA NVGPU-1008
Change-Id: I12368dfa81b137c35bd056668c1867f03a73b7aa
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017503
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FECS ucode does a priv holdoff around the assertion of context
reset. So, priv transactions (e.g. mailbox1 register write) might
fail due to this. Hence, do write with ack i.e. write and read
it back to make sure write happened for mailbox1.
Bug 200417403
Change-Id: I463be1cb8fdd477106b87786cb0603327a22cebe
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2023494
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Add zbc stencil as chip feature. This help to remove the
hals added for stencil feature, instead use common functions.
Removed hals
stencil_query_table
load_stencil_default_tbl
add_type_stencil
load_stencil_tbl
JIRA NVGPU-1882
Change-Id: Iae410a8dd879660ecfd2d2a5ebf28b2cc8309be4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022385
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The unit_id is a u8, but the macros defining the different unit ids as
u32s in the header file. This causes MISRA 10.3 violations for
implicitly assigning objects of different size. So, this change makes
the header declarations u8s to avoid the 10.3 violations.
JIRA NVGPU-1008
Change-Id: I9790793b43d1d710941d8da2e6e97f07bc44e30c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017607
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Update the nvgpu_request_firmware API to use u32 for the flags
parameter. The API previously defined the flags parameter to be an int.
However, the flags were defined as UL. This was causing MISRA 10.3
violations for implicitly assigning an object of different essential
type. So, this change makes all definitions a u32.
JIRA NVGPU-1008
Change-Id: I09eb75d4e2a20e7ac6dba80d3bc06335d3c78d62
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2023223
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Previously, BITS_TO_LONGS macro had calculation bug due to incorrect
ordering of parantheses. This patch rearranges the parantheses to
correctly convert specified bits to nearest higher multiple of unsigned
long.
Change-Id: I296da2a2ebd805325189f956089ac201aa5b04d8
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024034
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Create new gr/fecs_trace unit with common/gr/fecs_trace/fecs_trace.c
as common source file and include/nvgpu/gr/fecs_trace.h as common
header file
This unit will be common between Linux and QNX
Corresponding HAL files will be added under common/gr/fecs_trace/
as more functionality is moved to new unit
For now move struct gk20a_fecs_trace_hash_ent to new unit and
rename it as struct nvgpu_fecs_trace_context_entry
Add vmid field to this struct since it is required for QNX
Remove use of hashtables and simply use linked list to simplify
the code. FECS tracing is not a performance sensitive use case
so perf hit could be ignored
Rename hash_lock mutex to list_lock
struct gk20a_fecs_trace and mutex list_lock are still declared in
gk20a/fecs_trace_gk20a.c, hence they cannot be used in new unit yet
Rename and update all gk20a_fecs_trace_hash_*() APIs to appropriate
nvgpu_gr_fecs_trace_*() APIs
Remove gk20a_fecs_trace_hash_dump() since it is not being used
Jira NVGPU-1880
Change-Id: I89c2715baa770dbbd864ea70ab43d83d98ba693c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022903
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gk20a_fecs_trace_poll() right now calls gk20a_fecs_trace_ring_read()
to read the trace ring buffer written by FECS
gk20a_fecs_trace_ring_read() returns number of trace entries written
to local buffer if successful, otherwise returns error
In case there is really an invalid entry, gk20a_fecs_trace_poll()
will just stop reading more entries, write current read pointer to
h/w and return
When gk20a_fecs_trace_poll() is called next time, we again read that
invalid entry, and again skip it, and again return
This keeps happening, and we never move on to read new entries
Fix this by always continuing to read next entry irrespective
of current entry is valid or not
gk20a_fecs_trace_poll() now just prints a debug message instead of
breaking the loop
Bug 200491708
Change-Id: I8cf823d7dc5f72ebd70cab2f115af32f3d20ac78
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2020167
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Create a new directory fifo under common vgpu path moving all
vgp common fifo files under that directory.
Move vgpu runlist implementations to a new file runlist_vgpu.c
and create corresponding header file.
Also fix lines over 80 chars in fifo_vgpu.c
Jira GVSCI-334
Change-Id: Ic00535b22a6066a0d27435b9a987de7fa701ea05
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011762
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Renamed gr_gk20a zbc hal functions which involve register access as
gk20a_gr_zbc* hal functions.
gr_gk20a_add_zbc_color -> gk20a_gr_zbc_add_color
gr_gk20a_add_zbc_depth -> gk20a_gr_zbc_add_depth
gr_gk20a zbc hal functions without any register access are renamed as
common function as nvgpu_gr_zbc*
gk20a_gr_zbc_set_table -> nvgpu_gr_zbc_set_table
gr_gk20a_query_zbc -> nvgpu_gr_zbc_query_table
Renamed gr_gp10b zbc hal functions as gp10b_gr_zbc* hal functions.
gr_gp10b_add_zbc_color -> gp10b_gr_zbc_add_color
gr_gp10b_add_zbc_depth -> gp10b_gr_zbc_add_depth
gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg ->
gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg
gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg ->
gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg
common code added for nvgpu_gr_zbc_add_color and
nvgpu_gr_zbc_add_depth which update ltc, update local copy
and call add_color or add_depth hal function
All these functions will be moved to common/gr/zbc location
in future updates.
gk20a_writel replaced with nvgpu_writel function.
JIRA NVGPU-1882
Change-Id: I717739e0b20c243e8f5ed3e00f8f76755587bcee
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018737
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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As part of creating zbc as gr subunit, move pmu_save hal function
from zbc to pmu hal.
This hal function is used to pass the information to gpmu
firmware, which should reside as part of pmu.
remove pmu_save hal from zbc.
add save_zbc hal under pmu.
remove unused function gr_gk20a_pmu_save_zbc
JIRA NVGPU-1882
Change-Id: I132dbc7a9ee9755043cd08f288344df447e28af6
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018581
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- "nvgpu_rmos/include" path is recently added in Makefile
under NV_COMPONENT_INCLUDES. atomic.h file is also present in
the same path.
- This atomic.h is conflicting with QNX OS's atomic.h which
needs to be included in some components.
- Hence, renaming atomic.h to rmos_atomic.h
Bug 200475265
Change-Id: I2a5c28157d1cf388a526765b688c3fe56a666a09
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2021821
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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MISRA Rule 10.3 does not allow value of expression to be assigned to
an object with a narrower essential type or to a different essential
type category.
Fix such 10.3 violations in nvlink code by type-casting (when sure
there will be no overflows) or by changing the data-type of variables
JIRA NVGPU-1921
Change-Id: Iab103a7f0c23cf2a047152cbd76c0b55b3cc947c
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012811
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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queue specific sources should use general logging interfaces like
nvgpu_err, nvgpu_log_info and not PMU specific nvgpu_pmu_dbg. With
this we can remove pmu.h inclusion in engine_mem_queue.c and
engine_fb_queue.c. This uncovers some new header inclusions
that we have to do for compilation of both these files.
More cleanup of PMU fields and related headers to follow.
JIRA NVGPU-1994
Change-Id: I728746094de85f338fcae940f10ee1731d397048
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019415
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Some of the engine queue related defines are shared by PMU, SEC2 and
queue implementations and currently in gpmuif_cmn.h. Let us add
engine_queue.h header file to club all those defines together.
JIRA NVGPU-1994
Change-Id: I57a889e6d14d954d2660e513994bb87cbb1e5824
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019414
GVS: Gerrit_Virtual_Submit
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With engine queues implementations now isolated from falcon unit let us
move it to common with following units in the sources:
1. nvgpu.common.engine_queues.mem_queues.mem_queue
2. nvgpu.common.engine_queues.mem_queues.emem_queue
3. nvgpu.common.engine_queues.mem_queues.dmem_queue
4. nvgpu.common.engine_queues.fb_queue
5. nvgpu.common.falcon.falcon
6. nvgpu.common.hal.falcon
File/folder names are prepended with "engine_" for better understanding.
JIRA NVGPU-1994
Change-Id: I02b06f134e964b0ec665208ae4e08ae65504ed4e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016291
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engine queue head and tail methods were retrieved from falcon structure.
engine queue initialization can get these methods directly from hal
through params. Also eliminate struct nvgpu_falcon dereference in engine
queue sources to remove inclusion of falcon_priv.h.
JIRA NVGPU-1994
Change-Id: Idbebd5049cfd14eb3fe0e27b2bef8436cc61e101
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016290
GVS: Gerrit_Virtual_Submit
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As we plan to move the queue implementations out of falcon unit let us
rename these as:
1. engine_mem_queue - Generic implementation.
2. engine_dmem_queue - DMEM queue implementation of engine_mem_queue.
3. engine_emem_queue - EMEM queue implementation of engine_mem_queu.
4. engine_fb_queue - FB queue implementation.
JIRA NVGPU-1994
Change-Id: Ic81dcc154b3383d9f75fe57cc01269bda2698b25
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016288
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FB queues handling is different from DMEM/EMEM queues in many aspects.
For e.g. no rewind required, additional queue struct fields, additional
queue operations required only for FB queues, push/pop semantics are
different.
Hence prepare separate structure and APIs for FB queues. PMU will have
to deal with the queue implementation chosen. This patch does the follo-
wing:
1. Update function/structure names to falcon_fb_queue_<op/name>.
2. Export nvgpu_falcon_fb_queue_* structure and functions.
3. Removed rewind function pointer and used direct functions for push,
pop and has_room.
4. PMU wrapper defined to use appropriate queue for empty check -
nvgpu_pmu_queue_is_empty.
5. PMU side updates for handling the work buffer and SEC2 updates for
usage of public queue functions.
JIRA NVGPU-1994
Change-Id: Ia5e40384e6e3f9e81d5dbc3d8138eb091337c086
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016285
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