Timeslice mode is always set to enabled. So, it is not
required to check for timeslice mode enable and done
following cleanup as part of this change.
1. Removed timeslice_mode field from struct gr_gk20a and
removed setting of this field from the function
gr_gk20a_init_gr_config.
2. Removed checks for timeslice_mode enable in
gr_gk20a_commit_global_timeslice function.
3. Removed unused kernel definitions from headers:
gr_gpcs_ppcs_cbm_cfg_r()
gr_gpcs_ppcs_cbm_cfg_timeslice_mode_enable_v()
JIRA NVGPU-2155
Change-Id: Id99f4b771c74f4cea763ea63441043e93def2347
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Id99f4b771c74f4cea763ea63441043e93def2347
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024320
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gm20b clocks is accessing thermal registers directly in several places.
Moved all this code to thermal unit and clock code is accessing these
through provided thermal hal functions.
Following new hal are defined in thermal unit for enabling/disabling
throttling and enabling/disabling idle slowdown:
void (*throttle_enable)(struct gk20a *g, u32 val);
int (*throttle_disable)(struct gk20a *g);
void (*idle_slowdown_enable)(struct gk20a *g, u32 val);
int (*idle_slowdown_disable)(struct gk20a *g);
At this moment, these hals are getting used only by gm20b code.
JIRA NVGPU-2001
Change-Id: I937a7c76dfae9aa7e86f23c53f84fae9a9dda13e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2023289
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The type for the timeout parameter to the NVGPU_COND_WAIT and
NVGPU_COND_WAIT_INTERRUPTIBLE macros was too weak. This updates these
macros to require a u32 for the timeout.
Users of the macros are updated to be compliant as necessary.
This addresses MISRA 10.3 violations for implicit conversions of types
of different size or essential type.
JIRA NVGPU-1008
Change-Id: I12368dfa81b137c35bd056668c1867f03a73b7aa
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017503
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Add zbc stencil as chip feature. This help to remove the
hals added for stencil feature, instead use common functions.
Removed hals
stencil_query_table
load_stencil_default_tbl
add_type_stencil
load_stencil_tbl
JIRA NVGPU-1882
Change-Id: Iae410a8dd879660ecfd2d2a5ebf28b2cc8309be4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022385
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The unit_id is a u8, but the macros defining the different unit ids as
u32s in the header file. This causes MISRA 10.3 violations for
implicitly assigning objects of different size. So, this change makes
the header declarations u8s to avoid the 10.3 violations.
JIRA NVGPU-1008
Change-Id: I9790793b43d1d710941d8da2e6e97f07bc44e30c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017607
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Update the nvgpu_request_firmware API to use u32 for the flags
parameter. The API previously defined the flags parameter to be an int.
However, the flags were defined as UL. This was causing MISRA 10.3
violations for implicitly assigning an object of different essential
type. So, this change makes all definitions a u32.
JIRA NVGPU-1008
Change-Id: I09eb75d4e2a20e7ac6dba80d3bc06335d3c78d62
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2023223
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Previously, BITS_TO_LONGS macro had calculation bug due to incorrect
ordering of parantheses. This patch rearranges the parantheses to
correctly convert specified bits to nearest higher multiple of unsigned
long.
Change-Id: I296da2a2ebd805325189f956089ac201aa5b04d8
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024034
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Create new gr/fecs_trace unit with common/gr/fecs_trace/fecs_trace.c
as common source file and include/nvgpu/gr/fecs_trace.h as common
header file
This unit will be common between Linux and QNX
Corresponding HAL files will be added under common/gr/fecs_trace/
as more functionality is moved to new unit
For now move struct gk20a_fecs_trace_hash_ent to new unit and
rename it as struct nvgpu_fecs_trace_context_entry
Add vmid field to this struct since it is required for QNX
Remove use of hashtables and simply use linked list to simplify
the code. FECS tracing is not a performance sensitive use case
so perf hit could be ignored
Rename hash_lock mutex to list_lock
struct gk20a_fecs_trace and mutex list_lock are still declared in
gk20a/fecs_trace_gk20a.c, hence they cannot be used in new unit yet
Rename and update all gk20a_fecs_trace_hash_*() APIs to appropriate
nvgpu_gr_fecs_trace_*() APIs
Remove gk20a_fecs_trace_hash_dump() since it is not being used
Jira NVGPU-1880
Change-Id: I89c2715baa770dbbd864ea70ab43d83d98ba693c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022903
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As part of creating zbc as gr subunit, move pmu_save hal function
from zbc to pmu hal.
This hal function is used to pass the information to gpmu
firmware, which should reside as part of pmu.
remove pmu_save hal from zbc.
add save_zbc hal under pmu.
remove unused function gr_gk20a_pmu_save_zbc
JIRA NVGPU-1882
Change-Id: I132dbc7a9ee9755043cd08f288344df447e28af6
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018581
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- "nvgpu_rmos/include" path is recently added in Makefile
under NV_COMPONENT_INCLUDES. atomic.h file is also present in
the same path.
- This atomic.h is conflicting with QNX OS's atomic.h which
needs to be included in some components.
- Hence, renaming atomic.h to rmos_atomic.h
Bug 200475265
Change-Id: I2a5c28157d1cf388a526765b688c3fe56a666a09
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2021821
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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MISRA Rule 10.3 does not allow value of expression to be assigned to
an object with a narrower essential type or to a different essential
type category.
Fix such 10.3 violations in nvlink code by type-casting (when sure
there will be no overflows) or by changing the data-type of variables
JIRA NVGPU-1921
Change-Id: Iab103a7f0c23cf2a047152cbd76c0b55b3cc947c
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012811
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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Some of the engine queue related defines are shared by PMU, SEC2 and
queue implementations and currently in gpmuif_cmn.h. Let us add
engine_queue.h header file to club all those defines together.
JIRA NVGPU-1994
Change-Id: I57a889e6d14d954d2660e513994bb87cbb1e5824
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019414
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engine queue head and tail methods were retrieved from falcon structure.
engine queue initialization can get these methods directly from hal
through params. Also eliminate struct nvgpu_falcon dereference in engine
queue sources to remove inclusion of falcon_priv.h.
JIRA NVGPU-1994
Change-Id: Idbebd5049cfd14eb3fe0e27b2bef8436cc61e101
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016290
GVS: Gerrit_Virtual_Submit
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As we plan to move the queue implementations out of falcon unit let us
rename these as:
1. engine_mem_queue - Generic implementation.
2. engine_dmem_queue - DMEM queue implementation of engine_mem_queue.
3. engine_emem_queue - EMEM queue implementation of engine_mem_queu.
4. engine_fb_queue - FB queue implementation.
JIRA NVGPU-1994
Change-Id: Ic81dcc154b3383d9f75fe57cc01269bda2698b25
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016288
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FB queues handling is different from DMEM/EMEM queues in many aspects.
For e.g. no rewind required, additional queue struct fields, additional
queue operations required only for FB queues, push/pop semantics are
different.
Hence prepare separate structure and APIs for FB queues. PMU will have
to deal with the queue implementation chosen. This patch does the follo-
wing:
1. Update function/structure names to falcon_fb_queue_<op/name>.
2. Export nvgpu_falcon_fb_queue_* structure and functions.
3. Removed rewind function pointer and used direct functions for push,
pop and has_room.
4. PMU wrapper defined to use appropriate queue for empty check -
nvgpu_pmu_queue_is_empty.
5. PMU side updates for handling the work buffer and SEC2 updates for
usage of public queue functions.
JIRA NVGPU-1994
Change-Id: Ia5e40384e6e3f9e81d5dbc3d8138eb091337c086
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016285
GVS: Gerrit_Virtual_Submit
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A new unit pbdma_status is added. The unit provides a HAL
ops function pointer read_pbdma_status_info() to read and produce
a struct of type nvgpu_pbdma_status_info. Additionally, the unit
provides public APIs to retrieve data from the struct
nvgpu_pbdma_status_info.
Jira NVGPU-1311
Change-Id: Ic89c78703c3738b91be8d18ba970a591658d4022
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2019976
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Changes:
1) Separated clk.h which is in /nvgpu/include/pmu
into different units
2) Renamed global functions
Intention: At present /nvgpu/include/pmu/clk.h
consists of structures and functions of different
clock units. It is difficult to work on individual
clk units if this file is not separated into
individual units. All stucts and functions in clk.h
are seperated into different clk units.
Individual private clk units were not touched.
Post this patch, the sebsequent patches would make
changes in the individual clk units.
NVGPU-2707
Change-Id: I7bf9fab38a73bceb451291530a67c70ed343b0cb
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2021704
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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Move ACR code to separate folder under common/acr to
make ACR separate unit. with this, separating ACR blob
construct, bootstrap & ACR chip specific configuration
code to different files.
ACR blob construction code split into two version, as
gm20b & gp10b still uses older ACR interfaces & not yet
moved to Tegra ACR, blob_construct_v0 file can be deleted
once gm20b/gp10b uses Tegra ACR ucode & point to
blob_construct_v1 with simple change.
As ACR ucode can execute on different engine falcon &
should not be dependent on specific engine falcon, used
generic falcon functions/interface to support ACR & doesn't
access any engine h/w registers directly, and files with
chip name has configuration needed for ACR HS ucode & LS
falcons.
JIRA NVGPU-1148
Change-Id: Ieedbe82f3e1a4303f055fbc795d9ce0f1866d259
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017046
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The following changes are done in this patch.
1) gk20a_fifo_get_engine_info() is moved to common/fifo/engine.c
and is renamed to gk20a_fifo_get_active_engine_info() to reflect
accurately the purpose of the function.
2) move the definition of enum fifo_engine to <nvgpu/engines.h> and
add the prefix NVGPU_
3) move the following functions related to engines in fifo_gk20a.c to
common/fifo/engines.c and replace their signature by adding the prefix
nvgpu_engine and removing gk20a_fifo.
gk20a_fifo_get_active_engine_info
gk20a_fifo_engine_enum_from_type
gk20a_fifo_get_engine_ids
gk20a_fifo_is_valid_engine_id
gk20a_fifo_get_gr_engine_id
gk20a_fifo_act_eng_interrupt_mask
gk20a_fifo_engine_interrupt_mask
gk20a_fifo_get_all_ce_engine_reset_mask
Jira NVGPU-1315
Change-Id: I63d9dcd905a0bebcc9a4c65776cf6ec7a0837acf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011298
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Drop the "runlist_" part in the runlist section of the HAL ops. For
example:
- old: g->ops.runlist.runlist_wait_pending
- new: g->ops.runlist.wait_pending
At the same time, drop the "fifo_" part from the function names. For
example:
- old: gk20a_fifo_runlist_wait_pending
- new: gk20a_runlist_wait_pending
Also rename eng_runlist_base_size to count_max. The size of the
eng_runlist_base register array depicts the maximum possible number of
runlists in the chip for which count_max is more descriptive.
Jira NVGPU-1309
Change-Id: Ie9e94b9f65cd10d3e682d19954f240adb6e311be
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017403
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Since we plan to separate engine DMEM/EMEM and FB queues into separate
implementations, let's make the engine queue_head and queue_tail APIs
independent of nvgpu_falcon_queue parameter.
JIRA NVGPU-1994
Change-Id: I389cc48d4045d9df8f768166f6a1d7074a69a309
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016283
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We get gpc_mask by calling GR HAL g->ops.gr.get_gpc_mask()
But gpc_mask should be logically owned by gr/config unit
Hence add new gpc_mask field to nvgpu_gr_config
Initialize it in nvgpu_gr_config_init() by calling a new HAL
g->ops.gr.config.get_gpc_mask() if available
If HAL is not defined we just initialize it based on gpc_count
Expose new API nvgpu_gr_config_get_gpc_mask() to get gpc_mask
and use this API now
Remove gr_gm20b_get_gpc_mask() and HAL g->ops.gr.get_gpc_mask()
Update GV100 and TU104 chip HALs to remove old and add new HAL
Add gpc_mask to struct tegra_vgpu_constants_params to support this
on vGPU. Also get gpc_mask from vGPU private data in
vgpu_gr_init_gr_config()
Jira NVGPU-1879
Change-Id: Ibdc89ea51df944dc7085920509e3536a5721efc0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016084
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Unit gr/config right now queries gpc_count from priv_ring by directly
reading the value from register
priv_ring unit now exposes below HAL to get gpc_count
g->ops.priv_ring.get_gpc_count()
Use this HAL in gr/config unit
Jira NVGPU-1879
Change-Id: Ibd3557b7f906690a7ad18f11d02a0a6990b98337
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016083
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In gr/config unit we right now query max gpc_count and tpc_per_gpc_count
by directly accessing registers using hw_top_gm20b.h h/w header
Update TOP unit to provide below HALs
g->ops.top.get_gpc_count()
g->ops.top.get_tpc_per_gpc_count()
And call these HALs from gr/config
Jira NVGPU-1879
Change-Id: I39f5d3bb80960d68a1f493b372745e964ad82803
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016082
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A new unit nvgpu_engine_status_info is added. The unit provides a HAL
ops function pointer read_engine_status_info() to read and produce
a struct of type nvgpu_engine_status_info. Additionally, the unit
provides public APIs to retrieve data from the struct
nvgpu_engine_status_info.
Jira NVGPU-1315
Change-Id: I6c167c36081bee5c9a8db51d3467c8f5f02c2685
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2003886
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Add a HAL op for resetting the eng_faulted and pbdma_faulted states on a
channel. This used to be a local feature in fifo_gv11b.c; the HAL is
defined for all chips from gv11b onwards.
Jira NVGPU-1307
Change-Id: I120a59c429851cc69e712ddd5b06a4b3d16c06c9
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017269
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Refactor read accesses to the ccsr_channel register for channel state to
be done via a channel HAL op for all chips. A new op called read_state
is added for this; information needed by other units is collected in a
new struct nvgpu_channel_hw_state.
Jira NVGPU-1307
Change-Id: Iff9385c08e17ac086d97f5771a54b56b2727e3c4
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017266
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Split out ops that belong to channel unit to a new section called
channel. Channel is a broad concept; this includes just the code that
accesses channel registers (ccsr_*). This is effectively just renaming;
the implementation still stays put.
The word "channel" is also dropped from certain HAL entries to avoid
redundancy (e.g., channel.disable_channel -> channel.disable).
fifo.get_num_fifos gets an entirely new name: channel.count.
Jira NVGPU-1307
Change-Id: I9a08103e461bf3ddb743aa37ababee3e0c73c861
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017261
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Currently clk_arb needs PSTATE to be true for dGPU.
Setting PSTATE only FALSE, causes issue as clk_arb fails.
There is no such dependency of PSTATE on iGPU.
Making it unified with a call to check_clk_arb_support().
This call is implemented based on its dependency in iGPU, dGPU.
check_clk_arb_support returns true if supported, else false.
Jira NVGPU-1948
Change-Id: I108dc12bd6ad8d0e074352080c978b7dda9bee05
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014775
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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