emem related handling is specific to DGPU hence compile it out.
falcon_sw_init for platforms other than gv11b is also compiled
out.
Restored the DGPU falcons handling as the falcon common sw
init handling has case for initialization of unsupported
falcons that needs to be covered.
JIRA NVGPU-898
Change-Id: I41e886aba2aead052f3ef00278309759dd410df3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2160233
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- Added version and reseved elements in
nv_pmu_clk_clk_vin_device_boardobjgrp_set_header struct.
- Added volt_rail_idx, por_override_mode and override_mode
elements are added in nv_pmu_clk_clk_vin_device_boardobj_set
struct.
- Implemented parsing the above elements from vbios table.
- Moved from cmd to rpc in vin_load function.
- Changed the global macros of clk domain which matches to
PMU firmware for easy reference.
NVGPU-3743
Change-Id: I0189548fce19d65193203fbf6317c4a04147bf5a
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2163135
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-dGPU PMU init message interface updated to support RPC style init
PMU init message changed to RPC event & made needed changes to
handle RPC event during init stage
-Added new RPC header PMU_RM_RPC_HEADER, header from PMU to NvGPU
which will be part of RPC events received from PMU.
-GID info moved to super-surface for dGPU, so removed GID info
fetch from DMEM for dGPU & kept support for iGPU only.
-PMU_UNIT_INIT value for dGPU init changed
JIRA NVGPU-3723
Change-Id: I016bd1150494007a56905db23b4769e693ecd5da
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153141
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-Message header is added as part of FB message queue to have
sequence number & checksum to perform sanity check on
received message.
-Made required changes in structs to read message correctly
from data member offset but skipped to handle sanity checks
in code as NvGPU not needed for current supported messages .
-Added support to handle cmd/msg queue element changes.
JIRA NVGPU-3724
Change-Id: I85dccfab8902cbf71752582666931f482c3ec408
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155165
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Reduce code complexity of following functions in common.gr.intr
nvgpu_gr_intr_stall_isr(complexity : 33)
nvgpu_gr_intr_handle_sm_exception(complexity : 17)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create five sub functions from nvgpu_gr_intr_stall_isr function.
Four of the sub functions based interrupt types.
One sub function for getting the channel information from context
gr_intr_get_channel_from_ctx(complexity : 4)
gr_intr_handle_exception_interrupts(complexity : 11)
This function complexity will reduce with NVGPU_DEBUGGER disable
gr_intr_handle_illegal_interrupts(complexity : 5)
gr_intr_handle_error_interrupts(complexity : 7)
gr_intr_handle_pending_interrupts(complexity : 3)
and reduce nvgpu_gr_intr_stall_isr complexity to 9
Create one sub functions from nvgpu_gr_intr_handle_sm_exception function
One sub function to report back any warp error.
gr_intr_report_warp_error(with complexity : 3)
and reduce nvgpu_gr_intr_handle_sm_exception complexity to 15
This function complexity will reduce with NVGPU_DEBUGGER disable
Jira NVGPU-3662
Change-Id: Ib325d9d8bca6b48766bc8a75f428dceeac495850
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2160578
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This patch adds the support to handle and report graphics related
exceptions to 3LSS. Specifically, it adds the following exceptions:
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_CROP
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_ZROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZCULL
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_SETUP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES0
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES1
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_PE
JIRA NVGPU-3457
Change-Id: Ib24b67ed33ae139317ec85bba3fbb80ba51fd384
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
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This patch reverts the following commit 13a7ef2cc7
The bios devinit for tu104 encountered the unaligned buffer scenario.
However bios devinit functionality is now removed from nvgpu. Other
than that there are no firmwares where we expect the input/output
buffer addresses to be un-aligned, hence removing the logic added
to handle un-aligned addresses.
JIRA NVGPU-3271
Change-Id: Ifd24cc5b50b9d2548878436befb2220e7bf02ed4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161735
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The following DEVCTLs not needed in safety build
Compiled out below DEVCTLs for safety build
* NVGPU_GPU_DEVCTL_SET_THERM_ALERT_LIMIT
* NVGPU_GPU_DEVCTL_GET_TPC_EXCEPTION_EN_STATUS
* NVGPU_GPU_DEVCTL_GET_CPU_TIME_CORRELATION_INFO
Also added config flag CONFIG_NVGPU_IOCTL_NON_FUSA
JIRA NVGPU-3768
Change-Id: Ia233d0aac8201268524581f588d97390a913ab9c
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159398
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This change switches nvgpu_timeout_peek_expired() to return a bool
instead of an int to remove advisory rule MISRA 10.5 violations.
MISRA 10.5 states that the value of an expression should not be
cast to an inappropriate essential type.
JIRA NVGPU-3798
Change-Id: I5cf9badaf07493e11a639e47ae4cf221700134ff
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155617
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There was a name clash between the nvgpu_set_error_notifier*() APIs and
the SET_ERROR_NOTIFIER IOCTL. Therefore, the APIs were renamed from
nvgpu_set_error_notifier*() to nvgpu_set_err_notifier*(). This rename
was done to fix MISRA 5.x errors.
JIRA NVGPU-1633
Change-Id: I06af551a664b0706f106e853f1ea8733894f11bd
Signed-off-by: Adeel Raza <araza@nvidia.com>
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INT-30 requires checking for overflow of arithmetic operations on
unsigned integers.
INT-31 requires bounds checking for unsigned integers cast to
smaller size.
Fix these violations by using the safe ops in nvgpu.common.mm.mm and
nvgpu.hal.mm.mm.
JIRA NVGPU-3848
Change-Id: I2751a14fb1f45d330a92040ac3c7777c52ae9199
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158860
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Following common and corresponding hal functions are non-safe. They are
either required for intr handling or for debug. Compile them out for
igpu safety release. Moved corresponding HALs to falcon_gk20a.c.
nvgpu_falcon_copy_from_emem
nvgpu_falcon_copy_to_emem
nvgpu_falcon_clear_halt_intr_status
nvgpu_falcon_set_irq
nvgpu_falcon_copy_from_dmem
nvgpu_falcon_copy_from_imem
nvgpu_falcon_print_dmem
nvgpu_falcon_print_imem
nvgpu_falcon_get_ctls
nvgpu_falcon_dump_stats can be used in the safety debug build.
JIRA NVGPU-898
JIRA NVGPU-2214
Change-Id: Icb7f904b088aa74b976f75a6a0ecdb783486bab3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152978
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MISRA Advisory Rule 10.5 states that the value of an expression should
not be cast to an inappropriate essential type.
This change removes five violations of this rule that involve casting
boolean results to unsigned values:
* pass 1/0 (instead of true/false) to nvgpu_atomic operations
* fix skip_mask handling in gm20b_gr_init_pd_skip_table_gpc()
* fix l3_alloc flags check in nvgpu_gmmu_map_locked()
This change also eliminates several MISRA Advisory Rule 4.6 violations.
JIRA NVGPU-3798
Change-Id: I707da8a812bfb32eaeb2200463885c0961b197b3
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153070
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Add BLCG and SLCG clock gating support for HSHUB unit on gv11b and tu104
Register list for BLCG and SLCG is auto generated with scripts.
Add HAL operations to enable/disable HSHUB clock gating
Re-generate gv11b reglist so that all the manually commented registers
are automatically deleted. Some of the unicast registers are also
deleted. We already have corresponding broadcast registers present.
Bug 2526212
Change-Id: I2654f158daa802bcf992e103ed4a44675aa5fd4d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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- Rule 5.7 doesn't allow an identifier to be reused. This patch renames
identifier 'notification' to resolve this violation.
- Rule 8.3 requires all functions and prototypes to have same parameter
names and type qualifier.
- Rule 10.x necessitates operands to have essential type, and left and
right operands should be of same width.
- Rule 11.9 requires pointers to be compared with 'NULL' instead of '0'.
- Rule 14.4 requires if statement condition to be Boolean type.
- Rule 15.7 needs if-elseif constructs to be terminated with else
statement.
- Rule 16.x requires all switch statements to be well-formed with
unconditional break statement terminate every switch-clause.
- Rule 20.7 requires macro parameters to be enclosed in parentheses.
- Rule 21.x doesn't allow reserved identifier or macro names to be
reused or defined.
This patch fixes above listed violations in common/clk_arb/clk_arb.c.
Jira NVGPU-3740
Change-Id: I871ce240ca7fb0372240a8886a53c8d4c460acea
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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