[P3762/P3783]:Virtual i2c mux support all Hawks

Add virtual i2c bus support for 2nd,3rd & 4th Hawks
to read/write EEPROM data while streaming

Bug 4807682

Change-Id: I76e4a1128a66f22d13f7ee2c04c64d42da519080
Signed-off-by: Praveen AC <pac@nvidia.com>
(cherry picked from commit e96aba03cf)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3258815
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ankur Pawar <ankurp@nvidia.com>

Makefile

@@ -7,8 +7,10 @@ dtbo-y :=
 makefile-path := t23x/nv-public
 
 dtb-y += tegra234-p3737-0000+p3701-0000.dtb
+dtb-y += tegra234-p3737-0000+p3701-0008.dtb
 dtb-y += tegra234-p3740-0002+p3701-0008.dtb
 dtb-y += tegra234-p3768-0000+p3767-0000.dtb
+dtb-y += tegra234-p3768-0000+p3767-0005.dtb
 
 ifneq ($(dtb-y),)
 dtb-y := $(addprefix $(makefile-path)/,$(dtb-y))

OWNERS

@@ -0,0 +1,16 @@
+# SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+# SPDX-License-Identifier: LicenseRef-NvidiaProprietary
+#
+# NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
+# property and proprietary rights in and to this material, related
+# documentation and any modifications thereto. Any use, reproduction,
+# disclosure or distribution of this material and related documentation
+# without an express license agreement from NVIDIA CORPORATION or
+# its affiliates is strictly prohibited.
+
+# Top-level directory owners:
+ldewangan@nvidia.com
+
+# Do not uncomment: Not supported in OWNERS file, added for additional info
+#{NVBUGS_MODULE=<to-be-updated-by-owner>}
+#{OWNERS_DL=<to-be-updated-by-owner>}

include/kernel/dt-bindings/clock/tegra234-clock.h

@@ -1,903 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
-
-#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
-#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
-
-/**
- * @file
- * @defgroup bpmp_clock_ids Clock ID's
- * @{
- */
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */
-#define TEGRA234_CLK_ACTMON			1U
-/** @brief output of gate CLK_ENB_ADSP */
-#define TEGRA234_CLK_ADSP			2U
-/** @brief output of gate CLK_ENB_ADSPNEON */
-#define TEGRA234_CLK_ADSPNEON			3U
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
-#define TEGRA234_CLK_AHUB			4U
-/** @brief output of gate CLK_ENB_APB2APE */
-#define TEGRA234_CLK_APB2APE			5U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
-#define TEGRA234_CLK_APE			6U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
-#define TEGRA234_CLK_AUD_MCLK			7U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
-#define TEGRA234_CLK_AXI_CBB			8U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
-#define TEGRA234_CLK_CAN1			9U
-/** @brief output of gate CLK_ENB_CAN1_HOST */
-#define TEGRA234_CLK_CAN1_HOST			10U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
-#define TEGRA234_CLK_CAN2			11U
-/** @brief output of gate CLK_ENB_CAN2_HOST */
-#define TEGRA234_CLK_CAN2_HOST			12U
-/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
-#define TEGRA234_CLK_CLK_M			14U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
-#define TEGRA234_CLK_DMIC1			15U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
-#define TEGRA234_CLK_DMIC2			16U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
-#define TEGRA234_CLK_DMIC3			17U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
-#define TEGRA234_CLK_DMIC4			18U
-/** @brief output of gate CLK_ENB_DPAUX */
-#define TEGRA234_CLK_DPAUX			19U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG1 */
-#define TEGRA234_CLK_NVJPG1			20U
-/**
- * @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY
- * divided by the divider controlled by ACLK_CLK_DIVISOR in
- * CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER
- */
-#define TEGRA234_CLK_ACLK			21U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT switch divider output */
-#define TEGRA234_CLK_MSS_ENCRYPT		22U
-/** @brief clock recovered from EAVB input */
-#define TEGRA234_CLK_EQOS_RX_INPUT		23U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB switch divider output */
-#define TEGRA234_CLK_AON_APB			25U
-/** @brief CLK_RST_CONTROLLER_AON_NIC_RATE divider output */
-#define TEGRA234_CLK_AON_NIC			26U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC switch divider output */
-#define TEGRA234_CLK_AON_CPU_NIC		27U
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
-#define TEGRA234_CLK_PLLA1			28U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
-#define TEGRA234_CLK_DSPK1			29U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
-#define TEGRA234_CLK_DSPK2			30U
-/**
- * @brief controls the EMC clock frequency.
- * @details Doing a clk_set_rate on this clock will select the
- * appropriate clock source, program the source rate and execute a
- * specific sequence to switch to the new clock source for both memory
- * controllers. This can be used to control the balance between memory
- * throughput and memory controller power.
- */
-#define TEGRA234_CLK_EMC			31U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
-#define TEGRA234_CLK_EQOS_AXI			32U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
-#define TEGRA234_CLK_EQOS_PTP_REF		33U
-/** @brief output of gate CLK_ENB_EQOS_RX */
-#define TEGRA234_CLK_EQOS_RX			34U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */
-#define TEGRA234_CLK_EQOS_TX			35U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
-#define TEGRA234_CLK_EXTPERIPH1			36U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
-#define TEGRA234_CLK_EXTPERIPH2			37U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
-#define TEGRA234_CLK_EXTPERIPH3			38U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
-#define TEGRA234_CLK_EXTPERIPH4			39U
-/** @brief output of gate CLK_ENB_FUSE */
-#define TEGRA234_CLK_FUSE			40U
-/** @brief output of GPU GPC0 clkGen (in 1x mode same rate as GPC0 MUX2 out) */
-#define TEGRA234_CLK_GPC0CLK			41U
-/** @brief TODO */
-#define TEGRA234_CLK_GPU_PWR			42U
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
-#define TEGRA234_CLK_HOST1X			46U
-/** @brief xusb_hs_hsicp_clk */
-#define TEGRA234_CLK_XUSB_HS_HSICP		47U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
-#define TEGRA234_CLK_I2C1			48U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
-#define TEGRA234_CLK_I2C2			49U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
-#define TEGRA234_CLK_I2C3			50U
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
-#define TEGRA234_CLK_I2C4			51U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
-#define TEGRA234_CLK_I2C6			52U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
-#define TEGRA234_CLK_I2C7			53U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
-#define TEGRA234_CLK_I2C8			54U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
-#define TEGRA234_CLK_I2C9			55U
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
-#define TEGRA234_CLK_I2S1			56U
-/** @brief clock recovered from I2S1 input */
-#define TEGRA234_CLK_I2S1_SYNC_INPUT		57U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
-#define TEGRA234_CLK_I2S2			58U
-/** @brief clock recovered from I2S2 input */
-#define TEGRA234_CLK_I2S2_SYNC_INPUT		59U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
-#define TEGRA234_CLK_I2S3			60U
-/** @brief clock recovered from I2S3 input */
-#define TEGRA234_CLK_I2S3_SYNC_INPUT		61U
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
-#define TEGRA234_CLK_I2S4			62U
-/** @brief clock recovered from I2S4 input */
-#define TEGRA234_CLK_I2S4_SYNC_INPUT		63U
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
-#define TEGRA234_CLK_I2S5			64U
-/** @brief clock recovered from I2S5 input */
-#define TEGRA234_CLK_I2S5_SYNC_INPUT		65U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */
-#define TEGRA234_CLK_I2S6			66U
-/** @brief clock recovered from I2S6 input */
-#define TEGRA234_CLK_I2S6_SYNC_INPUT		67U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
-#define TEGRA234_CLK_ISP			69U
-/** @brief Monitored branch of EQOS_RX clock */
-#define TEGRA234_CLK_EQOS_RX_M			70U
-/** @brief CLK_RST_CONTROLLER_MAUDCLK_OUT_SWITCH_DIVIDER switch divider output (maudclk) */
-#define TEGRA234_CLK_MAUD			71U
-/** @brief output of gate CLK_ENB_MIPI_CAL */
-#define TEGRA234_CLK_MIPI_CAL			72U
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
-#define TEGRA234_CLK_MPHY_CORE_PLL_FIXED	73U
-/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
-#define TEGRA234_CLK_MPHY_L0_RX_ANA		74U
-/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
-#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT		75U
-/** @brief output of gate CLK_ENB_MPHY_L0_RX_SYMB */
-#define TEGRA234_CLK_MPHY_L0_RX_SYMB		76U
-/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
-#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT	77U
-/** @brief output of gate CLK_ENB_MPHY_L0_TX_SYMB */
-#define TEGRA234_CLK_MPHY_L0_TX_SYMB		78U
-/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
-#define TEGRA234_CLK_MPHY_L1_RX_ANA		79U
-/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
-#define TEGRA234_CLK_MPHY_TX_1MHZ_REF		80U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
-#define TEGRA234_CLK_NVCSI			81U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
-#define TEGRA234_CLK_NVCSILP			82U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
-#define TEGRA234_CLK_NVDEC			83U
-/** @brief CLK_RST_CONTROLLER_HUBCLK_OUT_SWITCH_DIVIDER switch divider output (hubclk) */
-#define TEGRA234_CLK_HUB			84U
-/** @brief CLK_RST_CONTROLLER_DISPCLK_SWITCH_DIVIDER switch divider output (dispclk) */
-#define TEGRA234_CLK_DISP			85U
-/** @brief RG_CLK_CTRL__0_DIV divider output (nvdisplay_p0_clk) */
-#define TEGRA234_CLK_NVDISPLAY_P0		86U
-/** @brief RG_CLK_CTRL__1_DIV divider output (nvdisplay_p1_clk) */
-#define TEGRA234_CLK_NVDISPLAY_P1		87U
-/** @brief DSC_CLK (DISPCLK ÷ 3) */
-#define TEGRA234_CLK_DSC			88U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
-#define TEGRA234_CLK_NVENC			89U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
-#define TEGRA234_CLK_NVJPG			90U
-/** @brief input from Tegra's XTAL_IN */
-#define TEGRA234_CLK_OSC			91U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH switch divider output */
-#define TEGRA234_CLK_AON_TOUCH			92U
-/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
-#define TEGRA234_CLK_PLLA			93U
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
-#define TEGRA234_CLK_PLLAON			94U
-/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
-#define TEGRA234_CLK_PLLE			100U
-/** @brief PLLP vco output */
-#define TEGRA234_CLK_PLLP			101U
-/** @brief PLLP clk output */
-#define TEGRA234_CLK_PLLP_OUT0			102U
-/** Fixed frequency 960MHz PLL for USB and EAVB */
-#define TEGRA234_CLK_UTMIP_PLL			103U
-/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
-#define TEGRA234_CLK_PLLA_OUT0			104U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
-#define TEGRA234_CLK_PWM1			105U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
-#define TEGRA234_CLK_PWM2			106U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
-#define TEGRA234_CLK_PWM3			107U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
-#define TEGRA234_CLK_PWM4			108U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
-#define TEGRA234_CLK_PWM5			109U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
-#define TEGRA234_CLK_PWM6			110U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
-#define TEGRA234_CLK_PWM7			111U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
-#define TEGRA234_CLK_PWM8			112U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_RCE_CPU_NIC output */
-#define TEGRA234_CLK_RCE_CPU_NIC		113U
-/** @brief CLK_RST_CONTROLLER_RCE_NIC_RATE divider output */
-#define TEGRA234_CLK_RCE_NIC			114U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW switch divider output */
-#define TEGRA234_CLK_AON_I2C_SLOW		117U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
-#define TEGRA234_CLK_SCE_CPU_NIC		118U
-/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
-#define TEGRA234_CLK_SCE_NIC			119U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
-#define TEGRA234_CLK_SDMMC1			120U
-/** @brief Logical clk for setting the UPHY PLL3 rate */
-#define TEGRA234_CLK_UPHY_PLL3			121U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
-#define TEGRA234_CLK_SDMMC4			123U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */
-#define TEGRA234_CLK_SE				124U
-/** @brief VPLL select for sor0_ref clk driven by disp_2clk_sor0_head_sel signal */
-#define TEGRA234_CLK_SOR0_PLL_REF		125U
-/** @brief Output of mux controlled by disp_2clk_sor0_pll_ref_clk_safe signal (sor0_ref_clk) */
-#define TEGRA234_CLK_SOR0_REF			126U
-/** @brief VPLL select for sor1_ref clk driven by disp_2clk_sor0_head_sel signal */
-#define TEGRA234_CLK_SOR1_PLL_REF		127U
-/** @brief SOR_PLL_REF_CLK_CTRL__0_DIV divider output */
-#define TEGRA234_CLK_PRE_SOR0_REF		128U
-/** @brief Output of mux controlled by disp_2clk_sor1_pll_ref_clk_safe signal (sor1_ref_clk) */
-#define TEGRA234_CLK_SOR1_REF			129U
-/** @brief SOR_PLL_REF_CLK_CTRL__1_DIV divider output */
-#define TEGRA234_CLK_PRE_SOR1_REF		130U
-/** @brief output of gate CLK_ENB_SOR_SAFE */
-#define TEGRA234_CLK_SOR_SAFE			131U
-/** @brief SOR_CLK_CTRL__0_DIV divider output */
-#define TEGRA234_CLK_SOR0_DIV			132U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
-#define TEGRA234_CLK_DMIC5			134U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
-#define TEGRA234_CLK_SPI1			135U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
-#define TEGRA234_CLK_SPI2			136U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI3 */
-#define TEGRA234_CLK_SPI3			137U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
-#define TEGRA234_CLK_I2C_SLOW			138U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
-#define TEGRA234_CLK_SYNC_DMIC1			139U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
-#define TEGRA234_CLK_SYNC_DMIC2			140U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
-#define TEGRA234_CLK_SYNC_DMIC3			141U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
-#define TEGRA234_CLK_SYNC_DMIC4			142U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
-#define TEGRA234_CLK_SYNC_DSPK1			143U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
-#define TEGRA234_CLK_SYNC_DSPK2			144U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
-#define TEGRA234_CLK_SYNC_I2S1			145U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
-#define TEGRA234_CLK_SYNC_I2S2			146U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
-#define TEGRA234_CLK_SYNC_I2S3			147U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
-#define TEGRA234_CLK_SYNC_I2S4			148U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
-#define TEGRA234_CLK_SYNC_I2S5			149U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
-#define TEGRA234_CLK_SYNC_I2S6			150U
-/** @brief controls MPHY_FORCE_LS_MODE upon enable & disable */
-#define TEGRA234_CLK_MPHY_FORCE_LS_MODE		151U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH0 */
-#define TEGRA234_CLK_TACH0			152U
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
-#define TEGRA234_CLK_TSEC			153U
-/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */
-#define TEGRA234_CLK_TSEC_PKA			154U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
-#define TEGRA234_CLK_UARTA			155U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
-#define TEGRA234_CLK_UARTB			156U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
-#define TEGRA234_CLK_UARTC			157U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
-#define TEGRA234_CLK_UARTD			158U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
-#define TEGRA234_CLK_UARTE			159U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
-#define TEGRA234_CLK_UARTF			160U
-/** @brief output of gate CLK_ENB_PEX1_CORE_6 */
-#define TEGRA234_CLK_PEX1_C6_CORE		161U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
-#define TEGRA234_CLK_UART_FST_MIPI_CAL		162U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
-#define TEGRA234_CLK_UFSDEV_REF			163U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
-#define TEGRA234_CLK_UFSHC			164U
-/** @brief output of gate CLK_ENB_USB2_TRK */
-#define TEGRA234_CLK_USB2_TRK			165U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
-#define TEGRA234_CLK_VI				166U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
-#define TEGRA234_CLK_VIC			167U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_CSITE switch divider output */
-#define TEGRA234_CLK_CSITE			168U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_IST switch divider output */
-#define TEGRA234_CLK_IST			169U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_IST_JTAG_REG_CLK_SEL */
-#define TEGRA234_CLK_JTAG_INTFC_PRE_CG		170U
-/** @brief output of gate CLK_ENB_PEX2_CORE_7 */
-#define TEGRA234_CLK_PEX2_C7_CORE		171U
-/** @brief output of gate CLK_ENB_PEX2_CORE_8 */
-#define TEGRA234_CLK_PEX2_C8_CORE		172U
-/** @brief output of gate CLK_ENB_PEX2_CORE_9 */
-#define TEGRA234_CLK_PEX2_C9_CORE		173U
-/** @brief dla0_falcon_clk */
-#define TEGRA234_CLK_DLA0_FALCON		174U
-/** @brief dla0_core_clk */
-#define TEGRA234_CLK_DLA0_CORE			175U
-/** @brief dla1_falcon_clk */
-#define TEGRA234_CLK_DLA1_FALCON		176U
-/** @brief dla1_core_clk */
-#define TEGRA234_CLK_DLA1_CORE			177U
-/** @brief Output of mux controlled by disp_2clk_sor0_clk_safe signal (sor0_clk) */
-#define TEGRA234_CLK_SOR0			178U
-/** @brief Output of mux controlled by disp_2clk_sor1_clk_safe signal (sor1_clk) */
-#define TEGRA234_CLK_SOR1			179U
-/** @brief DP macro feedback clock (same as LINKA_SYM CLKOUT) */
-#define TEGRA234_CLK_SOR_PAD_INPUT		180U
-/** @brief Output of mux controlled by disp_2clk_h0_dsi_sel signal in sf0_clk path */
-#define TEGRA234_CLK_PRE_SF0			181U
-/** @brief Output of mux controlled by disp_2clk_sf0_clk_safe signal (sf0_clk) */
-#define TEGRA234_CLK_SF0			182U
-/** @brief Output of mux controlled by disp_2clk_sf1_clk_safe signal (sf1_clk) */
-#define TEGRA234_CLK_SF1			183U
-/** @brief CLKOUT_AB output from DSI BRICK A (dsi_clkout_ab) */
-#define TEGRA234_CLK_DSI_PAD_INPUT		184U
-/** @brief output of gate CLK_ENB_PEX2_CORE_10 */
-#define TEGRA234_CLK_PEX2_C10_CORE		187U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTI switch divider output (uarti_r_clk) */
-#define TEGRA234_CLK_UARTI			188U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ switch divider output (uartj_r_clk) */
-#define TEGRA234_CLK_UARTJ			189U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH switch divider output */
-#define TEGRA234_CLK_UARTH			190U
-/** @brief ungated version of fuse clk */
-#define TEGRA234_CLK_FUSE_SERIAL		191U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output (qspi0_2x_pm_clk) */
-#define TEGRA234_CLK_QSPI0_2X_PM		192U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output (qspi1_2x_pm_clk) */
-#define TEGRA234_CLK_QSPI1_2X_PM		193U
-/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 (qspi0_pm_clk) */
-#define TEGRA234_CLK_QSPI0_PM			194U
-/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 (qspi1_pm_clk) */
-#define TEGRA234_CLK_QSPI1_PM			195U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_VI_CONST switch divider output */
-#define TEGRA234_CLK_VI_CONST			196U
-/** @brief NAFLL clock source for BPMP */
-#define TEGRA234_CLK_NAFLL_BPMP			197U
-/** @brief NAFLL clock source for SCE */
-#define TEGRA234_CLK_NAFLL_SCE			198U
-/** @brief NAFLL clock source for NVDEC */
-#define TEGRA234_CLK_NAFLL_NVDEC		199U
-/** @brief NAFLL clock source for NVJPG */
-#define TEGRA234_CLK_NAFLL_NVJPG		200U
-/** @brief NAFLL clock source for TSEC */
-#define TEGRA234_CLK_NAFLL_TSEC			201U
-/** @brief NAFLL clock source for VI */
-#define TEGRA234_CLK_NAFLL_VI			203U
-/** @brief NAFLL clock source for SE */
-#define TEGRA234_CLK_NAFLL_SE			204U
-/** @brief NAFLL clock source for NVENC */
-#define TEGRA234_CLK_NAFLL_NVENC		205U
-/** @brief NAFLL clock source for ISP */
-#define TEGRA234_CLK_NAFLL_ISP			206U
-/** @brief NAFLL clock source for VIC */
-#define TEGRA234_CLK_NAFLL_VIC			207U
-/** @brief NAFLL clock source for AXICBB */
-#define TEGRA234_CLK_NAFLL_AXICBB		209U
-/** @brief NAFLL clock source for NVJPG1 */
-#define TEGRA234_CLK_NAFLL_NVJPG1		210U
-/** @brief NAFLL clock source for PVA core */
-#define TEGRA234_CLK_NAFLL_PVA0_CORE		211U
-/** @brief NAFLL clock source for PVA VPS */
-#define TEGRA234_CLK_NAFLL_PVA0_VPS		212U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_DBGAPB_0 switch divider output (dbgapb_clk) */
-#define TEGRA234_CLK_DBGAPB			213U
-/** @brief NAFLL clock source for RCE */
-#define TEGRA234_CLK_NAFLL_RCE			214U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_LA switch divider output (la_r_clk) */
-#define TEGRA234_CLK_LA				215U
-/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTD */
-#define TEGRA234_CLK_PLLP_OUT_JTAG		216U
-/** @brief AXI_CBB branch sharing gate control with SDMMC4 */
-#define TEGRA234_CLK_SDMMC4_AXICIF		217U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
-#define TEGRA234_CLK_SDMMC_LEGACY_TM		219U
-/** @brief output of gate CLK_ENB_PEX0_CORE_0 */
-#define TEGRA234_CLK_PEX0_C0_CORE		220U
-/** @brief output of gate CLK_ENB_PEX0_CORE_1 */
-#define TEGRA234_CLK_PEX0_C1_CORE		221U
-/** @brief output of gate CLK_ENB_PEX0_CORE_2 */
-#define TEGRA234_CLK_PEX0_C2_CORE		222U
-/** @brief output of gate CLK_ENB_PEX0_CORE_3 */
-#define TEGRA234_CLK_PEX0_C3_CORE		223U
-/** @brief output of gate CLK_ENB_PEX0_CORE_4 */
-#define TEGRA234_CLK_PEX0_C4_CORE		224U
-/** @brief output of gate CLK_ENB_PEX1_CORE_5 */
-#define TEGRA234_CLK_PEX1_C5_CORE		225U
-/** @brief Monitored branch of PEX0_C0_CORE clock */
-#define TEGRA234_CLK_PEX0_C0_CORE_M		229U
-/** @brief Monitored branch of PEX0_C1_CORE clock */
-#define TEGRA234_CLK_PEX0_C1_CORE_M		230U
-/** @brief Monitored branch of PEX0_C2_CORE clock */
-#define TEGRA234_CLK_PEX0_C2_CORE_M		231U
-/** @brief Monitored branch of PEX0_C3_CORE clock */
-#define TEGRA234_CLK_PEX0_C3_CORE_M		232U
-/** @brief Monitored branch of PEX0_C4_CORE clock */
-#define TEGRA234_CLK_PEX0_C4_CORE_M		233U
-/** @brief Monitored branch of PEX1_C5_CORE clock */
-#define TEGRA234_CLK_PEX1_C5_CORE_M		234U
-/** @brief Monitored branch of PEX1_C6_CORE clock */
-#define TEGRA234_CLK_PEX1_C6_CORE_M		235U
-/** @brief output of GPU GPC1 clkGen (in 1x mode same rate as GPC1 MUX2 out) */
-#define TEGRA234_CLK_GPC1CLK			236U
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
-#define TEGRA234_CLK_PLLC4			237U
-/** @brief PLLC4 VCO followed by DIV3 path */
-#define TEGRA234_CLK_PLLC4_OUT1			239U
-/** @brief PLLC4 VCO followed by DIV5 path */
-#define TEGRA234_CLK_PLLC4_OUT2			240U
-/** @brief output of the mux controlled by PLLC4_CLK_SEL */
-#define TEGRA234_CLK_PLLC4_MUXED		241U
-/** @brief PLLC4 VCO followed by DIV2 path */
-#define TEGRA234_CLK_PLLC4_VCO_DIV2		242U
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVHS_BASE */
-#define TEGRA234_CLK_PLLNVHS			243U
-/** @brief Monitored branch of PEX2_C7_CORE clock */
-#define TEGRA234_CLK_PEX2_C7_CORE_M		244U
-/** @brief Monitored branch of PEX2_C8_CORE clock */
-#define TEGRA234_CLK_PEX2_C8_CORE_M		245U
-/** @brief Monitored branch of PEX2_C9_CORE clock */
-#define TEGRA234_CLK_PEX2_C9_CORE_M		246U
-/** @brief Monitored branch of PEX2_C10_CORE clock */
-#define TEGRA234_CLK_PEX2_C10_CORE_M		247U
-/** @brief RX clock recovered from MGBE0 lane input */
-#define TEGRA234_CLK_MGBE0_RX_INPUT		248U
-/** @brief RX clock recovered from MGBE1 lane input */
-#define TEGRA234_CLK_MGBE1_RX_INPUT		249U
-/** @brief RX clock recovered from MGBE2 lane input */
-#define TEGRA234_CLK_MGBE2_RX_INPUT		250U
-/** @brief RX clock recovered from MGBE3 lane input */
-#define TEGRA234_CLK_MGBE3_RX_INPUT		251U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP switch divider output */
-#define TEGRA234_CLK_PEX_SATA_USB_RX_BYP	254U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT switch divider output */
-#define TEGRA234_CLK_PEX_USB_PAD_PLL0_MGMT	255U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT switch divider output */
-#define TEGRA234_CLK_PEX_USB_PAD_PLL1_MGMT	256U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL2_MGMT switch divider output */
-#define TEGRA234_CLK_PEX_USB_PAD_PLL2_MGMT	257U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL3_MGMT switch divider output */
-#define TEGRA234_CLK_PEX_USB_PAD_PLL3_MGMT	258U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_RX_BYP switch divider output */
-#define TEGRA234_CLK_NVHS_RX_BYP_REF		263U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL0_MGMT switch divider output */
-#define TEGRA234_CLK_NVHS_PLL0_MGMT		264U
-/** @brief xusb_core_dev_clk */
-#define TEGRA234_CLK_XUSB_CORE_DEV		265U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_HOST switch divider output  */
-#define TEGRA234_CLK_XUSB_CORE_MUX		266U
-/** @brief xusb_core_host_clk */
-#define TEGRA234_CLK_XUSB_CORE_HOST		267U
-/** @brief xusb_core_superspeed_clk */
-#define TEGRA234_CLK_XUSB_CORE_SS		268U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FALCON switch divider output */
-#define TEGRA234_CLK_XUSB_FALCON		269U
-/** @brief xusb_falcon_host_clk */
-#define TEGRA234_CLK_XUSB_FALCON_HOST		270U
-/** @brief xusb_falcon_superspeed_clk */
-#define TEGRA234_CLK_XUSB_FALCON_SS		271U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS switch divider output */
-#define TEGRA234_CLK_XUSB_FS			272U
-/** @brief xusb_fs_host_clk */
-#define TEGRA234_CLK_XUSB_FS_HOST		273U
-/** @brief xusb_fs_dev_clk */
-#define TEGRA234_CLK_XUSB_FS_DEV		274U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS switch divider output */
-#define TEGRA234_CLK_XUSB_SS			275U
-/** @brief xusb_ss_dev_clk */
-#define TEGRA234_CLK_XUSB_SS_DEV		276U
-/** @brief xusb_ss_superspeed_clk */
-#define TEGRA234_CLK_XUSB_SS_SUPERSPEED		277U
-/** @brief NAFLL clock source for CPU cluster 0 */
-#define TEGRA234_CLK_NAFLL_CLUSTER0		280U /* TODO: remove */
-#define TEGRA234_CLK_NAFLL_CLUSTER0_CORE	280U
-/** @brief NAFLL clock source for CPU cluster 1 */
-#define TEGRA234_CLK_NAFLL_CLUSTER1		281U /* TODO: remove */
-#define TEGRA234_CLK_NAFLL_CLUSTER1_CORE	281U
-/** @brief NAFLL clock source for CPU cluster 2 */
-#define TEGRA234_CLK_NAFLL_CLUSTER2		282U /* TODO: remove */
-#define TEGRA234_CLK_NAFLL_CLUSTER2_CORE	282U
-/** @brief CLK_RST_CONTROLLER_CAN1_CORE_RATE divider output */
-#define TEGRA234_CLK_CAN1_CORE			284U
-/** @brief CLK_RST_CONTROLLER_CAN2_CORE_RATE divider outputt */
-#define TEGRA234_CLK_CAN2_CORE			285U
-/** @brief CLK_RST_CONTROLLER_PLLA1_OUT1 switch divider output */
-#define TEGRA234_CLK_PLLA1_OUT1			286U
-/** @brief NVHS PLL hardware power sequencer (overrides 'manual' programming of PLL) */
-#define TEGRA234_CLK_PLLNVHS_HPS		287U
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE */
-#define TEGRA234_CLK_PLLREFE_VCOOUT		288U
-/** @brief 32K input clock provided by PMIC */
-#define TEGRA234_CLK_CLK_32K			289U
-/** @brief Fixed 48MHz clock divided down from utmipll */
-#define TEGRA234_CLK_UTMIPLL_CLKOUT48		291U
-/** @brief Fixed 480MHz clock divided down from utmipll */
-#define TEGRA234_CLK_UTMIPLL_CLKOUT480		292U
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE  */
-#define TEGRA234_CLK_PLLNVCSI			294U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_CPU_AXI switch divider output */
-#define TEGRA234_CLK_PVA0_CPU_AXI		295U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_PVA0_VPS switch divider output */
-#define TEGRA234_CLK_PVA0_VPS			297U
-/** @brief DLA0_CORE_NAFLL */
-#define TEGRA234_CLK_NAFLL_DLA0_CORE		299U
-/** @brief DLA0_FALCON_NAFLL */
-#define TEGRA234_CLK_NAFLL_DLA0_FALCON		300U
-/** @brief DLA1_CORE_NAFLL */
-#define TEGRA234_CLK_NAFLL_DLA1_CORE		301U
-/** @brief DLA1_FALCON_NAFLL */
-#define TEGRA234_CLK_NAFLL_DLA1_FALCON		302U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
-#define TEGRA234_CLK_AON_UART_FST_MIPI_CAL	303U
-/** @brief GPU system clock */
-#define TEGRA234_CLK_GPUSYS			304U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 */
-#define TEGRA234_CLK_I2C5			305U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider free running clk */
-#define TEGRA234_CLK_FR_SE			306U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC switch divider output */
-#define TEGRA234_CLK_BPMP_CPU_NIC		307U
-/** @brief output of gate CLK_ENB_BPMP_CPU */
-#define TEGRA234_CLK_BPMP_CPU			308U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSC switch divider output */
-#define TEGRA234_CLK_TSC			309U
-/** @brief output of mem pll A sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMC */
-#define TEGRA234_CLK_EMCSA_MPLL			310U
-/** @brief output of mem pll B sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSB */
-#define TEGRA234_CLK_EMCSB_MPLL			311U
-/** @brief output of mem pll C sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSC */
-#define TEGRA234_CLK_EMCSC_MPLL			312U
-/** @brief output of mem pll D sync mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EMCSD */
-#define TEGRA234_CLK_EMCSD_MPLL			313U
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
-#define TEGRA234_CLK_PLLC			314U
-/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
-#define TEGRA234_CLK_PLLC2			315U
-/** @brief CLK_RST_CONTROLLER_TSC_HS_SUPER_CLK_DIVIDER skip divider output */
-#define TEGRA234_CLK_TSC_REF			317U
-/** @brief Dummy clock to ensure minimum SoC voltage for fuse burning */
-#define TEGRA234_CLK_FUSE_BURN			318U
-/** @brief GBE PLL */
-#define TEGRA234_CLK_PLLGBE			319U
-/** @brief GBE PLL hardware power sequencer */
-#define TEGRA234_CLK_PLLGBE_HPS			320U
-/** @brief output of EMC CDB side A fixed (DIV4)  divider */
-#define TEGRA234_CLK_EMCSA_EMC			321U
-/** @brief output of EMC CDB side B fixed (DIV4)  divider */
-#define TEGRA234_CLK_EMCSB_EMC			322U
-/** @brief output of EMC CDB side C fixed (DIV4)  divider */
-#define TEGRA234_CLK_EMCSC_EMC			323U
-/** @brief output of EMC CDB side D fixed (DIV4)  divider */
-#define TEGRA234_CLK_EMCSD_EMC			324U
-/** @brief PLLE hardware power sequencer (overrides 'manual' programming of PLL) */
-#define TEGRA234_CLK_PLLE_HPS			326U
-/** @brief CLK_ENB_PLLREFE_OUT gate output */
-#define TEGRA234_CLK_PLLREFE_VCOOUT_GATED	327U
-/** @brief TEGRA234_CLK_SOR_SAFE clk source (PLLP_OUT0 divided by 17) */
-#define TEGRA234_CLK_PLLP_DIV17			328U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SOC_THERM switch divider output */
-#define TEGRA234_CLK_SOC_THERM			329U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_TSENSE switch divider output */
-#define TEGRA234_CLK_TSENSE			330U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider free running clk */
-#define TEGRA234_CLK_FR_SEU1			331U
-/** @brief NAFLL clock source for OFA */
-#define TEGRA234_CLK_NAFLL_OFA			333U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_OFA switch divider output */
-#define TEGRA234_CLK_OFA			334U
-/** @brief NAFLL clock source for SEU1 */
-#define TEGRA234_CLK_NAFLL_SEU1			335U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider gated output */
-#define TEGRA234_CLK_SEU1			336U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
-#define TEGRA234_CLK_SPI4			337U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI5 */
-#define TEGRA234_CLK_SPI5			338U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DCE_CPU_NIC */
-#define TEGRA234_CLK_DCE_CPU_NIC		339U
-/** @brief output of divider CLK_RST_CONTROLLER_DCE_NIC_RATE */
-#define TEGRA234_CLK_DCE_NIC			340U
-/** @brief NAFLL clock source for DCE */
-#define TEGRA234_CLK_NAFLL_DCE			341U
-/** @brief Monitored branch of MPHY_L0_RX_ANA clock */
-#define TEGRA234_CLK_MPHY_L0_RX_ANA_M		342U
-/** @brief Monitored branch of MPHY_L1_RX_ANA clock */
-#define TEGRA234_CLK_MPHY_L1_RX_ANA_M		343U
-/** @brief ungated version of TX symbol clock after fixed 1/2 divider */
-#define TEGRA234_CLK_MPHY_L0_TX_PRE_SYMB	344U
-/** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
-#define TEGRA234_CLK_MPHY_L0_TX_LS_SYMB_DIV	345U
-/** @brief output of gate CLK_ENB_MPHY_L0_TX_2X_SYMB */
-#define TEGRA234_CLK_MPHY_L0_TX_2X_SYMB		346U
-/** @brief output of SW_MPHY_L0_TX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
-#define TEGRA234_CLK_MPHY_L0_TX_HS_SYMB_DIV	347U
-/** @brief output of SW_MPHY_L0_TX_LS_3XBIT divider in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
-#define TEGRA234_CLK_MPHY_L0_TX_LS_3XBIT_DIV	348U
-/** @brief LS/HS divider mux SW_MPHY_L0_TX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_TX_CLK_CTRL_0 */
-#define TEGRA234_CLK_MPHY_L0_TX_MUX_SYMB_DIV	349U
-/** @brief Monitored branch of MPHY_L0_TX_SYMB clock */
-#define TEGRA234_CLK_MPHY_L0_TX_SYMB_M		350U
-/** @brief output of divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
-#define TEGRA234_CLK_MPHY_L0_RX_LS_SYMB_DIV	351U
-/** @brief output of SW_MPHY_L0_RX_HS_SYMB divider in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
-#define TEGRA234_CLK_MPHY_L0_RX_HS_SYMB_DIV	352U
-/** @brief output of SW_MPHY_L0_RX_LS_BIT divider in  CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
-#define TEGRA234_CLK_MPHY_L0_RX_LS_BIT_DIV	353U
-/** @brief LS/HS divider mux SW_MPHY_L0_RX_LS_HS_SEL in CLK_RST_CONTROLLER_MPHY_L0_RX_CLK_CTRL_0 */
-#define TEGRA234_CLK_MPHY_L0_RX_MUX_SYMB_DIV	354U
-/** @brief Monitored branch of MPHY_L0_RX_SYMB clock */
-#define TEGRA234_CLK_MPHY_L0_RX_SYMB_M		355U
-/** @brief Monitored branch of MBGE0 RX input clock */
-#define TEGRA234_CLK_MGBE0_RX_INPUT_M		357U
-/** @brief Monitored branch of MBGE1 RX input clock */
-#define TEGRA234_CLK_MGBE1_RX_INPUT_M		358U
-/** @brief Monitored branch of MBGE2 RX input clock */
-#define TEGRA234_CLK_MGBE2_RX_INPUT_M		359U
-/** @brief Monitored branch of MBGE3 RX input clock */
-#define TEGRA234_CLK_MGBE3_RX_INPUT_M		360U
-/** @brief Monitored branch of MGBE0 RX PCS mux output */
-#define TEGRA234_CLK_MGBE0_RX_PCS_M		361U
-/** @brief Monitored branch of MGBE1 RX PCS mux output */
-#define TEGRA234_CLK_MGBE1_RX_PCS_M		362U
-/** @brief Monitored branch of MGBE2 RX PCS mux output */
-#define TEGRA234_CLK_MGBE2_RX_PCS_M		363U
-/** @brief Monitored branch of MGBE3 RX PCS mux output */
-#define TEGRA234_CLK_MGBE3_RX_PCS_M		364U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH1 */
-#define TEGRA234_CLK_TACH1			365U
-/** @brief GBE_UPHY_MGBES_APP_CLK switch divider gated output */
-#define TEGRA234_CLK_MGBES_APP			366U
-/** @brief Logical clk for setting GBE UPHY PLL2 TX_REF rate */
-#define TEGRA234_CLK_UPHY_GBE_PLL2_TX_REF	367U
-/** @brief Logical clk for setting GBE UPHY PLL2 XDIG rate */
-#define TEGRA234_CLK_UPHY_GBE_PLL2_XDIG		368U
-/** @brief RX PCS clock recovered from MGBE0 lane input */
-#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT		369U
-/** @brief RX PCS clock recovered from MGBE1 lane input */
-#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT		370U
-/** @brief RX PCS clock recovered from MGBE2 lane input */
-#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT		371U
-/** @brief RX PCS clock recovered from MGBE3 lane input */
-#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT		372U
-/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */
-#define TEGRA234_CLK_MGBE0_RX_PCS		373U
-/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
-#define TEGRA234_CLK_MGBE0_TX			374U
-/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
-#define TEGRA234_CLK_MGBE0_TX_PCS		375U
-/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
-#define TEGRA234_CLK_MGBE0_MAC_DIVIDER		376U
-/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
-#define TEGRA234_CLK_MGBE0_MAC			377U
-/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
-#define TEGRA234_CLK_MGBE0_MACSEC		378U
-/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
-#define TEGRA234_CLK_MGBE0_EEE_PCS		379U
-/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
-#define TEGRA234_CLK_MGBE0_APP			380U
-/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
-#define TEGRA234_CLK_MGBE0_PTP_REF		381U
-/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */
-#define TEGRA234_CLK_MGBE1_RX_PCS		382U
-/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
-#define TEGRA234_CLK_MGBE1_TX			383U
-/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
-#define TEGRA234_CLK_MGBE1_TX_PCS		384U
-/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
-#define TEGRA234_CLK_MGBE1_MAC_DIVIDER		385U
-/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
-#define TEGRA234_CLK_MGBE1_MAC			386U
-/** @brief GBE_UPHY_MGBE1_MACSEC_CLK gate output */
-#define TEGRA234_CLK_MGBE1_MACSEC		387U
-/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
-#define TEGRA234_CLK_MGBE1_EEE_PCS		388U
-/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
-#define TEGRA234_CLK_MGBE1_APP			389U
-/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
-#define TEGRA234_CLK_MGBE1_PTP_REF		390U
-/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */
-#define TEGRA234_CLK_MGBE2_RX_PCS		391U
-/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
-#define TEGRA234_CLK_MGBE2_TX			392U
-/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
-#define TEGRA234_CLK_MGBE2_TX_PCS		393U
-/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
-#define TEGRA234_CLK_MGBE2_MAC_DIVIDER		394U
-/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
-#define TEGRA234_CLK_MGBE2_MAC			395U
-/** @brief GBE_UPHY_MGBE2_MACSEC_CLK gate output */
-#define TEGRA234_CLK_MGBE2_MACSEC		396U
-/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
-#define TEGRA234_CLK_MGBE2_EEE_PCS		397U
-/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
-#define TEGRA234_CLK_MGBE2_APP			398U
-/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
-#define TEGRA234_CLK_MGBE2_PTP_REF		399U
-/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */
-#define TEGRA234_CLK_MGBE3_RX_PCS		400U
-/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
-#define TEGRA234_CLK_MGBE3_TX			401U
-/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
-#define TEGRA234_CLK_MGBE3_TX_PCS		402U
-/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
-#define TEGRA234_CLK_MGBE3_MAC_DIVIDER		403U
-/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
-#define TEGRA234_CLK_MGBE3_MAC			404U
-/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
-#define TEGRA234_CLK_MGBE3_MACSEC		405U
-/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
-#define TEGRA234_CLK_MGBE3_EEE_PCS		406U
-/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
-#define TEGRA234_CLK_MGBE3_APP			407U
-/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
-#define TEGRA234_CLK_MGBE3_PTP_REF		408U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_RX_BYP switch divider output */
-#define TEGRA234_CLK_GBE_RX_BYP_REF		409U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL0_MGMT switch divider output */
-#define TEGRA234_CLK_GBE_PLL0_MGMT		410U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL1_MGMT switch divider output */
-#define TEGRA234_CLK_GBE_PLL1_MGMT		411U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_GBE_PLL2_MGMT switch divider output */
-#define TEGRA234_CLK_GBE_PLL2_MGMT		412U
-/** @brief output of gate CLK_ENB_EQOS_MACSEC_RX */
-#define TEGRA234_CLK_EQOS_MACSEC_RX		413U
-/** @brief output of gate CLK_ENB_EQOS_MACSEC_TX */
-#define TEGRA234_CLK_EQOS_MACSEC_TX		414U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider ungated output */
-#define TEGRA234_CLK_EQOS_TX_DIVIDER		415U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_NVHS_PLL1_MGMT switch divider output */
-#define TEGRA234_CLK_NVHS_PLL1_MGMT		416U
-/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EMCHUB mux output */
-#define TEGRA234_CLK_EMCHUB			417U
-/** @brief clock recovered from I2S7 input */
-#define TEGRA234_CLK_I2S7_SYNC_INPUT		418U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S7 */
-#define TEGRA234_CLK_SYNC_I2S7			419U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S7 */
-#define TEGRA234_CLK_I2S7			420U
-/** @brief Monitored output of I2S7 pad macro mux */
-#define TEGRA234_CLK_I2S7_PAD_M			421U
-/** @brief clock recovered from I2S8 input */
-#define TEGRA234_CLK_I2S8_SYNC_INPUT		422U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S8 */
-#define TEGRA234_CLK_SYNC_I2S8			423U
-/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S8 */
-#define TEGRA234_CLK_I2S8			424U
-/** @brief Monitored output of I2S8 pad macro mux */
-#define TEGRA234_CLK_I2S8_PAD_M			425U
-/** @brief NAFLL clock source for GPU GPC0 */
-#define TEGRA234_CLK_NAFLL_GPC0			426U
-/** @brief NAFLL clock source for GPU GPC1 */
-#define TEGRA234_CLK_NAFLL_GPC1			427U
-/** @brief NAFLL clock source for GPU SYSCLK */
-#define TEGRA234_CLK_NAFLL_GPUSYS		428U
-/** @brief NAFLL clock source for CPU cluster 0 DSUCLK */
-#define TEGRA234_CLK_NAFLL_DSU0			429U /* TODO: remove */
-#define TEGRA234_CLK_NAFLL_CLUSTER0_DSU		429U
-/** @brief NAFLL clock source for CPU cluster 1 DSUCLK */
-#define TEGRA234_CLK_NAFLL_DSU1			430U /* TODO: remove */
-#define TEGRA234_CLK_NAFLL_CLUSTER1_DSU		430U
-/** @brief NAFLL clock source for CPU cluster 2 DSUCLK */
-#define TEGRA234_CLK_NAFLL_DSU2			431U /* TODO: remove */
-#define TEGRA234_CLK_NAFLL_CLUSTER2_DSU		431U
-/** @brief output of gate CLK_ENB_SCE_CPU */
-#define TEGRA234_CLK_SCE_CPU			432U
-/** @brief output of gate CLK_ENB_RCE_CPU */
-#define TEGRA234_CLK_RCE_CPU			433U
-/** @brief output of gate CLK_ENB_DCE_CPU */
-#define TEGRA234_CLK_DCE_CPU			434U
-/** @brief DSIPLL VCO output */
-#define TEGRA234_CLK_DSIPLL_VCO			435U
-/** @brief DSIPLL SYNC_CLKOUTP/N differential output */
-#define TEGRA234_CLK_DSIPLL_CLKOUTPN		436U
-/** @brief DSIPLL SYNC_CLKOUTA output */
-#define TEGRA234_CLK_DSIPLL_CLKOUTA		437U
-/** @brief SPPLL0 VCO output */
-#define TEGRA234_CLK_SPPLL0_VCO			438U
-/** @brief SPPLL0 SYNC_CLKOUTP/N differential output */
-#define TEGRA234_CLK_SPPLL0_CLKOUTPN		439U
-/** @brief SPPLL0 SYNC_CLKOUTA output */
-#define TEGRA234_CLK_SPPLL0_CLKOUTA		440U
-/** @brief SPPLL0 SYNC_CLKOUTB output */
-#define TEGRA234_CLK_SPPLL0_CLKOUTB		441U
-/** @brief SPPLL0 CLKOUT_DIVBY10 output */
-#define TEGRA234_CLK_SPPLL0_DIV10		442U
-/** @brief SPPLL0 CLKOUT_DIVBY25 output */
-#define TEGRA234_CLK_SPPLL0_DIV25		443U
-/** @brief SPPLL0 CLKOUT_DIVBY27P/N differential output */
-#define TEGRA234_CLK_SPPLL0_DIV27PN		444U
-/** @brief SPPLL1 VCO output */
-#define TEGRA234_CLK_SPPLL1_VCO			445U
-/** @brief SPPLL1 SYNC_CLKOUTP/N differential output */
-#define TEGRA234_CLK_SPPLL1_CLKOUTPN		446U
-/** @brief SPPLL1 CLKOUT_DIVBY27P/N differential output */
-#define TEGRA234_CLK_SPPLL1_DIV27PN		447U
-/** @brief VPLL0 reference clock */
-#define TEGRA234_CLK_VPLL0_REF			448U
-/** @brief VPLL0 */
-#define TEGRA234_CLK_VPLL0			449U
-/** @brief VPLL1 */
-#define TEGRA234_CLK_VPLL1			450U
-/** @brief NVDISPLAY_P0_CLK reference select */
-#define TEGRA234_CLK_NVDISPLAY_P0_REF		451U
-/** @brief RG0_PCLK */
-#define TEGRA234_CLK_RG0			452U
-/** @brief RG1_PCLK */
-#define TEGRA234_CLK_RG1			453U
-/** @brief DISPPLL output */
-#define TEGRA234_CLK_DISPPLL			454U
-/** @brief DISPHUBPLL output */
-#define TEGRA234_CLK_DISPHUBPLL			455U
-/** @brief CLK_RST_CONTROLLER_DSI_LP_SWITCH_DIVIDER switch divider output (dsi_lp_clk) */
-#define TEGRA234_CLK_DSI_LP			456U
-/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
-#define TEGRA234_CLK_AZA_2XBIT			457U
-/** @brief aza_2xbitclk / 2 (aza_bitclk) */
-#define TEGRA234_CLK_AZA_BIT			458U
-/** @brief SWITCH_DSI_CORE_PIXEL_MISC_DSI_CORE_CLK_SRC switch output (dsi_core_clk) */
-#define TEGRA234_CLK_DSI_CORE			459U
-/** @brief Output of mux controlled by pkt_wr_fifo_signal from dsi (dsi_pixel_clk) */
-#define TEGRA234_CLK_DSI_PIXEL			460U
-/** @brief Output of mux controlled by disp_2clk_sor0_dp_sel (pre_sor0_clk) */
-#define TEGRA234_CLK_PRE_SOR0			461U
-/** @brief Output of mux controlled by disp_2clk_sor1_dp_sel (pre_sor1_clk) */
-#define TEGRA234_CLK_PRE_SOR1			462U
-/** @brief CLK_RST_CONTROLLER_LINK_REFCLK_CFG__0 output */
-#define TEGRA234_CLK_DP_LINK_REF		463U
-/** @brief Link clock input from DP macro brick PLL */
-#define TEGRA234_CLK_SOR_LINKA_INPUT		464U
-/** @brief SOR AFIFO clock outut */
-#define TEGRA234_CLK_SOR_LINKA_AFIFO		465U
-/** @brief Monitored branch of linka_afifo_clk */
-#define TEGRA234_CLK_SOR_LINKA_AFIFO_M		466U
-/** @brief Monitored branch of rg0_pclk */
-#define TEGRA234_CLK_RG0_M			467U
-/** @brief Monitored branch of rg1_pclk */
-#define TEGRA234_CLK_RG1_M			468U
-/** @brief Monitored branch of sor0_clk */
-#define TEGRA234_CLK_SOR0_M			469U
-/** @brief Monitored branch of sor1_clk */
-#define TEGRA234_CLK_SOR1_M			470U
-/** @brief EMC PLLHUB output */
-#define TEGRA234_CLK_PLLHUB			471U
-/** @brief output of fixed (DIV2) MC HUB divider */
-#define TEGRA234_CLK_MCHUB			472U
-/** @brief output of divider controlled by EMC side A MC_EMC_SAFE_SAME_FREQ */
-#define TEGRA234_CLK_EMCSA_MC			473U
-/** @brief output of divider controlled by EMC side B MC_EMC_SAFE_SAME_FREQ */
-#define TEGRA234_CLK_EMCSB_MC			474U
-/** @brief output of divider controlled by EMC side C MC_EMC_SAFE_SAME_FREQ */
-#define TEGRA234_CLK_EMCSC_MC			475U
-/** @brief output of divider controlled by EMC side D MC_EMC_SAFE_SAME_FREQ */
-#define TEGRA234_CLK_EMCSD_MC			476U
-
-/** @} */
-
-#endif

include/kernel/dt-bindings/gpio/gpio.h

@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2023, NVIDIA CORPORATION.  All rights reserved. */
-/*
- * This header provides constants for most GPIO bindings.
- *
- * Most GPIO bindings include a flags cell as part of the GPIO specifier.
- * In most cases, the format of the flags cell uses the standard values
- * defined in this header.
- */
-
-#ifndef _DT_BINDINGS_GPIO_GPIO_H
-#define _DT_BINDINGS_GPIO_GPIO_H
-
-/* Bit 0 express polarity */
-#define GPIO_ACTIVE_HIGH 0
-#define GPIO_ACTIVE_LOW 1
-
-/* Bit 1 express single-endedness */
-#define GPIO_PUSH_PULL 0
-#define GPIO_SINGLE_ENDED 2
-
-/* Bit 2 express Open drain or open source */
-#define GPIO_LINE_OPEN_SOURCE 0
-#define GPIO_LINE_OPEN_DRAIN 4
-
-/*
- * Open Drain/Collector is the combination of single-ended open drain interface.
- * Open Source/Emitter is the combination of single-ended open source interface.
- */
-#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
-#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
-
-/* Bit 3 express GPIO suspend/resume and reset persistence */
-#define GPIO_PERSISTENT 0
-#define GPIO_TRANSITORY 8
-
-/* Bit 4 express pull up */
-#define GPIO_PULL_UP 16
-
-/* Bit 5 express pull down */
-#define GPIO_PULL_DOWN 32
-
-/* Bit 6 express pull disable */
-#define GPIO_PULL_DISABLE 64
-
-#endif

include/kernel/dt-bindings/gpio/tegra234-gpio.h

@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */
-
-/*
- * This header provides constants for binding nvidia,tegra234-gpio*.
- *
- * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
- * provide names for this.
- *
- * The second cell contains standard flag values specified in gpio.h.
- */
-
-#ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
-#define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H
-
-#include <dt-bindings/gpio/gpio.h>
-
-/* GPIOs implemented by main GPIO controller */
-#define TEGRA234_MAIN_GPIO_PORT_A   0
-#define TEGRA234_MAIN_GPIO_PORT_B   1
-#define TEGRA234_MAIN_GPIO_PORT_C   2
-#define TEGRA234_MAIN_GPIO_PORT_D   3
-#define TEGRA234_MAIN_GPIO_PORT_E   4
-#define TEGRA234_MAIN_GPIO_PORT_F   5
-#define TEGRA234_MAIN_GPIO_PORT_G   6
-#define TEGRA234_MAIN_GPIO_PORT_H   7
-#define TEGRA234_MAIN_GPIO_PORT_I   8
-#define TEGRA234_MAIN_GPIO_PORT_J   9
-#define TEGRA234_MAIN_GPIO_PORT_K  10
-#define TEGRA234_MAIN_GPIO_PORT_L  11
-#define TEGRA234_MAIN_GPIO_PORT_M  12
-#define TEGRA234_MAIN_GPIO_PORT_N  13
-#define TEGRA234_MAIN_GPIO_PORT_P  14
-#define TEGRA234_MAIN_GPIO_PORT_Q  15
-#define TEGRA234_MAIN_GPIO_PORT_R  16
-#define TEGRA234_MAIN_GPIO_PORT_X  17
-#define TEGRA234_MAIN_GPIO_PORT_Y  18
-#define TEGRA234_MAIN_GPIO_PORT_Z  19
-#define TEGRA234_MAIN_GPIO_PORT_AC 20
-#define TEGRA234_MAIN_GPIO_PORT_AD 21
-#define TEGRA234_MAIN_GPIO_PORT_AE 22
-#define TEGRA234_MAIN_GPIO_PORT_AF 23
-#define TEGRA234_MAIN_GPIO_PORT_AG 24
-
-#define TEGRA234_MAIN_GPIO(port, offset) \
-	((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset)
-
-/* GPIOs implemented by AON GPIO controller */
-#define TEGRA234_AON_GPIO_PORT_AA 0
-#define TEGRA234_AON_GPIO_PORT_BB 1
-#define TEGRA234_AON_GPIO_PORT_CC 2
-#define TEGRA234_AON_GPIO_PORT_DD 3
-#define TEGRA234_AON_GPIO_PORT_EE 4
-#define TEGRA234_AON_GPIO_PORT_GG 5
-
-#define TEGRA234_AON_GPIO(port, offset) \
-	((TEGRA234_AON_GPIO_PORT_##port * 8) + offset)
-
-#endif

include/kernel/dt-bindings/input/gpio-keys.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for gpio keys bindings.
- */
-
-#ifndef _DT_BINDINGS_GPIO_KEYS_H
-#define _DT_BINDINGS_GPIO_KEYS_H
-
-#define EV_ACT_ANY		0x00	/* asserted or deasserted */
-#define EV_ACT_ASSERTED		0x01	/* asserted */
-#define EV_ACT_DEASSERTED	0x02	/* deasserted */
-
-#endif /* _DT_BINDINGS_GPIO_KEYS_H */

include/kernel/dt-bindings/input/linux-event-codes.h

@@ -1,977 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
-/*
- * Input event codes
- *
- *    *** IMPORTANT ***
- * This file is not only included from C-code but also from devicetree source
- * files. As such this file MUST only contain comments and defines.
- *
- * Copyright (c) 1999-2002 Vojtech Pavlik
- * Copyright (c) 2015 Hans de Goede <hdegoede@redhat.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef _UAPI_INPUT_EVENT_CODES_H
-#define _UAPI_INPUT_EVENT_CODES_H
-
-/*
- * Device properties and quirks
- */
-
-#define INPUT_PROP_POINTER		0x00	/* needs a pointer */
-#define INPUT_PROP_DIRECT		0x01	/* direct input devices */
-#define INPUT_PROP_BUTTONPAD		0x02	/* has button(s) under pad */
-#define INPUT_PROP_SEMI_MT		0x03	/* touch rectangle only */
-#define INPUT_PROP_TOPBUTTONPAD		0x04	/* softbuttons at top of pad */
-#define INPUT_PROP_POINTING_STICK	0x05	/* is a pointing stick */
-#define INPUT_PROP_ACCELEROMETER	0x06	/* has accelerometer */
-
-#define INPUT_PROP_MAX			0x1f
-#define INPUT_PROP_CNT			(INPUT_PROP_MAX + 1)
-
-/*
- * Event types
- */
-
-#define EV_SYN			0x00
-#define EV_KEY			0x01
-#define EV_REL			0x02
-#define EV_ABS			0x03
-#define EV_MSC			0x04
-#define EV_SW			0x05
-#define EV_LED			0x11
-#define EV_SND			0x12
-#define EV_REP			0x14
-#define EV_FF			0x15
-#define EV_PWR			0x16
-#define EV_FF_STATUS		0x17
-#define EV_MAX			0x1f
-#define EV_CNT			(EV_MAX+1)
-
-/*
- * Synchronization events.
- */
-
-#define SYN_REPORT		0
-#define SYN_CONFIG		1
-#define SYN_MT_REPORT		2
-#define SYN_DROPPED		3
-#define SYN_MAX			0xf
-#define SYN_CNT			(SYN_MAX+1)
-
-/*
- * Keys and buttons
- *
- * Most of the keys/buttons are modeled after USB HUT 1.12
- * (see http://www.usb.org/developers/hidpage).
- * Abbreviations in the comments:
- * AC - Application Control
- * AL - Application Launch Button
- * SC - System Control
- */
-
-#define KEY_RESERVED		0
-#define KEY_ESC			1
-#define KEY_1			2
-#define KEY_2			3
-#define KEY_3			4
-#define KEY_4			5
-#define KEY_5			6
-#define KEY_6			7
-#define KEY_7			8
-#define KEY_8			9
-#define KEY_9			10
-#define KEY_0			11
-#define KEY_MINUS		12
-#define KEY_EQUAL		13
-#define KEY_BACKSPACE		14
-#define KEY_TAB			15
-#define KEY_Q			16
-#define KEY_W			17
-#define KEY_E			18
-#define KEY_R			19
-#define KEY_T			20
-#define KEY_Y			21
-#define KEY_U			22
-#define KEY_I			23
-#define KEY_O			24
-#define KEY_P			25
-#define KEY_LEFTBRACE		26
-#define KEY_RIGHTBRACE		27
-#define KEY_ENTER		28
-#define KEY_LEFTCTRL		29
-#define KEY_A			30
-#define KEY_S			31
-#define KEY_D			32
-#define KEY_F			33
-#define KEY_G			34
-#define KEY_H			35
-#define KEY_J			36
-#define KEY_K			37
-#define KEY_L			38
-#define KEY_SEMICOLON		39
-#define KEY_APOSTROPHE		40
-#define KEY_GRAVE		41
-#define KEY_LEFTSHIFT		42
-#define KEY_BACKSLASH		43
-#define KEY_Z			44
-#define KEY_X			45
-#define KEY_C			46
-#define KEY_V			47
-#define KEY_B			48
-#define KEY_N			49
-#define KEY_M			50
-#define KEY_COMMA		51
-#define KEY_DOT			52
-#define KEY_SLASH		53
-#define KEY_RIGHTSHIFT		54
-#define KEY_KPASTERISK		55
-#define KEY_LEFTALT		56
-#define KEY_SPACE		57
-#define KEY_CAPSLOCK		58
-#define KEY_F1			59
-#define KEY_F2			60
-#define KEY_F3			61
-#define KEY_F4			62
-#define KEY_F5			63
-#define KEY_F6			64
-#define KEY_F7			65
-#define KEY_F8			66
-#define KEY_F9			67
-#define KEY_F10			68
-#define KEY_NUMLOCK		69
-#define KEY_SCROLLLOCK		70
-#define KEY_KP7			71
-#define KEY_KP8			72
-#define KEY_KP9			73
-#define KEY_KPMINUS		74
-#define KEY_KP4			75
-#define KEY_KP5			76
-#define KEY_KP6			77
-#define KEY_KPPLUS		78
-#define KEY_KP1			79
-#define KEY_KP2			80
-#define KEY_KP3			81
-#define KEY_KP0			82
-#define KEY_KPDOT		83
-
-#define KEY_ZENKAKUHANKAKU	85
-#define KEY_102ND		86
-#define KEY_F11			87
-#define KEY_F12			88
-#define KEY_RO			89
-#define KEY_KATAKANA		90
-#define KEY_HIRAGANA		91
-#define KEY_HENKAN		92
-#define KEY_KATAKANAHIRAGANA	93
-#define KEY_MUHENKAN		94
-#define KEY_KPJPCOMMA		95
-#define KEY_KPENTER		96
-#define KEY_RIGHTCTRL		97
-#define KEY_KPSLASH		98
-#define KEY_SYSRQ		99
-#define KEY_RIGHTALT		100
-#define KEY_LINEFEED		101
-#define KEY_HOME		102
-#define KEY_UP			103
-#define KEY_PAGEUP		104
-#define KEY_LEFT		105
-#define KEY_RIGHT		106
-#define KEY_END			107
-#define KEY_DOWN		108
-#define KEY_PAGEDOWN		109
-#define KEY_INSERT		110
-#define KEY_DELETE		111
-#define KEY_MACRO		112
-#define KEY_MUTE		113
-#define KEY_VOLUMEDOWN		114
-#define KEY_VOLUMEUP		115
-#define KEY_POWER		116	/* SC System Power Down */
-#define KEY_KPEQUAL		117
-#define KEY_KPPLUSMINUS		118
-#define KEY_PAUSE		119
-#define KEY_SCALE		120	/* AL Compiz Scale (Expose) */
-
-#define KEY_KPCOMMA		121
-#define KEY_HANGEUL		122
-#define KEY_HANGUEL		KEY_HANGEUL
-#define KEY_HANJA		123
-#define KEY_YEN			124
-#define KEY_LEFTMETA		125
-#define KEY_RIGHTMETA		126
-#define KEY_COMPOSE		127
-
-#define KEY_STOP		128	/* AC Stop */
-#define KEY_AGAIN		129
-#define KEY_PROPS		130	/* AC Properties */
-#define KEY_UNDO		131	/* AC Undo */
-#define KEY_FRONT		132
-#define KEY_COPY		133	/* AC Copy */
-#define KEY_OPEN		134	/* AC Open */
-#define KEY_PASTE		135	/* AC Paste */
-#define KEY_FIND		136	/* AC Search */
-#define KEY_CUT			137	/* AC Cut */
-#define KEY_HELP		138	/* AL Integrated Help Center */
-#define KEY_MENU		139	/* Menu (show menu) */
-#define KEY_CALC		140	/* AL Calculator */
-#define KEY_SETUP		141
-#define KEY_SLEEP		142	/* SC System Sleep */
-#define KEY_WAKEUP		143	/* System Wake Up */
-#define KEY_FILE		144	/* AL Local Machine Browser */
-#define KEY_SENDFILE		145
-#define KEY_DELETEFILE		146
-#define KEY_XFER		147
-#define KEY_PROG1		148
-#define KEY_PROG2		149
-#define KEY_WWW			150	/* AL Internet Browser */
-#define KEY_MSDOS		151
-#define KEY_COFFEE		152	/* AL Terminal Lock/Screensaver */
-#define KEY_SCREENLOCK		KEY_COFFEE
-#define KEY_ROTATE_DISPLAY	153	/* Display orientation for e.g. tablets */
-#define KEY_DIRECTION		KEY_ROTATE_DISPLAY
-#define KEY_CYCLEWINDOWS	154
-#define KEY_MAIL		155
-#define KEY_BOOKMARKS		156	/* AC Bookmarks */
-#define KEY_COMPUTER		157
-#define KEY_BACK		158	/* AC Back */
-#define KEY_FORWARD		159	/* AC Forward */
-#define KEY_CLOSECD		160
-#define KEY_EJECTCD		161
-#define KEY_EJECTCLOSECD	162
-#define KEY_NEXTSONG		163
-#define KEY_PLAYPAUSE		164
-#define KEY_PREVIOUSSONG	165
-#define KEY_STOPCD		166
-#define KEY_RECORD		167
-#define KEY_REWIND		168
-#define KEY_PHONE		169	/* Media Select Telephone */
-#define KEY_ISO			170
-#define KEY_CONFIG		171	/* AL Consumer Control Configuration */
-#define KEY_HOMEPAGE		172	/* AC Home */
-#define KEY_REFRESH		173	/* AC Refresh */
-#define KEY_EXIT		174	/* AC Exit */
-#define KEY_MOVE		175
-#define KEY_EDIT		176
-#define KEY_SCROLLUP		177
-#define KEY_SCROLLDOWN		178
-#define KEY_KPLEFTPAREN		179
-#define KEY_KPRIGHTPAREN	180
-#define KEY_NEW			181	/* AC New */
-#define KEY_REDO		182	/* AC Redo/Repeat */
-
-#define KEY_F13			183
-#define KEY_F14			184
-#define KEY_F15			185
-#define KEY_F16			186
-#define KEY_F17			187
-#define KEY_F18			188
-#define KEY_F19			189
-#define KEY_F20			190
-#define KEY_F21			191
-#define KEY_F22			192
-#define KEY_F23			193
-#define KEY_F24			194
-
-#define KEY_PLAYCD		200
-#define KEY_PAUSECD		201
-#define KEY_PROG3		202
-#define KEY_PROG4		203
-#define KEY_ALL_APPLICATIONS	204	/* AC Desktop Show All Applications */
-#define KEY_DASHBOARD		KEY_ALL_APPLICATIONS
-#define KEY_SUSPEND		205
-#define KEY_CLOSE		206	/* AC Close */
-#define KEY_PLAY		207
-#define KEY_FASTFORWARD		208
-#define KEY_BASSBOOST		209
-#define KEY_PRINT		210	/* AC Print */
-#define KEY_HP			211
-#define KEY_CAMERA		212
-#define KEY_SOUND		213
-#define KEY_QUESTION		214
-#define KEY_EMAIL		215
-#define KEY_CHAT		216
-#define KEY_SEARCH		217
-#define KEY_CONNECT		218
-#define KEY_FINANCE		219	/* AL Checkbook/Finance */
-#define KEY_SPORT		220
-#define KEY_SHOP		221
-#define KEY_ALTERASE		222
-#define KEY_CANCEL		223	/* AC Cancel */
-#define KEY_BRIGHTNESSDOWN	224
-#define KEY_BRIGHTNESSUP	225
-#define KEY_MEDIA		226
-
-#define KEY_SWITCHVIDEOMODE	227	/* Cycle between available video
-					   outputs (Monitor/LCD/TV-out/etc) */
-#define KEY_KBDILLUMTOGGLE	228
-#define KEY_KBDILLUMDOWN	229
-#define KEY_KBDILLUMUP		230
-
-#define KEY_SEND		231	/* AC Send */
-#define KEY_REPLY		232	/* AC Reply */
-#define KEY_FORWARDMAIL		233	/* AC Forward Msg */
-#define KEY_SAVE		234	/* AC Save */
-#define KEY_DOCUMENTS		235
-
-#define KEY_BATTERY		236
-
-#define KEY_BLUETOOTH		237
-#define KEY_WLAN		238
-#define KEY_UWB			239
-
-#define KEY_UNKNOWN		240
-
-#define KEY_VIDEO_NEXT		241	/* drive next video source */
-#define KEY_VIDEO_PREV		242	/* drive previous video source */
-#define KEY_BRIGHTNESS_CYCLE	243	/* brightness up, after max is min */
-#define KEY_BRIGHTNESS_AUTO	244	/* Set Auto Brightness: manual
-					  brightness control is off,
-					  rely on ambient */
-#define KEY_BRIGHTNESS_ZERO	KEY_BRIGHTNESS_AUTO
-#define KEY_DISPLAY_OFF		245	/* display device to off state */
-
-#define KEY_WWAN		246	/* Wireless WAN (LTE, UMTS, GSM, etc.) */
-#define KEY_WIMAX		KEY_WWAN
-#define KEY_RFKILL		247	/* Key that controls all radios */
-
-#define KEY_MICMUTE		248	/* Mute / unmute the microphone */
-
-/* Code 255 is reserved for special needs of AT keyboard driver */
-
-#define BTN_MISC		0x100
-#define BTN_0			0x100
-#define BTN_1			0x101
-#define BTN_2			0x102
-#define BTN_3			0x103
-#define BTN_4			0x104
-#define BTN_5			0x105
-#define BTN_6			0x106
-#define BTN_7			0x107
-#define BTN_8			0x108
-#define BTN_9			0x109
-
-#define BTN_MOUSE		0x110
-#define BTN_LEFT		0x110
-#define BTN_RIGHT		0x111
-#define BTN_MIDDLE		0x112
-#define BTN_SIDE		0x113
-#define BTN_EXTRA		0x114
-#define BTN_FORWARD		0x115
-#define BTN_BACK		0x116
-#define BTN_TASK		0x117
-
-#define BTN_JOYSTICK		0x120
-#define BTN_TRIGGER		0x120
-#define BTN_THUMB		0x121
-#define BTN_THUMB2		0x122
-#define BTN_TOP			0x123
-#define BTN_TOP2		0x124
-#define BTN_PINKIE		0x125
-#define BTN_BASE		0x126
-#define BTN_BASE2		0x127
-#define BTN_BASE3		0x128
-#define BTN_BASE4		0x129
-#define BTN_BASE5		0x12a
-#define BTN_BASE6		0x12b
-#define BTN_DEAD		0x12f
-
-#define BTN_GAMEPAD		0x130
-#define BTN_SOUTH		0x130
-#define BTN_A			BTN_SOUTH
-#define BTN_EAST		0x131
-#define BTN_B			BTN_EAST
-#define BTN_C			0x132
-#define BTN_NORTH		0x133
-#define BTN_X			BTN_NORTH
-#define BTN_WEST		0x134
-#define BTN_Y			BTN_WEST
-#define BTN_Z			0x135
-#define BTN_TL			0x136
-#define BTN_TR			0x137
-#define BTN_TL2			0x138
-#define BTN_TR2			0x139
-#define BTN_SELECT		0x13a
-#define BTN_START		0x13b
-#define BTN_MODE		0x13c
-#define BTN_THUMBL		0x13d
-#define BTN_THUMBR		0x13e
-
-#define BTN_DIGI		0x140
-#define BTN_TOOL_PEN		0x140
-#define BTN_TOOL_RUBBER		0x141
-#define BTN_TOOL_BRUSH		0x142
-#define BTN_TOOL_PENCIL		0x143
-#define BTN_TOOL_AIRBRUSH	0x144
-#define BTN_TOOL_FINGER		0x145
-#define BTN_TOOL_MOUSE		0x146
-#define BTN_TOOL_LENS		0x147
-#define BTN_TOOL_QUINTTAP	0x148	/* Five fingers on trackpad */
-#define BTN_STYLUS3		0x149
-#define BTN_TOUCH		0x14a
-#define BTN_STYLUS		0x14b
-#define BTN_STYLUS2		0x14c
-#define BTN_TOOL_DOUBLETAP	0x14d
-#define BTN_TOOL_TRIPLETAP	0x14e
-#define BTN_TOOL_QUADTAP	0x14f	/* Four fingers on trackpad */
-
-#define BTN_WHEEL		0x150
-#define BTN_GEAR_DOWN		0x150
-#define BTN_GEAR_UP		0x151
-
-#define KEY_OK			0x160
-#define KEY_SELECT		0x161
-#define KEY_GOTO		0x162
-#define KEY_CLEAR		0x163
-#define KEY_POWER2		0x164
-#define KEY_OPTION		0x165
-#define KEY_INFO		0x166	/* AL OEM Features/Tips/Tutorial */
-#define KEY_TIME		0x167
-#define KEY_VENDOR		0x168
-#define KEY_ARCHIVE		0x169
-#define KEY_PROGRAM		0x16a	/* Media Select Program Guide */
-#define KEY_CHANNEL		0x16b
-#define KEY_FAVORITES		0x16c
-#define KEY_EPG			0x16d
-#define KEY_PVR			0x16e	/* Media Select Home */
-#define KEY_MHP			0x16f
-#define KEY_LANGUAGE		0x170
-#define KEY_TITLE		0x171
-#define KEY_SUBTITLE		0x172
-#define KEY_ANGLE		0x173
-#define KEY_FULL_SCREEN		0x174	/* AC View Toggle */
-#define KEY_ZOOM		KEY_FULL_SCREEN
-#define KEY_MODE		0x175
-#define KEY_KEYBOARD		0x176
-#define KEY_ASPECT_RATIO	0x177	/* HUTRR37: Aspect */
-#define KEY_SCREEN		KEY_ASPECT_RATIO
-#define KEY_PC			0x178	/* Media Select Computer */
-#define KEY_TV			0x179	/* Media Select TV */
-#define KEY_TV2			0x17a	/* Media Select Cable */
-#define KEY_VCR			0x17b	/* Media Select VCR */
-#define KEY_VCR2		0x17c	/* VCR Plus */
-#define KEY_SAT			0x17d	/* Media Select Satellite */
-#define KEY_SAT2		0x17e
-#define KEY_CD			0x17f	/* Media Select CD */
-#define KEY_TAPE		0x180	/* Media Select Tape */
-#define KEY_RADIO		0x181
-#define KEY_TUNER		0x182	/* Media Select Tuner */
-#define KEY_PLAYER		0x183
-#define KEY_TEXT		0x184
-#define KEY_DVD			0x185	/* Media Select DVD */
-#define KEY_AUX			0x186
-#define KEY_MP3			0x187
-#define KEY_AUDIO		0x188	/* AL Audio Browser */
-#define KEY_VIDEO		0x189	/* AL Movie Browser */
-#define KEY_DIRECTORY		0x18a
-#define KEY_LIST		0x18b
-#define KEY_MEMO		0x18c	/* Media Select Messages */
-#define KEY_CALENDAR		0x18d
-#define KEY_RED			0x18e
-#define KEY_GREEN		0x18f
-#define KEY_YELLOW		0x190
-#define KEY_BLUE		0x191
-#define KEY_CHANNELUP		0x192	/* Channel Increment */
-#define KEY_CHANNELDOWN		0x193	/* Channel Decrement */
-#define KEY_FIRST		0x194
-#define KEY_LAST		0x195	/* Recall Last */
-#define KEY_AB			0x196
-#define KEY_NEXT		0x197
-#define KEY_RESTART		0x198
-#define KEY_SLOW		0x199
-#define KEY_SHUFFLE		0x19a
-#define KEY_BREAK		0x19b
-#define KEY_PREVIOUS		0x19c
-#define KEY_DIGITS		0x19d
-#define KEY_TEEN		0x19e
-#define KEY_TWEN		0x19f
-#define KEY_VIDEOPHONE		0x1a0	/* Media Select Video Phone */
-#define KEY_GAMES		0x1a1	/* Media Select Games */
-#define KEY_ZOOMIN		0x1a2	/* AC Zoom In */
-#define KEY_ZOOMOUT		0x1a3	/* AC Zoom Out */
-#define KEY_ZOOMRESET		0x1a4	/* AC Zoom */
-#define KEY_WORDPROCESSOR	0x1a5	/* AL Word Processor */
-#define KEY_EDITOR		0x1a6	/* AL Text Editor */
-#define KEY_SPREADSHEET		0x1a7	/* AL Spreadsheet */
-#define KEY_GRAPHICSEDITOR	0x1a8	/* AL Graphics Editor */
-#define KEY_PRESENTATION	0x1a9	/* AL Presentation App */
-#define KEY_DATABASE		0x1aa	/* AL Database App */
-#define KEY_NEWS		0x1ab	/* AL Newsreader */
-#define KEY_VOICEMAIL		0x1ac	/* AL Voicemail */
-#define KEY_ADDRESSBOOK		0x1ad	/* AL Contacts/Address Book */
-#define KEY_MESSENGER		0x1ae	/* AL Instant Messaging */
-#define KEY_DISPLAYTOGGLE	0x1af	/* Turn display (LCD) on and off */
-#define KEY_BRIGHTNESS_TOGGLE	KEY_DISPLAYTOGGLE
-#define KEY_SPELLCHECK		0x1b0   /* AL Spell Check */
-#define KEY_LOGOFF		0x1b1   /* AL Logoff */
-
-#define KEY_DOLLAR		0x1b2
-#define KEY_EURO		0x1b3
-
-#define KEY_FRAMEBACK		0x1b4	/* Consumer - transport controls */
-#define KEY_FRAMEFORWARD	0x1b5
-#define KEY_CONTEXT_MENU	0x1b6	/* GenDesc - system context menu */
-#define KEY_MEDIA_REPEAT	0x1b7	/* Consumer - transport control */
-#define KEY_10CHANNELSUP	0x1b8	/* 10 channels up (10+) */
-#define KEY_10CHANNELSDOWN	0x1b9	/* 10 channels down (10-) */
-#define KEY_IMAGES		0x1ba	/* AL Image Browser */
-#define KEY_NOTIFICATION_CENTER	0x1bc	/* Show/hide the notification center */
-#define KEY_PICKUP_PHONE	0x1bd	/* Answer incoming call */
-#define KEY_HANGUP_PHONE	0x1be	/* Decline incoming call */
-
-#define KEY_DEL_EOL		0x1c0
-#define KEY_DEL_EOS		0x1c1
-#define KEY_INS_LINE		0x1c2
-#define KEY_DEL_LINE		0x1c3
-
-#define KEY_FN			0x1d0
-#define KEY_FN_ESC		0x1d1
-#define KEY_FN_F1		0x1d2
-#define KEY_FN_F2		0x1d3
-#define KEY_FN_F3		0x1d4
-#define KEY_FN_F4		0x1d5
-#define KEY_FN_F5		0x1d6
-#define KEY_FN_F6		0x1d7
-#define KEY_FN_F7		0x1d8
-#define KEY_FN_F8		0x1d9
-#define KEY_FN_F9		0x1da
-#define KEY_FN_F10		0x1db
-#define KEY_FN_F11		0x1dc
-#define KEY_FN_F12		0x1dd
-#define KEY_FN_1		0x1de
-#define KEY_FN_2		0x1df
-#define KEY_FN_D		0x1e0
-#define KEY_FN_E		0x1e1
-#define KEY_FN_F		0x1e2
-#define KEY_FN_S		0x1e3
-#define KEY_FN_B		0x1e4
-#define KEY_FN_RIGHT_SHIFT	0x1e5
-
-#define KEY_BRL_DOT1		0x1f1
-#define KEY_BRL_DOT2		0x1f2
-#define KEY_BRL_DOT3		0x1f3
-#define KEY_BRL_DOT4		0x1f4
-#define KEY_BRL_DOT5		0x1f5
-#define KEY_BRL_DOT6		0x1f6
-#define KEY_BRL_DOT7		0x1f7
-#define KEY_BRL_DOT8		0x1f8
-#define KEY_BRL_DOT9		0x1f9
-#define KEY_BRL_DOT10		0x1fa
-
-#define KEY_NUMERIC_0		0x200	/* used by phones, remote controls, */
-#define KEY_NUMERIC_1		0x201	/* and other keypads */
-#define KEY_NUMERIC_2		0x202
-#define KEY_NUMERIC_3		0x203
-#define KEY_NUMERIC_4		0x204
-#define KEY_NUMERIC_5		0x205
-#define KEY_NUMERIC_6		0x206
-#define KEY_NUMERIC_7		0x207
-#define KEY_NUMERIC_8		0x208
-#define KEY_NUMERIC_9		0x209
-#define KEY_NUMERIC_STAR	0x20a
-#define KEY_NUMERIC_POUND	0x20b
-#define KEY_NUMERIC_A		0x20c	/* Phone key A - HUT Telephony 0xb9 */
-#define KEY_NUMERIC_B		0x20d
-#define KEY_NUMERIC_C		0x20e
-#define KEY_NUMERIC_D		0x20f
-
-#define KEY_CAMERA_FOCUS	0x210
-#define KEY_WPS_BUTTON		0x211	/* WiFi Protected Setup key */
-
-#define KEY_TOUCHPAD_TOGGLE	0x212	/* Request switch touchpad on or off */
-#define KEY_TOUCHPAD_ON		0x213
-#define KEY_TOUCHPAD_OFF	0x214
-
-#define KEY_CAMERA_ZOOMIN	0x215
-#define KEY_CAMERA_ZOOMOUT	0x216
-#define KEY_CAMERA_UP		0x217
-#define KEY_CAMERA_DOWN		0x218
-#define KEY_CAMERA_LEFT		0x219
-#define KEY_CAMERA_RIGHT	0x21a
-
-#define KEY_ATTENDANT_ON	0x21b
-#define KEY_ATTENDANT_OFF	0x21c
-#define KEY_ATTENDANT_TOGGLE	0x21d	/* Attendant call on or off */
-#define KEY_LIGHTS_TOGGLE	0x21e	/* Reading light on or off */
-
-#define BTN_DPAD_UP		0x220
-#define BTN_DPAD_DOWN		0x221
-#define BTN_DPAD_LEFT		0x222
-#define BTN_DPAD_RIGHT		0x223
-
-#define KEY_ALS_TOGGLE		0x230	/* Ambient light sensor */
-#define KEY_ROTATE_LOCK_TOGGLE	0x231	/* Display rotation lock */
-
-#define KEY_BUTTONCONFIG		0x240	/* AL Button Configuration */
-#define KEY_TASKMANAGER		0x241	/* AL Task/Project Manager */
-#define KEY_JOURNAL		0x242	/* AL Log/Journal/Timecard */
-#define KEY_CONTROLPANEL		0x243	/* AL Control Panel */
-#define KEY_APPSELECT		0x244	/* AL Select Task/Application */
-#define KEY_SCREENSAVER		0x245	/* AL Screen Saver */
-#define KEY_VOICECOMMAND		0x246	/* Listening Voice Command */
-#define KEY_ASSISTANT		0x247	/* AL Context-aware desktop assistant */
-#define KEY_KBD_LAYOUT_NEXT	0x248	/* AC Next Keyboard Layout Select */
-#define KEY_EMOJI_PICKER	0x249	/* Show/hide emoji picker (HUTRR101) */
-#define KEY_DICTATE		0x24a	/* Start or Stop Voice Dictation Session (HUTRR99) */
-#define KEY_CAMERA_ACCESS_ENABLE	0x24b	/* Enables programmatic access to camera devices. (HUTRR72) */
-#define KEY_CAMERA_ACCESS_DISABLE	0x24c	/* Disables programmatic access to camera devices. (HUTRR72) */
-#define KEY_CAMERA_ACCESS_TOGGLE	0x24d	/* Toggles the current state of the camera access control. (HUTRR72) */
-
-#define KEY_BRIGHTNESS_MIN		0x250	/* Set Brightness to Minimum */
-#define KEY_BRIGHTNESS_MAX		0x251	/* Set Brightness to Maximum */
-
-#define KEY_KBDINPUTASSIST_PREV		0x260
-#define KEY_KBDINPUTASSIST_NEXT		0x261
-#define KEY_KBDINPUTASSIST_PREVGROUP		0x262
-#define KEY_KBDINPUTASSIST_NEXTGROUP		0x263
-#define KEY_KBDINPUTASSIST_ACCEPT		0x264
-#define KEY_KBDINPUTASSIST_CANCEL		0x265
-
-/* Diagonal movement keys */
-#define KEY_RIGHT_UP			0x266
-#define KEY_RIGHT_DOWN			0x267
-#define KEY_LEFT_UP			0x268
-#define KEY_LEFT_DOWN			0x269
-
-#define KEY_ROOT_MENU			0x26a /* Show Device's Root Menu */
-/* Show Top Menu of the Media (e.g. DVD) */
-#define KEY_MEDIA_TOP_MENU		0x26b
-#define KEY_NUMERIC_11			0x26c
-#define KEY_NUMERIC_12			0x26d
-/*
- * Toggle Audio Description: refers to an audio service that helps blind and
- * visually impaired consumers understand the action in a program. Note: in
- * some countries this is referred to as "Video Description".
- */
-#define KEY_AUDIO_DESC			0x26e
-#define KEY_3D_MODE			0x26f
-#define KEY_NEXT_FAVORITE		0x270
-#define KEY_STOP_RECORD			0x271
-#define KEY_PAUSE_RECORD		0x272
-#define KEY_VOD				0x273 /* Video on Demand */
-#define KEY_UNMUTE			0x274
-#define KEY_FASTREVERSE			0x275
-#define KEY_SLOWREVERSE			0x276
-/*
- * Control a data application associated with the currently viewed channel,
- * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.)
- */
-#define KEY_DATA			0x277
-#define KEY_ONSCREEN_KEYBOARD		0x278
-/* Electronic privacy screen control */
-#define KEY_PRIVACY_SCREEN_TOGGLE	0x279
-
-/* Select an area of screen to be copied */
-#define KEY_SELECTIVE_SCREENSHOT	0x27a
-
-/* Move the focus to the next or previous user controllable element within a UI container */
-#define KEY_NEXT_ELEMENT               0x27b
-#define KEY_PREVIOUS_ELEMENT           0x27c
-
-/* Toggle Autopilot engagement */
-#define KEY_AUTOPILOT_ENGAGE_TOGGLE    0x27d
-
-/* Shortcut Keys */
-#define KEY_MARK_WAYPOINT              0x27e
-#define KEY_SOS                                0x27f
-#define KEY_NAV_CHART                  0x280
-#define KEY_FISHING_CHART              0x281
-#define KEY_SINGLE_RANGE_RADAR         0x282
-#define KEY_DUAL_RANGE_RADAR           0x283
-#define KEY_RADAR_OVERLAY              0x284
-#define KEY_TRADITIONAL_SONAR          0x285
-#define KEY_CLEARVU_SONAR              0x286
-#define KEY_SIDEVU_SONAR               0x287
-#define KEY_NAV_INFO                   0x288
-#define KEY_BRIGHTNESS_MENU            0x289
-
-/*
- * Some keyboards have keys which do not have a defined meaning, these keys
- * are intended to be programmed / bound to macros by the user. For most
- * keyboards with these macro-keys the key-sequence to inject, or action to
- * take, is all handled by software on the host side. So from the kernel's
- * point of view these are just normal keys.
- *
- * The KEY_MACRO# codes below are intended for such keys, which may be labeled
- * e.g. G1-G18, or S1 - S30. The KEY_MACRO# codes MUST NOT be used for keys
- * where the marking on the key does indicate a defined meaning / purpose.
- *
- * The KEY_MACRO# codes MUST also NOT be used as fallback for when no existing
- * KEY_FOO define matches the marking / purpose. In this case a new KEY_FOO
- * define MUST be added.
- */
-#define KEY_MACRO1			0x290
-#define KEY_MACRO2			0x291
-#define KEY_MACRO3			0x292
-#define KEY_MACRO4			0x293
-#define KEY_MACRO5			0x294
-#define KEY_MACRO6			0x295
-#define KEY_MACRO7			0x296
-#define KEY_MACRO8			0x297
-#define KEY_MACRO9			0x298
-#define KEY_MACRO10			0x299
-#define KEY_MACRO11			0x29a
-#define KEY_MACRO12			0x29b
-#define KEY_MACRO13			0x29c
-#define KEY_MACRO14			0x29d
-#define KEY_MACRO15			0x29e
-#define KEY_MACRO16			0x29f
-#define KEY_MACRO17			0x2a0
-#define KEY_MACRO18			0x2a1
-#define KEY_MACRO19			0x2a2
-#define KEY_MACRO20			0x2a3
-#define KEY_MACRO21			0x2a4
-#define KEY_MACRO22			0x2a5
-#define KEY_MACRO23			0x2a6
-#define KEY_MACRO24			0x2a7
-#define KEY_MACRO25			0x2a8
-#define KEY_MACRO26			0x2a9
-#define KEY_MACRO27			0x2aa
-#define KEY_MACRO28			0x2ab
-#define KEY_MACRO29			0x2ac
-#define KEY_MACRO30			0x2ad
-
-/*
- * Some keyboards with the macro-keys described above have some extra keys
- * for controlling the host-side software responsible for the macro handling:
- * -A macro recording start/stop key. Note that not all keyboards which emit
- *  KEY_MACRO_RECORD_START will also emit KEY_MACRO_RECORD_STOP if
- *  KEY_MACRO_RECORD_STOP is not advertised, then KEY_MACRO_RECORD_START
- *  should be interpreted as a recording start/stop toggle;
- * -Keys for switching between different macro (pre)sets, either a key for
- *  cycling through the configured presets or keys to directly select a preset.
- */
-#define KEY_MACRO_RECORD_START		0x2b0
-#define KEY_MACRO_RECORD_STOP		0x2b1
-#define KEY_MACRO_PRESET_CYCLE		0x2b2
-#define KEY_MACRO_PRESET1		0x2b3
-#define KEY_MACRO_PRESET2		0x2b4
-#define KEY_MACRO_PRESET3		0x2b5
-
-/*
- * Some keyboards have a buildin LCD panel where the contents are controlled
- * by the host. Often these have a number of keys directly below the LCD
- * intended for controlling a menu shown on the LCD. These keys often don't
- * have any labeling so we just name them KEY_KBD_LCD_MENU#
- */
-#define KEY_KBD_LCD_MENU1		0x2b8
-#define KEY_KBD_LCD_MENU2		0x2b9
-#define KEY_KBD_LCD_MENU3		0x2ba
-#define KEY_KBD_LCD_MENU4		0x2bb
-#define KEY_KBD_LCD_MENU5		0x2bc
-
-#define BTN_TRIGGER_HAPPY		0x2c0
-#define BTN_TRIGGER_HAPPY1		0x2c0
-#define BTN_TRIGGER_HAPPY2		0x2c1
-#define BTN_TRIGGER_HAPPY3		0x2c2
-#define BTN_TRIGGER_HAPPY4		0x2c3
-#define BTN_TRIGGER_HAPPY5		0x2c4
-#define BTN_TRIGGER_HAPPY6		0x2c5
-#define BTN_TRIGGER_HAPPY7		0x2c6
-#define BTN_TRIGGER_HAPPY8		0x2c7
-#define BTN_TRIGGER_HAPPY9		0x2c8
-#define BTN_TRIGGER_HAPPY10		0x2c9
-#define BTN_TRIGGER_HAPPY11		0x2ca
-#define BTN_TRIGGER_HAPPY12		0x2cb
-#define BTN_TRIGGER_HAPPY13		0x2cc
-#define BTN_TRIGGER_HAPPY14		0x2cd
-#define BTN_TRIGGER_HAPPY15		0x2ce
-#define BTN_TRIGGER_HAPPY16		0x2cf
-#define BTN_TRIGGER_HAPPY17		0x2d0
-#define BTN_TRIGGER_HAPPY18		0x2d1
-#define BTN_TRIGGER_HAPPY19		0x2d2
-#define BTN_TRIGGER_HAPPY20		0x2d3
-#define BTN_TRIGGER_HAPPY21		0x2d4
-#define BTN_TRIGGER_HAPPY22		0x2d5
-#define BTN_TRIGGER_HAPPY23		0x2d6
-#define BTN_TRIGGER_HAPPY24		0x2d7
-#define BTN_TRIGGER_HAPPY25		0x2d8
-#define BTN_TRIGGER_HAPPY26		0x2d9
-#define BTN_TRIGGER_HAPPY27		0x2da
-#define BTN_TRIGGER_HAPPY28		0x2db
-#define BTN_TRIGGER_HAPPY29		0x2dc
-#define BTN_TRIGGER_HAPPY30		0x2dd
-#define BTN_TRIGGER_HAPPY31		0x2de
-#define BTN_TRIGGER_HAPPY32		0x2df
-#define BTN_TRIGGER_HAPPY33		0x2e0
-#define BTN_TRIGGER_HAPPY34		0x2e1
-#define BTN_TRIGGER_HAPPY35		0x2e2
-#define BTN_TRIGGER_HAPPY36		0x2e3
-#define BTN_TRIGGER_HAPPY37		0x2e4
-#define BTN_TRIGGER_HAPPY38		0x2e5
-#define BTN_TRIGGER_HAPPY39		0x2e6
-#define BTN_TRIGGER_HAPPY40		0x2e7
-
-/* We avoid low common keys in module aliases so they don't get huge. */
-#define KEY_MIN_INTERESTING	KEY_MUTE
-#define KEY_MAX			0x2ff
-#define KEY_CNT			(KEY_MAX+1)
-
-/*
- * Relative axes
- */
-
-#define REL_X			0x00
-#define REL_Y			0x01
-#define REL_Z			0x02
-#define REL_RX			0x03
-#define REL_RY			0x04
-#define REL_RZ			0x05
-#define REL_HWHEEL		0x06
-#define REL_DIAL		0x07
-#define REL_WHEEL		0x08
-#define REL_MISC		0x09
-/*
- * 0x0a is reserved and should not be used in input drivers.
- * It was used by HID as REL_MISC+1 and userspace needs to detect if
- * the next REL_* event is correct or is just REL_MISC + n.
- * We define here REL_RESERVED so userspace can rely on it and detect
- * the situation described above.
- */
-#define REL_RESERVED		0x0a
-#define REL_WHEEL_HI_RES	0x0b
-#define REL_HWHEEL_HI_RES	0x0c
-#define REL_MAX			0x0f
-#define REL_CNT			(REL_MAX+1)
-
-/*
- * Absolute axes
- */
-
-#define ABS_X			0x00
-#define ABS_Y			0x01
-#define ABS_Z			0x02
-#define ABS_RX			0x03
-#define ABS_RY			0x04
-#define ABS_RZ			0x05
-#define ABS_THROTTLE		0x06
-#define ABS_RUDDER		0x07
-#define ABS_WHEEL		0x08
-#define ABS_GAS			0x09
-#define ABS_BRAKE		0x0a
-#define ABS_HAT0X		0x10
-#define ABS_HAT0Y		0x11
-#define ABS_HAT1X		0x12
-#define ABS_HAT1Y		0x13
-#define ABS_HAT2X		0x14
-#define ABS_HAT2Y		0x15
-#define ABS_HAT3X		0x16
-#define ABS_HAT3Y		0x17
-#define ABS_PRESSURE		0x18
-#define ABS_DISTANCE		0x19
-#define ABS_TILT_X		0x1a
-#define ABS_TILT_Y		0x1b
-#define ABS_TOOL_WIDTH		0x1c
-
-#define ABS_VOLUME		0x20
-#define ABS_PROFILE		0x21
-
-#define ABS_MISC		0x28
-
-/*
- * 0x2e is reserved and should not be used in input drivers.
- * It was used by HID as ABS_MISC+6 and userspace needs to detect if
- * the next ABS_* event is correct or is just ABS_MISC + n.
- * We define here ABS_RESERVED so userspace can rely on it and detect
- * the situation described above.
- */
-#define ABS_RESERVED		0x2e
-
-#define ABS_MT_SLOT		0x2f	/* MT slot being modified */
-#define ABS_MT_TOUCH_MAJOR	0x30	/* Major axis of touching ellipse */
-#define ABS_MT_TOUCH_MINOR	0x31	/* Minor axis (omit if circular) */
-#define ABS_MT_WIDTH_MAJOR	0x32	/* Major axis of approaching ellipse */
-#define ABS_MT_WIDTH_MINOR	0x33	/* Minor axis (omit if circular) */
-#define ABS_MT_ORIENTATION	0x34	/* Ellipse orientation */
-#define ABS_MT_POSITION_X	0x35	/* Center X touch position */
-#define ABS_MT_POSITION_Y	0x36	/* Center Y touch position */
-#define ABS_MT_TOOL_TYPE	0x37	/* Type of touching device */
-#define ABS_MT_BLOB_ID		0x38	/* Group a set of packets as a blob */
-#define ABS_MT_TRACKING_ID	0x39	/* Unique ID of initiated contact */
-#define ABS_MT_PRESSURE		0x3a	/* Pressure on contact area */
-#define ABS_MT_DISTANCE		0x3b	/* Contact hover distance */
-#define ABS_MT_TOOL_X		0x3c	/* Center X tool position */
-#define ABS_MT_TOOL_Y		0x3d	/* Center Y tool position */
-
-
-#define ABS_MAX			0x3f
-#define ABS_CNT			(ABS_MAX+1)
-
-/*
- * Switch events
- */
-
-#define SW_LID			0x00  /* set = lid shut */
-#define SW_TABLET_MODE		0x01  /* set = tablet mode */
-#define SW_HEADPHONE_INSERT	0x02  /* set = inserted */
-#define SW_RFKILL_ALL		0x03  /* rfkill master switch, type "any"
-					 set = radio enabled */
-#define SW_RADIO		SW_RFKILL_ALL	/* deprecated */
-#define SW_MICROPHONE_INSERT	0x04  /* set = inserted */
-#define SW_DOCK			0x05  /* set = plugged into dock */
-#define SW_LINEOUT_INSERT	0x06  /* set = inserted */
-#define SW_JACK_PHYSICAL_INSERT 0x07  /* set = mechanical switch set */
-#define SW_VIDEOOUT_INSERT	0x08  /* set = inserted */
-#define SW_CAMERA_LENS_COVER	0x09  /* set = lens covered */
-#define SW_KEYPAD_SLIDE		0x0a  /* set = keypad slide out */
-#define SW_FRONT_PROXIMITY	0x0b  /* set = front proximity sensor active */
-#define SW_ROTATE_LOCK		0x0c  /* set = rotate locked/disabled */
-#define SW_LINEIN_INSERT	0x0d  /* set = inserted */
-#define SW_MUTE_DEVICE		0x0e  /* set = device disabled */
-#define SW_PEN_INSERTED		0x0f  /* set = pen inserted */
-#define SW_MACHINE_COVER	0x10  /* set = cover closed */
-#define SW_MAX			0x10
-#define SW_CNT			(SW_MAX+1)
-
-/*
- * Misc events
- */
-
-#define MSC_SERIAL		0x00
-#define MSC_PULSELED		0x01
-#define MSC_GESTURE		0x02
-#define MSC_RAW			0x03
-#define MSC_SCAN		0x04
-#define MSC_TIMESTAMP		0x05
-#define MSC_MAX			0x07
-#define MSC_CNT			(MSC_MAX+1)
-
-/*
- * LEDs
- */
-
-#define LED_NUML		0x00
-#define LED_CAPSL		0x01
-#define LED_SCROLLL		0x02
-#define LED_COMPOSE		0x03
-#define LED_KANA		0x04
-#define LED_SLEEP		0x05
-#define LED_SUSPEND		0x06
-#define LED_MUTE		0x07
-#define LED_MISC		0x08
-#define LED_MAIL		0x09
-#define LED_CHARGING		0x0a
-#define LED_MAX			0x0f
-#define LED_CNT			(LED_MAX+1)
-
-/*
- * Autorepeat values
- */
-
-#define REP_DELAY		0x00
-#define REP_PERIOD		0x01
-#define REP_MAX			0x01
-#define REP_CNT			(REP_MAX+1)
-
-/*
- * Sounds
- */
-
-#define SND_CLICK		0x00
-#define SND_BELL		0x01
-#define SND_TONE		0x02
-#define SND_MAX			0x07
-#define SND_CNT			(SND_MAX+1)
-
-#endif

include/kernel/dt-bindings/interrupt-controller/arm-gic.h

@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-/*
- * This header provides constants for the ARM GIC.
- */
-
-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
-
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/* interrupt specifier cell 0 */
-
-#define GIC_SPI 0
-#define GIC_PPI 1
-
-/*
- * Interrupt specifier cell 2.
- * The flags in irq.h are valid, plus those below.
- */
-#define GIC_CPU_MASK_RAW(x) ((x) << 8)
-#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
-
-#endif

include/kernel/dt-bindings/interrupt-controller/irq.h

@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-/*
- * This header provides constants for most IRQ bindings.
- *
- * Most IRQ bindings include a flags cell as part of the IRQ specifier.
- * In most cases, the format of the flags cell uses the standard values
- * defined in this header.
- */
-
-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
-
-#define IRQ_TYPE_NONE		0
-#define IRQ_TYPE_EDGE_RISING	1
-#define IRQ_TYPE_EDGE_FALLING	2
-#define IRQ_TYPE_EDGE_BOTH	(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
-#define IRQ_TYPE_LEVEL_HIGH	4
-#define IRQ_TYPE_LEVEL_LOW	8
-
-#endif

include/kernel/dt-bindings/mailbox/tegra186-hsp.h

@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for binding nvidia,tegra186-hsp.
- */
-
-#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
-#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
-
-/*
- * These define the type of mailbox that is to be used (doorbell, shared
- * mailbox, shared semaphore or arbitrated semaphore).
- */
-#define TEGRA_HSP_MBOX_TYPE_DB 0x0
-#define TEGRA_HSP_MBOX_TYPE_SM 0x1
-#define TEGRA_HSP_MBOX_TYPE_SS 0x2
-#define TEGRA_HSP_MBOX_TYPE_AS 0x3
-
-/*
- * These define the types of shared mailbox supported based on data size.
- */
-#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8)
-
-/*
- * These defines represent the bit associated with the given master ID in the
- * doorbell registers.
- */
-#define TEGRA_HSP_DB_MASTER_CCPLEX 17
-#define TEGRA_HSP_DB_MASTER_BPMP 19
-
-/*
- * Shared mailboxes are unidirectional, so the direction needs to be specified
- * in the device tree.
- */
-#define TEGRA_HSP_SM_MASK 0x00ffffff
-#define TEGRA_HSP_SM_FLAG_RX (0 << 31)
-#define TEGRA_HSP_SM_FLAG_TX (1 << 31)
-
-#define TEGRA_HSP_SM_RX(x) (TEGRA_HSP_SM_FLAG_RX | ((x) & TEGRA_HSP_SM_MASK))
-#define TEGRA_HSP_SM_TX(x) (TEGRA_HSP_SM_FLAG_TX | ((x) & TEGRA_HSP_SM_MASK))
-
-#endif

include/kernel/dt-bindings/memory/tegra234-mc.h

@@ -1,539 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
-
-#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA234_MC_H
-
-/* special clients */
-#define TEGRA234_SID_INVALID		0x00
-#define TEGRA234_SID_PASSTHROUGH	0x7f
-
-/* ISO stream IDs */
-#define TEGRA234_SID_ISO_NVDISPLAY	0x01
-#define TEGRA234_SID_ISO_VI		0x02
-#define TEGRA234_SID_ISO_VIFALC		0x03
-#define TEGRA234_SID_ISO_VI2		0x04
-#define TEGRA234_SID_ISO_VI2FALC	0x05
-#define TEGRA234_SID_ISO_VI_VM2		0x06
-#define TEGRA234_SID_ISO_VI2_VM2	0x07
-
-/* NISO0 stream IDs */
-#define TEGRA234_SID_AON		0x01
-#define TEGRA234_SID_APE		0x02
-#define TEGRA234_SID_HDA		0x03
-#define TEGRA234_SID_GPCDMA		0x04
-#define TEGRA234_SID_ETR		0x05
-#define TEGRA234_SID_MGBE		0x06
-#define TEGRA234_SID_NVDISPLAY		0x07
-#define TEGRA234_SID_DCE		0x08
-#define TEGRA234_SID_PSC		0x09
-#define TEGRA234_SID_RCE		0x0a
-#define TEGRA234_SID_SCE		0x0b
-#define TEGRA234_SID_UFSHC		0x0c
-#define TEGRA234_SID_APE_1		0x0d
-#define TEGRA234_SID_GPCDMA_1		0x0e
-#define TEGRA234_SID_GPCDMA_2		0x0f
-#define TEGRA234_SID_GPCDMA_3		0x10
-#define TEGRA234_SID_GPCDMA_4		0x11
-#define TEGRA234_SID_PCIE0		0x12
-#define TEGRA234_SID_PCIE4		0x13
-#define TEGRA234_SID_PCIE5		0x14
-#define TEGRA234_SID_PCIE6		0x15
-#define TEGRA234_SID_RCE_VM2		0x16
-#define TEGRA234_SID_RCE_SERVER		0x17
-#define TEGRA234_SID_SMMU_TEST		0x18
-#define TEGRA234_SID_UFS_1		0x19
-#define TEGRA234_SID_UFS_2		0x1a
-#define TEGRA234_SID_UFS_3		0x1b
-#define TEGRA234_SID_UFS_4		0x1c
-#define TEGRA234_SID_UFS_5		0x1d
-#define TEGRA234_SID_UFS_6		0x1e
-#define TEGRA234_SID_PCIE9		0x1f
-#define TEGRA234_SID_VSE_GPCDMA_VM0	0x20
-#define TEGRA234_SID_VSE_GPCDMA_VM1	0x21
-#define TEGRA234_SID_VSE_GPCDMA_VM2	0x22
-#define TEGRA234_SID_NVDLA1		0x23
-#define TEGRA234_SID_NVENC		0x24
-#define TEGRA234_SID_NVJPG1		0x25
-#define TEGRA234_SID_OFA		0x26
-#define TEGRA234_SID_MGBE_VF1		0x49
-#define TEGRA234_SID_MGBE_VF2		0x4a
-#define TEGRA234_SID_MGBE_VF3		0x4b
-#define TEGRA234_SID_MGBE_VF4		0x4c
-#define TEGRA234_SID_MGBE_VF5		0x4d
-#define TEGRA234_SID_MGBE_VF6		0x4e
-#define TEGRA234_SID_MGBE_VF7		0x4f
-#define TEGRA234_SID_MGBE_VF8		0x50
-#define TEGRA234_SID_MGBE_VF9		0x51
-#define TEGRA234_SID_MGBE_VF10		0x52
-#define TEGRA234_SID_MGBE_VF11		0x53
-#define TEGRA234_SID_MGBE_VF12		0x54
-#define TEGRA234_SID_MGBE_VF13		0x55
-#define TEGRA234_SID_MGBE_VF14		0x56
-#define TEGRA234_SID_MGBE_VF15		0x57
-#define TEGRA234_SID_MGBE_VF16		0x58
-#define TEGRA234_SID_MGBE_VF17		0x59
-#define TEGRA234_SID_MGBE_VF18		0x5a
-#define TEGRA234_SID_MGBE_VF19		0x5b
-#define TEGRA234_SID_MGBE_VF20		0x5c
-#define TEGRA234_SID_APE_2		0x5e
-#define TEGRA234_SID_APE_3		0x5f
-#define TEGRA234_SID_UFS_7		0x60
-#define TEGRA234_SID_UFS_8		0x61
-#define TEGRA234_SID_UFS_9		0x62
-#define TEGRA234_SID_UFS_10		0x63
-#define TEGRA234_SID_UFS_11		0x64
-#define TEGRA234_SID_UFS_12		0x65
-#define TEGRA234_SID_UFS_13		0x66
-#define TEGRA234_SID_UFS_14		0x67
-#define TEGRA234_SID_UFS_15		0x68
-#define TEGRA234_SID_UFS_16		0x69
-#define TEGRA234_SID_UFS_17		0x6a
-#define TEGRA234_SID_UFS_18		0x6b
-#define TEGRA234_SID_UFS_19		0x6c
-#define TEGRA234_SID_UFS_20		0x6d
-#define TEGRA234_SID_GPCDMA_5		0x6e
-#define TEGRA234_SID_GPCDMA_6		0x6f
-#define TEGRA234_SID_GPCDMA_7		0x70
-#define TEGRA234_SID_GPCDMA_8		0x71
-#define TEGRA234_SID_GPCDMA_9		0x72
-
-/* NISO1 stream IDs */
-#define TEGRA234_SID_SDMMC1A		0x01
-#define TEGRA234_SID_SDMMC4		0x02
-#define TEGRA234_SID_EQOS		0x03
-#define TEGRA234_SID_HWMP_PMA		0x04
-#define TEGRA234_SID_PCIE1		0x05
-#define TEGRA234_SID_PCIE2		0x06
-#define TEGRA234_SID_PCIE3		0x07
-#define TEGRA234_SID_PCIE7		0x08
-#define TEGRA234_SID_PCIE8		0x09
-#define TEGRA234_SID_PCIE10		0x0b
-#define TEGRA234_SID_QSPI0		0x0c
-#define TEGRA234_SID_QSPI1		0x0d
-#define TEGRA234_SID_XUSB_HOST		0x0e
-#define TEGRA234_SID_XUSB_DEV		0x0f
-#define TEGRA234_SID_BPMP		0x10
-#define TEGRA234_SID_FSI		0x11
-#define TEGRA234_SID_PVA0_VM0		0x12
-#define TEGRA234_SID_PVA0_VM1		0x13
-#define TEGRA234_SID_PVA0_VM2		0x14
-#define TEGRA234_SID_PVA0_VM3		0x15
-#define TEGRA234_SID_PVA0_VM4		0x16
-#define TEGRA234_SID_PVA0_VM5		0x17
-#define TEGRA234_SID_PVA0_VM6		0x18
-#define TEGRA234_SID_PVA0_VM7		0x19
-#define TEGRA234_SID_XUSB_VF0		0x1a
-#define TEGRA234_SID_XUSB_VF1		0x1b
-#define TEGRA234_SID_XUSB_VF2		0x1c
-#define TEGRA234_SID_XUSB_VF3		0x1d
-#define TEGRA234_SID_EQOS_VF1		0x1e
-#define TEGRA234_SID_EQOS_VF2		0x1f
-#define TEGRA234_SID_EQOS_VF3		0x20
-#define TEGRA234_SID_EQOS_VF4		0x21
-#define TEGRA234_SID_ISP_VM2		0x22
-#define TEGRA234_SID_HOST1X		0x27
-#define TEGRA234_SID_ISP		0x28
-#define TEGRA234_SID_NVDEC		0x29
-#define TEGRA234_SID_NVJPG		0x2a
-#define TEGRA234_SID_NVDLA0		0x2b
-#define TEGRA234_SID_PVA0		0x2c
-#define TEGRA234_SID_SES_SE0		0x2d
-#define TEGRA234_SID_SES_SE1		0x2e
-#define TEGRA234_SID_SES_SE2		0x2f
-#define TEGRA234_SID_SEU1_SE0		0x30
-#define TEGRA234_SID_SEU1_SE1		0x31
-#define TEGRA234_SID_SEU1_SE2		0x32
-#define TEGRA234_SID_TSEC		0x33
-#define TEGRA234_SID_VIC		0x34
-#define TEGRA234_SID_HC_VM0		0x3d
-#define TEGRA234_SID_HC_VM1		0x3e
-#define TEGRA234_SID_HC_VM2		0x3f
-#define TEGRA234_SID_HC_VM3		0x40
-#define TEGRA234_SID_HC_VM4		0x41
-#define TEGRA234_SID_HC_VM5		0x42
-#define TEGRA234_SID_HC_VM6		0x43
-#define TEGRA234_SID_HC_VM7		0x44
-#define TEGRA234_SID_SE_VM0		0x45
-#define TEGRA234_SID_SE_VM1		0x46
-#define TEGRA234_SID_SE_VM2		0x47
-#define TEGRA234_SID_ISPFALC		0x48
-#define TEGRA234_SID_NISO1_SMMU_TEST	0x49
-#define TEGRA234_SID_TSEC_VM0		0x4a
-
-/* Shared stream IDs */
-#define TEGRA234_SID_HOST1X_CTX0	0x35
-#define TEGRA234_SID_HOST1X_CTX1	0x36
-#define TEGRA234_SID_HOST1X_CTX2	0x37
-#define TEGRA234_SID_HOST1X_CTX3	0x38
-#define TEGRA234_SID_HOST1X_CTX4	0x39
-#define TEGRA234_SID_HOST1X_CTX5	0x3a
-#define TEGRA234_SID_HOST1X_CTX6	0x3b
-#define TEGRA234_SID_HOST1X_CTX7	0x3c
-
-/*
- * memory client IDs
- */
-
-/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */
-#define TEGRA234_MEMORY_CLIENT_PTCR 0x00
-/* MSS internal memqual MIU7 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU7R 0x01
-/* MSS internal memqual MIU7 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU7W 0x02
-/* MSS internal memqual MIU8 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU8R 0x03
-/* MSS internal memqual MIU8 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU8W 0x04
-/* MSS internal memqual MIU9 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU9R 0x05
-/* MSS internal memqual MIU9 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU9W 0x06
-/* MSS internal memqual MIU10 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU10R 0x07
-/* MSS internal memqual MIU10 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU10W 0x08
-/* MSS internal memqual MIU11 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU11R 0x09
-/* MSS internal memqual MIU11 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU11W 0x0a
-/* MSS internal memqual MIU12 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU12R 0x0b
-/* MSS internal memqual MIU12 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU12W 0x0c
-/* MSS internal memqual MIU13 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU13R 0x0d
-/* MSS internal memqual MIU13 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU13W 0x0e
-#define TEGRA234_MEMORY_CLIENT_NVL5RHP 0x13
-#define TEGRA234_MEMORY_CLIENT_NVL5R 0x14
-/* High-definition audio (HDA) read clients */
-#define TEGRA234_MEMORY_CLIENT_HDAR 0x15
-/* Host channel data read clients */
-#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16
-#define TEGRA234_MEMORY_CLIENT_NVL5W 0x17
-#define TEGRA234_MEMORY_CLIENT_NVL6RHP 0x18
-#define TEGRA234_MEMORY_CLIENT_NVL6R 0x19
-#define TEGRA234_MEMORY_CLIENT_NVL6W 0x1a
-#define TEGRA234_MEMORY_CLIENT_NVL7RHP 0x1b
-#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c
-#define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d
-#define TEGRA234_MEMORY_CLIENT_NVL7W 0x1e
-#define TEGRA234_MEMORY_CLIENT_NVL8RHP 0x20
-#define TEGRA234_MEMORY_CLIENT_NVL8R 0x21
-#define TEGRA234_MEMORY_CLIENT_NVL8W 0x22
-#define TEGRA234_MEMORY_CLIENT_NVL9RHP 0x23
-#define TEGRA234_MEMORY_CLIENT_NVL9R 0x24
-#define TEGRA234_MEMORY_CLIENT_NVL9W 0x25
-/* PCIE6 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
-/* PCIE6 write clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29
-/* PCIE7 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a
-#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b
-/* DLA0ARDB read clients */
-#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c
-/* DLA0ARDB1 read clients */
-#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d
-/* DLA0 writes */
-#define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e
-/* DLA1ARDB read clients */
-#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f
-/* PCIE7 write clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30
-/* PCIE8 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32
-/* High-definition audio (HDA) write clients */
-#define TEGRA234_MEMORY_CLIENT_HDAW 0x35
-/* Writes from Cortex-A9 4 CPU cores via the L2 cache */
-#define TEGRA234_MEMORY_CLIENT_MPCOREW 0x39
-/* OFAA client */
-#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a
-/* PCIE8 write clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b
-/* PCIE9 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c
-/* PCIE6r1 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d
-/* PCIE9 write clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e
-/* PCIE10 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f
-/* PCIE10 write clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40
-/* ISP read client for Crossbar A */
-#define TEGRA234_MEMORY_CLIENT_ISPRA 0x44
-/* ISP read client 1 for Crossbar A */
-#define TEGRA234_MEMORY_CLIENT_ISPFALR 0x45
-/* ISP Write client for Crossbar A */
-#define TEGRA234_MEMORY_CLIENT_ISPWA 0x46
-/* ISP Write client Crossbar B */
-#define TEGRA234_MEMORY_CLIENT_ISPWB 0x47
-/* PCIE10r1 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
-/* PCIE7r1 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
-/* XUSB_HOST read clients */
-#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTR 0x4a
-/* XUSB_HOST write clients */
-#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTW 0x4b
-/* XUSB read clients */
-#define TEGRA234_MEMORY_CLIENT_XUSB_DEVR 0x4c
-/* XUSB_DEV write clients */
-#define TEGRA234_MEMORY_CLIENT_XUSB_DEVW 0x4d
-/* TSEC Memory Return Data Client Description */
-#define TEGRA234_MEMORY_CLIENT_TSECSRD 0x54
-/* TSEC Memory Write Client Description */
-#define TEGRA234_MEMORY_CLIENT_TSECSWR 0x55
-/* XSPI writes */
-#define TEGRA234_MEMORY_CLIENT_XSPI1W 0x56
-/* MGBE0 read client */
-#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58
-/* MGBEB read client */
-#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59
-/* MGBEC read client */
-#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a
-/* MGBED read client */
-#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b
-/* MGBE0 write client */
-#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c
-/* OFAA client */
-#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d
-/* OFAA writes */
-#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e
-/* MGBEB write client */
-#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f
-/* sdmmca memory read client */
-#define TEGRA234_MEMORY_CLIENT_SDMMCRA 0x60
-/* MGBEC write client */
-#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61
-/* sdmmcd memory read client */
-#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
-/* sdmmca memory write client */
-#define TEGRA234_MEMORY_CLIENT_SDMMCWA 0x64
-/* MGBED write client */
-#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65
-/* sdmmcd memory write client */
-#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
-/* SE Memory Return Data Client Description */
-#define TEGRA234_MEMORY_CLIENT_SEU1RD 0x68
-/* SE Memory Write Client Description */
-#define TEGRA234_MEMORY_CLIENT_SUE1WR 0x69
-#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c
-#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d
-/* DLA1ARDB1 read clients */
-#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e
-/* DLA1 writes */
-#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f
-/* VI FLACON read clients */
-#define TEGRA234_MEMORY_CLIENT_VI2FALR 0x71
-/* VI Write client */
-#define TEGRA234_MEMORY_CLIENT_VI2W 0x70
-/* VI Write client */
-#define TEGRA234_MEMORY_CLIENT_VIW 0x72
-/* NISO display read client */
-#define TEGRA234_MEMORY_CLIENT_NVDISPNISOR 0x73
-/* NVDISPNISO writes */
-#define TEGRA234_MEMORY_CLIENT_NVDISPNISOW 0x74
-/* XSPI client */
-#define TEGRA234_MEMORY_CLIENT_XSPI0R 0x75
-/* XSPI writes */
-#define TEGRA234_MEMORY_CLIENT_XSPI0W 0x76
-/* XSPI client */
-#define TEGRA234_MEMORY_CLIENT_XSPI1R 0x77
-#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78
-#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79
-/* Audio Processing (APE) engine read clients */
-#define TEGRA234_MEMORY_CLIENT_APER 0x7a
-/* Audio Processing (APE) engine write clients */
-#define TEGRA234_MEMORY_CLIENT_APEW 0x7b
-/* VI2FAL writes */
-#define TEGRA234_MEMORY_CLIENT_VI2FALW 0x7c
-#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e
-#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f
-/* SE Memory Return Data Client Description */
-#define TEGRA234_MEMORY_CLIENT_SESRD 0x80
-/* SE Memory Write Client Description */
-#define TEGRA234_MEMORY_CLIENT_SESWR 0x81
-/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */
-#define TEGRA234_MEMORY_CLIENT_AXIAPR 0x82
-/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */
-#define TEGRA234_MEMORY_CLIENT_AXIAPW 0x83
-/* ETR read clients */
-#define TEGRA234_MEMORY_CLIENT_ETRR 0x84
-/* ETR write clients */
-#define TEGRA234_MEMORY_CLIENT_ETRW 0x85
-/* AXI Switch read client */
-#define TEGRA234_MEMORY_CLIENT_AXISR 0x8c
-/* AXI Switch write client */
-#define TEGRA234_MEMORY_CLIENT_AXISW 0x8d
-/* EQOS read client */
-#define TEGRA234_MEMORY_CLIENT_EQOSR 0x8e
-/* EQOS write client */
-#define TEGRA234_MEMORY_CLIENT_EQOSW 0x8f
-/* UFSHC read client */
-#define TEGRA234_MEMORY_CLIENT_UFSHCR 0x90
-/* UFSHC write client */
-#define TEGRA234_MEMORY_CLIENT_UFSHCW 0x91
-/* NVDISPLAY read client */
-#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR 0x92
-/* BPMP read client */
-#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
-/* BPMP write client */
-#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94
-/* BPMPDMA read client */
-#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
-/* BPMPDMA write client */
-#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
-/* AON read client */
-#define TEGRA234_MEMORY_CLIENT_AONR 0x97
-/* AON write client */
-#define TEGRA234_MEMORY_CLIENT_AONW 0x98
-/* AONDMA read client */
-#define TEGRA234_MEMORY_CLIENT_AONDMAR 0x99
-/* AONDMA write client */
-#define TEGRA234_MEMORY_CLIENT_AONDMAW 0x9a
-/* SCE read client */
-#define TEGRA234_MEMORY_CLIENT_SCER 0x9b
-/* SCE write client */
-#define TEGRA234_MEMORY_CLIENT_SCEW 0x9c
-/* SCEDMA read client */
-#define TEGRA234_MEMORY_CLIENT_SCEDMAR 0x9d
-/* SCEDMA write client */
-#define TEGRA234_MEMORY_CLIENT_SCEDMAW 0x9e
-/* APEDMA read client */
-#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f
-/* APEDMA write client */
-#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0
-/* NVDISPLAY read client instance 2 */
-#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 0xa1
-#define TEGRA234_MEMORY_CLIENT_VICSRD1 0xa2
-/* MSS internal memqual MIU0 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU0R 0xa6
-/* MSS internal memqual MIU0 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU0W 0xa7
-/* MSS internal memqual MIU1 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU1R 0xa8
-/* MSS internal memqual MIU1 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU1W 0xa9
-/* MSS internal memqual MIU2 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU2R 0xae
-/* MSS internal memqual MIU2 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU2W 0xaf
-/* MSS internal memqual MIU3 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU3R 0xb0
-/* MSS internal memqual MIU3 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU3W 0xb1
-/* MSS internal memqual MIU4 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU4R 0xb2
-/* MSS internal memqual MIU4 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU4W 0xb3
-#define TEGRA234_MEMORY_CLIENT_DPMUR 0xb4
-#define TEGRA234_MEMORY_CLIENT_DPMUW 0xb5
-#define TEGRA234_MEMORY_CLIENT_NVL0R 0xb6
-#define TEGRA234_MEMORY_CLIENT_NVL0W 0xb7
-#define TEGRA234_MEMORY_CLIENT_NVL1R 0xb8
-#define TEGRA234_MEMORY_CLIENT_NVL1W 0xb9
-#define TEGRA234_MEMORY_CLIENT_NVL2R 0xba
-#define TEGRA234_MEMORY_CLIENT_NVL2W 0xbb
-/* VI FLACON read clients */
-#define TEGRA234_MEMORY_CLIENT_VIFALR 0xbc
-/* VIFAL write clients */
-#define TEGRA234_MEMORY_CLIENT_VIFALW 0xbd
-/* DLA0ARDA read clients */
-#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe
-/* DLA0 Falcon read clients */
-#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf
-/* DLA0 write clients */
-#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0
-/* DLA0 write clients */
-#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1
-/* DLA1ARDA read clients */
-#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2
-/* DLA1 Falcon read clients */
-#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3
-/* DLA1 write clients */
-#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4
-/* DLA1 write clients */
-#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5
-/* PVA0RDA read clients */
-#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6
-/* PVA0RDB read clients */
-#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7
-/* PVA0RDC read clients */
-#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8
-/* PVA0WRA write clients */
-#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9
-/* PVA0WRB write clients */
-#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca
-/* PVA0WRC write clients */
-#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb
-/* RCE read client */
-#define TEGRA234_MEMORY_CLIENT_RCER 0xd2
-/* RCE write client */
-#define TEGRA234_MEMORY_CLIENT_RCEW 0xd3
-/* RCEDMA read client */
-#define TEGRA234_MEMORY_CLIENT_RCEDMAR 0xd4
-/* RCEDMA write client */
-#define TEGRA234_MEMORY_CLIENT_RCEDMAW 0xd5
-/* PCIE0 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8
-/* PCIE0 write clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9
-/* PCIE1 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda
-/* PCIE1 write clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb
-/* PCIE2 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc
-/* PCIE2 write clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd
-/* PCIE3 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde
-/* PCIE3 write clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf
-/* PCIE4 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0
-/* PCIE4 write clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1
-/* PCIE5 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2
-/* PCIE5 write clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3
-/* ISP read client 1 for Crossbar A */
-#define TEGRA234_MEMORY_CLIENT_ISPFALW 0xe4
-#define TEGRA234_MEMORY_CLIENT_NVL3R 0xe5
-#define TEGRA234_MEMORY_CLIENT_NVL3W 0xe6
-#define TEGRA234_MEMORY_CLIENT_NVL4R 0xe7
-#define TEGRA234_MEMORY_CLIENT_NVL4W 0xe8
-/* DLA0ARDA1 read clients */
-#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9
-/* DLA1ARDA1 read clients */
-#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea
-/* PVA0RDA1 read clients */
-#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb
-/* PVA0RDB1 read clients */
-#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec
-/* PCIE5r1 read clients */
-#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef
-#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0
-/* ISP read client for Crossbar A */
-#define TEGRA234_MEMORY_CLIENT_ISPRA1 0xf2
-#define TEGRA234_MEMORY_CLIENT_NVL0RHP 0xf4
-#define TEGRA234_MEMORY_CLIENT_NVL1RHP 0xf5
-#define TEGRA234_MEMORY_CLIENT_NVL2RHP 0xf6
-#define TEGRA234_MEMORY_CLIENT_NVL3RHP 0xf7
-#define TEGRA234_MEMORY_CLIENT_NVL4RHP 0xf8
-/* MSS internal memqual MIU5 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU5R 0xfc
-/* MSS internal memqual MIU5 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU5W 0xfd
-/* MSS internal memqual MIU6 read clients */
-#define TEGRA234_MEMORY_CLIENT_MIU6R 0xfe
-/* MSS internal memqual MIU6 write clients */
-#define TEGRA234_MEMORY_CLIENT_MIU6W 0xff
-#define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123
-#define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124
-
-#endif

include/kernel/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * pinctrl-tegra-io-pad.h: Tegra I/O pad source voltage configuration constants
- * pinctrl bindings.
- *
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
- *
- * Author: Aapo Vienamo <avienamo@nvidia.com>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H
-#define _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H
-
-/* Voltage levels of the I/O pad's source rail */
-#define TEGRA_IO_PAD_VOLTAGE_1V8	0
-#define TEGRA_IO_PAD_VOLTAGE_3V3	1
-
-#endif

include/kernel/dt-bindings/pinctrl/pinctrl-tegra.h

@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * This header provides constants for Tegra pinctrl bindings.
- *
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Author: Laxman Dewangan <ldewangan@nvidia.com>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
-#define _DT_BINDINGS_PINCTRL_TEGRA_H
-
-/*
- * Enable/disable for diffeent dt properties. This is applicable for
- * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
- * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
- */
-#define TEGRA_PIN_DISABLE				0
-#define TEGRA_PIN_ENABLE				1
-
-#define TEGRA_PIN_PULL_NONE				0
-#define TEGRA_PIN_PULL_DOWN				1
-#define TEGRA_PIN_PULL_UP				2
-
-/* Low power mode driver */
-#define TEGRA_PIN_LP_DRIVE_DIV_8			0
-#define TEGRA_PIN_LP_DRIVE_DIV_4			1
-#define TEGRA_PIN_LP_DRIVE_DIV_2			2
-#define TEGRA_PIN_LP_DRIVE_DIV_1			3
-
-/* Rising/Falling slew rate */
-#define TEGRA_PIN_SLEW_RATE_FASTEST			0
-#define TEGRA_PIN_SLEW_RATE_FAST			1
-#define TEGRA_PIN_SLEW_RATE_SLOW			2
-#define TEGRA_PIN_SLEW_RATE_SLOWEST			3
-
-#endif

include/kernel/dt-bindings/power/tegra234-powergate.h

@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved. */
-
-#ifndef __ABI_MACH_T234_POWERGATE_T234_H_
-#define __ABI_MACH_T234_POWERGATE_T234_H_
-
-#define TEGRA234_POWER_DOMAIN_OFA	1U
-#define TEGRA234_POWER_DOMAIN_AUD	2U
-#define TEGRA234_POWER_DOMAIN_DISP	3U
-#define TEGRA234_POWER_DOMAIN_PCIEX8A	5U
-#define TEGRA234_POWER_DOMAIN_PCIEX4A	6U
-#define TEGRA234_POWER_DOMAIN_PCIEX4BA	7U
-#define TEGRA234_POWER_DOMAIN_PCIEX4BB	8U
-#define TEGRA234_POWER_DOMAIN_PCIEX1A	9U
-#define TEGRA234_POWER_DOMAIN_XUSBA	10U
-#define TEGRA234_POWER_DOMAIN_XUSBB	11U
-#define TEGRA234_POWER_DOMAIN_XUSBC	12U
-#define TEGRA234_POWER_DOMAIN_PCIEX4CA	13U
-#define TEGRA234_POWER_DOMAIN_PCIEX4CB	14U
-#define TEGRA234_POWER_DOMAIN_PCIEX4CC	15U
-#define TEGRA234_POWER_DOMAIN_PCIEX8B	16U
-#define TEGRA234_POWER_DOMAIN_MGBEA	17U
-#define TEGRA234_POWER_DOMAIN_MGBEB	18U
-#define TEGRA234_POWER_DOMAIN_MGBEC	19U
-#define TEGRA234_POWER_DOMAIN_MGBED	20U
-#define TEGRA234_POWER_DOMAIN_ISPA	22U
-#define TEGRA234_POWER_DOMAIN_NVDEC	23U
-#define TEGRA234_POWER_DOMAIN_NVJPGA	24U
-#define TEGRA234_POWER_DOMAIN_NVENC	25U
-#define TEGRA234_POWER_DOMAIN_VI	28U
-#define TEGRA234_POWER_DOMAIN_VIC	29U
-#define TEGRA234_POWER_DOMAIN_PVA	30U
-#define TEGRA234_POWER_DOMAIN_DLAA	32U
-#define TEGRA234_POWER_DOMAIN_DLAB	33U
-#define TEGRA234_POWER_DOMAIN_CV	34U
-#define TEGRA234_POWER_DOMAIN_GPU	35U
-#define TEGRA234_POWER_DOMAIN_NVJPGB	36U
-
-#endif

include/kernel/dt-bindings/reset/tegra234-reset.h

@@ -1,182 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
-
-#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
-#define DT_BINDINGS_RESET_TEGRA234_RESET_H
-
-/**
- * @file
- * @defgroup bpmp_reset_ids Reset ID's
- * @brief Identifiers for Resets controllable by firmware
- * @{
- */
-#define TEGRA234_RESET_ACTMON			1U
-#define TEGRA234_RESET_ADSP_ALL			2U
-#define TEGRA234_RESET_DSI_CORE			3U
-#define TEGRA234_RESET_CAN1			4U
-#define TEGRA234_RESET_CAN2			5U
-#define TEGRA234_RESET_DLA0			6U
-#define TEGRA234_RESET_DLA1			7U
-#define TEGRA234_RESET_DPAUX			8U
-#define TEGRA234_RESET_OFA			9U
-#define TEGRA234_RESET_NVJPG1			10U
-#define TEGRA234_RESET_PEX1_CORE_6		11U
-#define TEGRA234_RESET_PEX1_CORE_6_APB		12U
-#define TEGRA234_RESET_PEX1_COMMON_APB		13U
-#define TEGRA234_RESET_PEX2_CORE_7		14U
-#define TEGRA234_RESET_PEX2_CORE_7_APB		15U
-#define TEGRA234_RESET_NVDISPLAY		16U
-#define TEGRA234_RESET_EQOS			17U
-#define TEGRA234_RESET_GPCDMA			18U
-#define TEGRA234_RESET_GPU			19U
-#define TEGRA234_RESET_HDA			20U
-#define TEGRA234_RESET_HDACODEC			21U
-#define TEGRA234_RESET_EQOS_MACSEC		22U
-#define TEGRA234_RESET_EQOS_MACSEC_SECURE	23U
-#define TEGRA234_RESET_I2C1			24U
-#define TEGRA234_RESET_PEX2_CORE_8		25U
-#define TEGRA234_RESET_PEX2_CORE_8_APB		26U
-#define TEGRA234_RESET_PEX2_CORE_9		27U
-#define TEGRA234_RESET_PEX2_CORE_9_APB		28U
-#define TEGRA234_RESET_I2C2			29U
-#define TEGRA234_RESET_I2C3			30U
-#define TEGRA234_RESET_I2C4			31U
-#define TEGRA234_RESET_I2C6			32U
-#define TEGRA234_RESET_I2C7			33U
-#define TEGRA234_RESET_I2C8			34U
-#define TEGRA234_RESET_I2C9			35U
-#define TEGRA234_RESET_ISP			36U
-#define TEGRA234_RESET_MIPI_CAL			37U
-#define TEGRA234_RESET_MPHY_CLK_CTL		38U
-#define TEGRA234_RESET_MPHY_L0_RX		39U
-#define TEGRA234_RESET_MPHY_L0_TX		40U
-#define TEGRA234_RESET_MPHY_L1_RX		41U
-#define TEGRA234_RESET_MPHY_L1_TX		42U
-#define TEGRA234_RESET_NVCSI			43U
-#define TEGRA234_RESET_NVDEC			44U
-#define TEGRA234_RESET_MGBE0_PCS		45U
-#define TEGRA234_RESET_MGBE0_MAC		46U
-#define TEGRA234_RESET_MGBE0_MACSEC		47U
-#define TEGRA234_RESET_MGBE0_MACSEC_SECURE	48U
-#define TEGRA234_RESET_MGBE1_PCS		49U
-#define TEGRA234_RESET_MGBE1_MAC		50U
-#define TEGRA234_RESET_MGBE1_MACSEC		51U
-#define TEGRA234_RESET_MGBE1_MACSEC_SECURE	52U
-#define TEGRA234_RESET_MGBE2_PCS		53U
-#define TEGRA234_RESET_MGBE2_MAC		54U
-#define TEGRA234_RESET_MGBE2_MACSEC		55U
-#define TEGRA234_RESET_PEX2_CORE_10		56U
-#define TEGRA234_RESET_PEX2_CORE_10_APB		57U
-#define TEGRA234_RESET_PEX2_COMMON_APB		58U
-#define TEGRA234_RESET_NVENC			59U
-#define TEGRA234_RESET_MGBE2_MACSEC_SECURE	60U
-#define TEGRA234_RESET_NVJPG			61U
-#define TEGRA234_RESET_LA			64U
-#define TEGRA234_RESET_HWPM			65U
-#define TEGRA234_RESET_PVA0_ALL			66U
-#define TEGRA234_RESET_CEC			67U
-#define TEGRA234_RESET_PWM1			68U
-#define TEGRA234_RESET_PWM2			69U
-#define TEGRA234_RESET_PWM3			70U
-#define TEGRA234_RESET_PWM4			71U
-#define TEGRA234_RESET_PWM5			72U
-#define TEGRA234_RESET_PWM6			73U
-#define TEGRA234_RESET_PWM7			74U
-#define TEGRA234_RESET_PWM8			75U
-#define TEGRA234_RESET_QSPI0			76U
-#define TEGRA234_RESET_QSPI1			77U
-#define TEGRA234_RESET_I2S7			78U
-#define TEGRA234_RESET_I2S8			79U
-#define TEGRA234_RESET_SCE_ALL			80U
-#define TEGRA234_RESET_RCE_ALL			81U
-#define TEGRA234_RESET_SDMMC1			82U
-#define TEGRA234_RESET_RSVD_83			83U
-#define TEGRA234_RESET_RSVD_84			84U
-#define TEGRA234_RESET_SDMMC4			85U
-#define TEGRA234_RESET_MGBE3_PCS		87U
-#define TEGRA234_RESET_MGBE3_MAC		88U
-#define TEGRA234_RESET_MGBE3_MACSEC		89U
-#define TEGRA234_RESET_MGBE3_MACSEC_SECURE	90U
-#define TEGRA234_RESET_SPI1			91U
-#define TEGRA234_RESET_SPI2			92U
-#define TEGRA234_RESET_SPI3			93U
-#define TEGRA234_RESET_SPI4			94U
-#define TEGRA234_RESET_TACH0			95U
-#define TEGRA234_RESET_TACH1			96U
-#define TEGRA234_RESET_SPI5			97U
-#define TEGRA234_RESET_TSEC			98U
-#define TEGRA234_RESET_UARTI			99U
-#define TEGRA234_RESET_UARTA			100U
-#define TEGRA234_RESET_UARTB			101U
-#define TEGRA234_RESET_UARTC			102U
-#define TEGRA234_RESET_UARTD			103U
-#define TEGRA234_RESET_UARTE			104U
-#define TEGRA234_RESET_UARTF			105U
-#define TEGRA234_RESET_UARTJ			106U
-#define TEGRA234_RESET_UARTH			107U
-#define TEGRA234_RESET_UFSHC			108U
-#define TEGRA234_RESET_UFSHC_AXI_M		109U
-#define TEGRA234_RESET_UFSHC_LP_SEQ		110U
-#define TEGRA234_RESET_RSVD_111			111U
-#define TEGRA234_RESET_VI			112U
-#define TEGRA234_RESET_VIC			113U
-#define TEGRA234_RESET_XUSB_PADCTL		114U
-#define TEGRA234_RESET_VI2			115U
-#define TEGRA234_RESET_PEX0_CORE_0		116U
-#define TEGRA234_RESET_PEX0_CORE_1		117U
-#define TEGRA234_RESET_PEX0_CORE_2		118U
-#define TEGRA234_RESET_PEX0_CORE_3		119U
-#define TEGRA234_RESET_PEX0_CORE_4		120U
-#define TEGRA234_RESET_PEX0_CORE_0_APB		121U
-#define TEGRA234_RESET_PEX0_CORE_1_APB		122U
-#define TEGRA234_RESET_PEX0_CORE_2_APB		123U
-#define TEGRA234_RESET_PEX0_CORE_3_APB		124U
-#define TEGRA234_RESET_PEX0_CORE_4_APB		125U
-#define TEGRA234_RESET_PEX0_COMMON_APB		126U
-#define TEGRA234_RESET_RSVD_127			127U
-#define TEGRA234_RESET_NVHS_UPHY_PLL1		128U
-#define TEGRA234_RESET_PEX1_CORE_5		129U
-#define TEGRA234_RESET_PEX1_CORE_5_APB		130U
-#define TEGRA234_RESET_GBE_UPHY			131U
-#define TEGRA234_RESET_GBE_UPHY_PM		132U
-#define TEGRA234_RESET_NVHS_UPHY		133U
-#define TEGRA234_RESET_NVHS_UPHY_PLL0		134U
-#define TEGRA234_RESET_NVHS_UPHY_L0		135U
-#define TEGRA234_RESET_NVHS_UPHY_L1		136U
-#define TEGRA234_RESET_NVHS_UPHY_L2		137U
-#define TEGRA234_RESET_NVHS_UPHY_L3		138U
-#define TEGRA234_RESET_NVHS_UPHY_L4		139U
-#define TEGRA234_RESET_NVHS_UPHY_L5		140U
-#define TEGRA234_RESET_NVHS_UPHY_L6		141U
-#define TEGRA234_RESET_NVHS_UPHY_L7		142U
-#define TEGRA234_RESET_NVHS_UPHY_PM		143U
-#define TEGRA234_RESET_DMIC5			144U
-#define TEGRA234_RESET_APE			145U
-#define TEGRA234_RESET_PEX_USB_UPHY		146U
-#define TEGRA234_RESET_PEX_USB_UPHY_L0		147U
-#define TEGRA234_RESET_PEX_USB_UPHY_L1		148U
-#define TEGRA234_RESET_PEX_USB_UPHY_L2		149U
-#define TEGRA234_RESET_PEX_USB_UPHY_L3		150U
-#define TEGRA234_RESET_PEX_USB_UPHY_L4		151U
-#define TEGRA234_RESET_PEX_USB_UPHY_L5		152U
-#define TEGRA234_RESET_PEX_USB_UPHY_L6		153U
-#define TEGRA234_RESET_PEX_USB_UPHY_L7		154U
-#define TEGRA234_RESET_PEX_USB_UPHY_PLL0	159U
-#define TEGRA234_RESET_PEX_USB_UPHY_PLL1	160U
-#define TEGRA234_RESET_PEX_USB_UPHY_PLL2	161U
-#define TEGRA234_RESET_PEX_USB_UPHY_PLL3	162U
-#define TEGRA234_RESET_GBE_UPHY_L0		163U
-#define TEGRA234_RESET_GBE_UPHY_L1		164U
-#define TEGRA234_RESET_GBE_UPHY_L2		165U
-#define TEGRA234_RESET_GBE_UPHY_L3		166U
-#define TEGRA234_RESET_GBE_UPHY_L4		167U
-#define TEGRA234_RESET_GBE_UPHY_L5		168U
-#define TEGRA234_RESET_GBE_UPHY_L6		169U
-#define TEGRA234_RESET_GBE_UPHY_L7		170U
-#define TEGRA234_RESET_GBE_UPHY_PLL0		171U
-#define TEGRA234_RESET_GBE_UPHY_PLL1		172U
-#define TEGRA234_RESET_GBE_UPHY_PLL2		173U
-
-/** @} */
-
-#endif

include/nvidia-oot/dt-bindings/sound/tegra-asoc-dais.h

@@ -1,346 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2019-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
-
-#ifndef __DT_TEGRA_ASOC_DAIS_H
-#define __DT_TEGRA_ASOC_DAIS_H
-
-/*
- * DAI links can have one of these value
- * PCM_LINK	: optional, if nothing is specified link is treated as PCM link
- * COMPR_LINK	: required, if link is used with compress device
- * C2C_LINK	: required, for any other back end codec-to-codec links
- */
-#define PCM_LINK	0
-#define COMPR_LINK	1
-#define C2C_LINK	2
-
-/*
- * Following DAI indices are derived from respective module drivers.
- * Thus below values have to be in sync with the DAI arrays defined
- * in the drivers.
- */
-
-#define XBAR_ADMAIF1			0
-#define XBAR_ADMAIF2			1
-#define XBAR_ADMAIF3			2
-#define XBAR_ADMAIF4			3
-#define XBAR_ADMAIF5			4
-#define XBAR_ADMAIF6			5
-#define XBAR_ADMAIF7			6
-#define XBAR_ADMAIF8			7
-#define XBAR_ADMAIF9			8
-#define XBAR_ADMAIF10			9
-#define XBAR_ADMAIF11			10
-#define XBAR_ADMAIF12			11
-#define XBAR_ADMAIF13			12
-#define XBAR_ADMAIF14			13
-#define XBAR_ADMAIF15			14
-#define XBAR_ADMAIF16			15
-#define XBAR_ADMAIF17			16
-#define XBAR_ADMAIF18			17
-#define XBAR_ADMAIF19			18
-#define XBAR_ADMAIF20			19
-#define XBAR_I2S1			20
-#define XBAR_I2S2			21
-#define XBAR_I2S3			22
-#define XBAR_I2S4			23
-#define XBAR_I2S5			24
-#define XBAR_I2S6			25
-#define XBAR_DMIC1			26
-#define XBAR_DMIC2			27
-#define XBAR_DMIC3			28
-#define XBAR_DMIC4			29
-#define XBAR_DSPK1			30
-#define XBAR_DSPK2			31
-#define XBAR_SFC1_RX			32
-
-/*
- * TODO As per downstream kernel code there will be routing issue
- * if DAI names are updated for SFC, MVC and OPE input and
- * output. Due to that using single DAI with same name as downstream
- * kernel for input and output and added output DAIs just to keep
- * similar to upstream kernel, so that it will be easy to upstream
- * later.
- *
- * Once the routing changes are done for above mentioned modules,
- * use the commented output dai index and define output dai
- * links in tegra186-audio-graph.dtsi
- */
-#if 0
-#define XBAR_SFC1_TX			33
-#define XBAR_SFC2_TX			35
-#define XBAR_SFC3_TX			37
-#define XBAR_SFC4_TX			39
-#define XBAR_MVC1_TX			41
-#define XBAR_MVC2_TX			43
-#define XBAR_OPE1_TX			113
-#else
-#define XBAR_SFC1_TX			XBAR_SFC1_RX
-#define XBAR_SFC2_TX			XBAR_SFC2_RX
-#define XBAR_SFC3_TX			XBAR_SFC3_RX
-#define XBAR_SFC4_TX			XBAR_SFC4_RX
-#define XBAR_MVC1_TX			XBAR_MVC1_RX
-#define XBAR_MVC2_TX			XBAR_MVC2_RX
-#define XBAR_OPE1_TX			XBAR_OPE1_RX
-#endif
-
-#define XBAR_SFC2_RX			34
-#define XBAR_SFC3_RX			36
-#define XBAR_SFC4_RX			38
-#define XBAR_MVC1_RX			40
-#define XBAR_MVC2_RX			42
-#define XBAR_AMX1_IN1			44
-#define XBAR_AMX1_IN2			45
-#define XBAR_AMX1_IN3			46
-#define XBAR_AMX1_IN4			47
-#define XBAR_AMX1_OUT			48
-#define XBAR_AMX2_IN1			49
-#define XBAR_AMX2_IN2			50
-#define XBAR_AMX2_IN3			51
-#define XBAR_AMX2_IN4			52
-#define XBAR_AMX2_OUT			53
-#define XBAR_AMX3_IN1			54
-#define XBAR_AMX3_IN2			55
-#define XBAR_AMX3_IN3			56
-#define XBAR_AMX3_IN4			57
-#define XBAR_AMX3_OUT			58
-#define XBAR_AMX4_IN1			59
-#define XBAR_AMX4_IN2			60
-#define XBAR_AMX4_IN3			61
-#define XBAR_AMX4_IN4			62
-#define XBAR_AMX4_OUT			63
-#define XBAR_ADX1_IN			64
-#define XBAR_ADX1_OUT1			65
-#define XBAR_ADX1_OUT2			66
-#define XBAR_ADX1_OUT3			67
-#define XBAR_ADX1_OUT4			68
-#define XBAR_ADX2_IN			69
-#define XBAR_ADX2_OUT1			70
-#define XBAR_ADX2_OUT2			71
-#define XBAR_ADX2_OUT3			72
-#define XBAR_ADX2_OUT4			73
-#define XBAR_ADX3_IN			74
-#define XBAR_ADX3_OUT1			75
-#define XBAR_ADX3_OUT2			76
-#define XBAR_ADX3_OUT3			77
-#define XBAR_ADX3_OUT4			78
-#define XBAR_ADX4_IN			79
-#define XBAR_ADX4_OUT1			80
-#define XBAR_ADX4_OUT2			81
-#define XBAR_ADX4_OUT3			82
-#define XBAR_ADX4_OUT4			83
-#define XBAR_MIXER_IN1			84
-#define XBAR_MIXER_IN2			85
-#define XBAR_MIXER_IN3			86
-#define XBAR_MIXER_IN4			87
-#define XBAR_MIXER_IN5			88
-#define XBAR_MIXER_IN6			89
-#define XBAR_MIXER_IN7			90
-#define XBAR_MIXER_IN8			91
-#define XBAR_MIXER_IN9			92
-#define XBAR_MIXER_IN10			93
-#define XBAR_MIXER_OUT1			94
-#define XBAR_MIXER_OUT2			95
-#define XBAR_MIXER_OUT3			96
-#define XBAR_MIXER_OUT4			97
-#define XBAR_MIXER_OUT5			98
-#define XBAR_ASRC_IN1			99
-#define XBAR_ASRC_OUT1			100
-#define XBAR_ASRC_IN2			101
-#define XBAR_ASRC_OUT2			102
-#define XBAR_ASRC_IN3			103
-#define XBAR_ASRC_OUT3			104
-#define XBAR_ASRC_IN4			105
-#define XBAR_ASRC_OUT4			106
-#define XBAR_ASRC_IN5			107
-#define XBAR_ASRC_OUT5			108
-#define XBAR_ASRC_IN6			109
-#define XBAR_ASRC_OUT6			110
-#define XBAR_ASRC_IN7			111
-#define XBAR_OPE1_RX			112
-#define XBAR_AFC1			114
-#define XBAR_AFC2			115
-#define XBAR_AFC3			116
-#define XBAR_AFC4			117
-#define XBAR_AFC5			118
-#define XBAR_AFC6			119
-#define XBAR_SPKPROT			120
-#define XBAR_IQC1_1			121
-#define XBAR_IQC1_2			122
-#define XBAR_IQC2_1			123
-#define XBAR_IQC2_2			124
-#define XBAR_ARAD			125
-
-/* ADMAIF DAIs */
-#define ADMAIF1				0
-#define ADMAIF2				1
-#define ADMAIF3				2
-#define ADMAIF4				3
-#define ADMAIF5				4
-#define ADMAIF6				5
-#define ADMAIF7				6
-#define ADMAIF8				7
-#define ADMAIF9				8
-#define ADMAIF10			9
-#define ADMAIF11			10
-#define ADMAIF12			11
-#define ADMAIF13			12
-#define ADMAIF14			13
-#define ADMAIF15			14
-#define ADMAIF16			15
-#define ADMAIF17			16
-#define ADMAIF18			17
-#define ADMAIF19			18
-#define ADMAIF20			19
-
-/*
- * ADMAIF_FIFO: DAIs used for DAI links between ADMAIF and ADSP.
- * Offset depends on the number of ADMAIF channels for a chip.
- * The DAI indices for these are derived from below offsets.
- */
-#define TEGRA186_ADMAIF_FIFO_OFFSET	20
-
-/*
- * ADMAIF_CIF: DAIs used for codec-to-codec links between ADMAIF and XBAR.
- * Offset depends on the number of ADMAIF channels for a chip.
- * The DAI indices for these are derived from below offsets.
- */
-#define TEGRA186_ADMAIF_CIF_OFFSET	40
-
-/* I2S */
-#define I2S_CIF		0
-#define I2S_DAP		1
-#define I2S_DUMMY	2
-
-/* DMIC */
-#define DMIC_CIF	0
-#define DMIC_DAP	1
-#define DMIC_DUMMY	2
-
-/* DSPK */
-#define DSPK_CIF	0
-#define DSPK_DAP	1
-#define DSPK_DUMMY	2
-
-/* SFC */
-#define SFC_IN		0
-#define SFC_OUT		1
-
-/* MIXER */
-#define MIXER_IN1	0
-#define MIXER_IN2	1
-#define MIXER_IN3	2
-#define MIXER_IN4	3
-#define MIXER_IN5	4
-#define MIXER_IN6	5
-#define MIXER_IN7	6
-#define MIXER_IN8	7
-#define MIXER_IN9	8
-#define MIXER_IN10	9
-#define MIXER_OUT1	10
-#define MIXER_OUT2	11
-#define MIXER_OUT3	12
-#define MIXER_OUT4	13
-#define MIXER_OUT5	14
-
-/* AFC */
-#define AFC_IN		0
-#define AFC_OUT		1
-
-/* OPE */
-#define OPE_IN		0
-#define OPE_OUT		1
-
-/* MVC */
-#define MVC_IN		0
-#define MVC_OUT		1
-
-/* AMX */
-#define AMX_IN1		0
-#define AMX_IN2		1
-#define AMX_IN3		2
-#define AMX_IN4		3
-#define AMX_OUT		4
-
-/* ADX */
-#define ADX_OUT1	0
-#define ADX_OUT2	1
-#define ADX_OUT3	2
-#define ADX_OUT4	3
-#define ADX_IN		4
-
-/* ASRC */
-#define ASRC_IN1	0
-#define ASRC_IN2	1
-#define ASRC_IN3	2
-#define ASRC_IN4	3
-#define ASRC_IN5	4
-#define ASRC_IN6	5
-#define ASRC_IN7	6
-#define ASRC_OUT1	7
-#define ASRC_OUT2	8
-#define ASRC_OUT3	9
-#define ASRC_OUT4	10
-#define ASRC_OUT5	11
-#define ASRC_OUT6	12
-
-/* ARAD */
-#define ARAD		0
-
-/* ADSP */
-#define ADSP_FE1	0
-#define ADSP_FE2	1
-#define ADSP_FE3	2
-#define ADSP_FE4	3
-#define ADSP_FE5	4
-#define ADSP_FE6	5
-#define ADSP_FE7	6
-#define ADSP_FE8	7
-#define ADSP_FE9	8
-#define ADSP_FE10	9
-#define ADSP_FE11	10
-#define ADSP_FE12	11
-#define ADSP_FE13	12
-#define ADSP_FE14	13
-#define ADSP_FE15	14
-#define ADSP_EAVB_CODEC	15
-#define ADSP_ADMAIF1	16
-#define ADSP_ADMAIF2	17
-#define ADSP_ADMAIF3	18
-#define ADSP_ADMAIF4	19
-#define ADSP_ADMAIF5	20
-#define ADSP_ADMAIF6	21
-#define ADSP_ADMAIF7	22
-#define ADSP_ADMAIF8	23
-#define ADSP_ADMAIF9	24
-#define ADSP_ADMAIF10	25
-#define ADSP_ADMAIF11	26
-#define ADSP_ADMAIF12	27
-#define ADSP_ADMAIF13	28
-#define ADSP_ADMAIF14	29
-#define ADSP_ADMAIF15	30
-#define ADSP_ADMAIF16	31
-#define ADSP_ADMAIF17	32
-#define ADSP_ADMAIF18	33
-#define ADSP_ADMAIF19	34
-#define ADSP_ADMAIF20	35
-#define ADSP_PCM1	36
-#define ADSP_PCM2	37
-#define ADSP_PCM3	38
-#define ADSP_PCM4	39
-#define ADSP_PCM5	40
-#define ADSP_PCM6	41
-#define ADSP_PCM7	42
-#define ADSP_PCM8	43
-#define ADSP_PCM9	44
-#define ADSP_PCM10	45
-#define ADSP_PCM11	46
-#define ADSP_PCM12	47
-#define ADSP_PCM13	48
-#define ADSP_PCM14	49
-#define ADSP_PCM15	50
-#define ADSP_COMPR1	51
-#define ADSP_COMPR2	52
-#define ADSP_EAVB	53
-
-#endif

include/nvidia-oot/dt-bindings/strap/tegra234-strp.h

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2021-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+
+#ifndef BPMP_ABI_MACH_T234_STRAP_H
+#define BPMP_ABI_MACH_T234_STRAP_H
+
+/**
+ * @file
+ * @defgroup bpmp_reset_ids Reset ID's
+ * @brief Identifiers for Resets controllable by firmware
+ * @{
+ */
+
+#define TEGRA234_STRAP_NV_FUSE_CTRL_OPT_GPC		1U
+#define TEGRA234_STRAP_NV_FUSE_CTRL_OPT_FBP		2U
+#define TEGRA234_STRAP_NV_FUSE_CTRL_OPT_TPC_GPC0	3U
+#define TEGRA234_STRAP_NV_FUSE_CTRL_OPT_TPC_GPC1	4U
+
+/** @} */
+
+#endif

include/nvidia-oot/dt-bindings/thermal/tegra234-bpmp-thermal-oot.h

@@ -1,19 +0,0 @@
-/*
- * This header provides constants for binding nvidia,tegra234-bpmp-thermal.
- */
-
-#ifndef _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H
-#define _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H
-
-#define TEGRA234_THERMAL_ZONE_CPU	0
-#define TEGRA234_THERMAL_ZONE_GPU	1
-#define TEGRA234_THERMAL_ZONE_CV0	2
-#define TEGRA234_THERMAL_ZONE_CV1	3
-#define TEGRA234_THERMAL_ZONE_CV2	4
-#define TEGRA234_THERMAL_ZONE_SOC0	5
-#define TEGRA234_THERMAL_ZONE_SOC1	6
-#define TEGRA234_THERMAL_ZONE_SOC2	7
-#define TEGRA234_THERMAL_ZONE_TJ_MAX	8
-#define TEGRA234_THERMAL_ZONE_COUNT	9
-
-#endif

include/platforms/dt-bindings/tegra234-android-bootargs.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-FileCopyrightText: Copyright (c) 2024-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved. */
+
+// Definitions for tegra234 android bootargs
+
+// Make sure ANDROID_BOOTARGS and ANDROID_KDUMP_BOOTARGS are consistent except the later has "crashkernel=512M enforcing=0 androidboot.selinux=permissive" appended
+#define ANDROID_BOOTARGS       "bootconfig console=ttyTCU0,115200 rootfstype=ext4 mminit_loglevel=4 loop.max_part=7 firmware_class.path=/vendor/firmware"
+
+#define ANDROID_KDUMP_BOOTARGS "bootconfig console=ttyTCU0,115200 rootfstype=ext4 mminit_loglevel=4 isabled loop.max_part=7 firmware_class.path=/vendor/firmware crashkernel=512M enforcing=0 androidboot.selinux=permissive"
+
+#define ANDROID_BOOTCONFIG "androidboot.boot_devices=bus@0/3460000.mmc\nandroidboot.hypervisor=disabled\nandroidboot.xudc=3550000.usb\nandroidboot.hardware=t234ref\n"
+
+// Make sure ANDROID_FIRESPRAY_BOOTARGS and ANDROID_FIRESPRAY_KDUMP_BOOTARGS are consistent except the later has "crashkernel=512M" appended
+#define ANDROID_FIRESPRAY_BOOTARGS       "bootconfig console=ttyTCU0,115200 rootfstype=ext4 mminit_loglevel=4 enforcing=0 loop.max_part=7 firmware_class.path=/vendor/firmware"
+
+#define ANDROID_FIRESPRAY_KDUMP_BOOTARGS "bootconfig console=ttyTCU0,115200 rootfstype=ext4 mminit_loglevel=4 enforcing=0 loop.max_part=7 firmware_class.path=/vendor/firmware crashkernel=512M"
+
+#define ANDROID_FIRESPRAY_BOOTCONFIG "androidboot.boot_devices=bus@0/3460000.mmc\nandroidboot.hypervisor=disabled\nandroidboot.xudc=3550000.usb\nandroidboot.hardware=t234ref\n"

include/platforms/dt-bindings/tegra234-p3737-0000+p3701-0000.h

@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Definitions for Jetson tegra234-p3737-0000-p3701-0000 board.
+ */
+
+#include <dt-bindings/gpio/tegra234-gpio.h>
+
+#define JETSON_COMPATIBLE	"nvidia,p3737-0000+p3701-0000", "nvidia,p3737-0000+p3701-0004", "nvidia,p3737-0000+p3701-0005", "nvidia,p3737-0000+p3701-0008"
+
+/* SoC function name for clock signal on 40-pin header pin 7 */
+#define HDR40_CLK	"extperiph4"
+/* SoC function name for I2S interface on 40-pin header pins 12, 35, 38 and 40 */
+#define HDR40_I2S	"i2s2"
+/* SoC function name for SPI interface on 40-pin header pins 19, 21, 23, 24 and 26 */
+#define HDR40_SPI	"spi1"
+/* SoC function name for UART interface on 40-pin header pins 8, 10, 11 and 36 */
+#define HDR40_UART	"uarta"
+
+/* SoC pin name definitions for 40-pin header */
+#define HDR40_PIN7	"soc_gpio33_pq6"
+#define HDR40_PIN11	"uart1_rts_pr4"
+#define HDR40_PIN12	"soc_gpio41_ph7"
+#define HDR40_PIN13	"soc_gpio37_pr0"
+#define HDR40_PIN15	"soc_gpio39_pn1"
+#define HDR40_PIN16	"can1_stb_pbb0"
+#define HDR40_PIN18	"soc_gpio21_ph0"
+#define HDR40_PIN19	"spi1_mosi_pz5"
+#define HDR40_PIN21	"spi1_miso_pz4"
+#define HDR40_PIN22	"soc_gpio23_pp4"
+#define HDR40_PIN23	"spi1_sck_pz3"
+#define HDR40_PIN24	"spi1_cs0_pz6"
+#define HDR40_PIN26	"spi1_cs1_pz7"
+#define HDR40_PIN29	"can0_din_paa1"
+#define HDR40_PIN31	"can0_dout_paa0"
+#define HDR40_PIN32	"can1_en_pbb1"
+#define HDR40_PIN33	"can1_dout_paa2"
+#define HDR40_PIN35	"soc_gpio44_pi2"
+#define HDR40_PIN36	"uart1_cts_pr5"
+#define HDR40_PIN37	"can1_din_paa3"
+#define HDR40_PIN38	"soc_gpio43_pi1"
+#define HDR40_PIN40	"soc_gpio42_pi0"
+
+/* SoC GPIO definitions for 40-pin header */
+#define HDR40_PIN7_GPIO		TEGRA_MAIN_GPIO(Q, 6)
+#define HDR40_PIN11_GPIO	TEGRA_MAIN_GPIO(R, 4)
+#define HDR40_PIN12_GPIO	TEGRA_MAIN_GPIO(H, 7)
+#define HDR40_PIN13_GPIO	TEGRA_MAIN_GPIO(R, 0)
+#define HDR40_PIN15_GPIO	TEGRA_MAIN_GPIO(N, 1)
+#define HDR40_PIN16_GPIO	TEGRA_AON_GPIO(BB, 0)
+#define HDR40_PIN18_GPIO	TEGRA_MAIN_GPIO(H, 0)
+#define HDR40_PIN19_GPIO	TEGRA_MAIN_GPIO(Z, 5)
+#define HDR40_PIN21_GPIO	TEGRA_MAIN_GPIO(Z, 4)
+#define HDR40_PIN22_GPIO	TEGRA_MAIN_GPIO(P, 4)
+#define HDR40_PIN23_GPIO	TEGRA_MAIN_GPIO(Z, 3)
+#define HDR40_PIN24_GPIO	TEGRA_MAIN_GPIO(Z, 6)
+#define HDR40_PIN26_GPIO	TEGRA_MAIN_GPIO(Z, 7)
+#define HDR40_PIN29_GPIO	TEGRA_AON_GPIO(AA, 1)
+#define HDR40_PIN31_GPIO	TEGRA_AON_GPIO(AA, 0)
+#define HDR40_PIN32_GPIO	TEGRA_AON_GPIO(BB, 1)
+#define HDR40_PIN33_GPIO	TEGRA_AON_GPIO(AA, 2)
+#define HDR40_PIN35_GPIO	TEGRA_MAIN_GPIO(I, 2)
+#define HDR40_PIN36_GPIO	TEGRA_MAIN_GPIO(R, 5)
+#define HDR40_PIN37_GPIO	TEGRA_AON_GPIO(AA, 3)
+#define HDR40_PIN38_GPIO	TEGRA_MAIN_GPIO(I, 1)
+#define HDR40_PIN40_GPIO	TEGRA_MAIN_GPIO(I, 0)

include/platforms/dt-bindings/tegra234-p3740-0002-p3701-0008.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Definitions for Jetson tegra234-p3740-0002-p3701-0008 board.
+ */
+
+#include <dt-bindings/gpio/tegra234-gpio.h>
+
+#define JETSON_COMPATIBLE	"nvidia,p3740-0002+p3701-0008"

include/platforms/dt-bindings/tegra234-p3767-0000-common.h

@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+ *
+ * Definitions for Jetson tegra234-p3767-0000 board.
+ */
+
+#include <dt-bindings/gpio/tegra234-gpio.h>
+
+#define JETSON_COMPATIBLE_P3768		"nvidia,p3768-0000+p3767-0000", \
+                                        "nvidia,p3768-0000+p3767-0001", \
+                                        "nvidia,p3768-0000+p3767-0003", \
+                                        "nvidia,p3768-0000+p3767-0004", \
+                                        "nvidia,p3768-0000+p3767-0005", \
+                                        "nvidia,p3768-0000+p3767-0000-super", \
+                                        "nvidia,p3768-0000+p3767-0001-super", \
+                                        "nvidia,p3768-0000+p3767-0003-super", \
+                                        "nvidia,p3768-0000+p3767-0004-super", \
+                                        "nvidia,p3768-0000+p3767-0005-super"
+
+#define JETSON_COMPATIBLE_P3509		"nvidia,p3509-0000+p3767-0000", \
+                                        "nvidia,p3509-0000+p3767-0001", \
+                                        "nvidia,p3509-0000+p3767-0003", \
+                                        "nvidia,p3509-0000+p3767-0004", \
+                                        "nvidia,p3509-0000+p3767-0005"
+
+#define JETSON_COMPATIBLE		JETSON_COMPATIBLE_P3768, \
+                                        JETSON_COMPATIBLE_P3509
+
+/* SoC function name for clock signal on 40-pin header pin 7 */
+#define HDR40_CLK	"aud"
+/* SoC function name for I2S interface on 40-pin header pins 12, 35, 38 and 40 */
+#define HDR40_I2S	"i2s2"
+/* SoC function name for SPI interface on 40-pin header pins 19, 21, 23, 24 and 26 */
+#define HDR40_SPI	"spi1"
+/* SoC function name for UART interface on 40-pin header pins 8, 10, 11 and 36 */
+#define HDR40_UART	"uarta"
+
+/* SoC pin name definitions for 40-pin header */
+#define HDR40_PIN7	"soc_gpio59_pac6"
+#define HDR40_PIN11	"uart1_rts_pr4"
+#define HDR40_PIN12	"soc_gpio41_ph7"
+#define HDR40_PIN13	"spi3_sck_py0"
+#define HDR40_PIN15	"soc_gpio39_pn1"
+#define HDR40_PIN16	"spi3_cs1_py4"
+#define HDR40_PIN18	"spi3_cs0_py3"
+#define HDR40_PIN19	"spi1_mosi_pz5"
+#define HDR40_PIN21	"spi1_miso_pz4"
+#define HDR40_PIN22	"spi3_miso_py1"
+#define HDR40_PIN23	"spi1_sck_pz3"
+#define HDR40_PIN24	"spi1_cs0_pz6"
+#define HDR40_PIN26	"spi1_cs1_pz7"
+#define HDR40_PIN29	"soc_gpio32_pq5"
+#define HDR40_PIN31	"soc_gpio33_pq6"
+#define HDR40_PIN32	"soc_gpio19_pg6"
+#define HDR40_PIN33	"soc_gpio21_ph0"
+#define HDR40_PIN35	"soc_gpio44_pi2"
+#define HDR40_PIN36	"uart1_cts_pr5"
+#define HDR40_PIN37	"spi3_mosi_py2"
+#define HDR40_PIN38	"soc_gpio43_pi1"
+#define HDR40_PIN40	"soc_gpio42_pi0"
+
+/* SoC GPIO definitions for 40-pin header */
+#define HDR40_PIN7_GPIO		TEGRA_MAIN_GPIO(AC, 6)
+#define HDR40_PIN11_GPIO	TEGRA_MAIN_GPIO(R, 4)
+#define HDR40_PIN12_GPIO	TEGRA_MAIN_GPIO(H, 7)
+#define HDR40_PIN13_GPIO	TEGRA_MAIN_GPIO(Y, 0)
+#define HDR40_PIN15_GPIO	TEGRA_MAIN_GPIO(N, 1)
+#define HDR40_PIN16_GPIO	TEGRA_AON_GPIO(Y, 4)
+#define HDR40_PIN18_GPIO	TEGRA_MAIN_GPIO(Y, 3)
+#define HDR40_PIN19_GPIO	TEGRA_MAIN_GPIO(Z, 5)
+#define HDR40_PIN21_GPIO	TEGRA_MAIN_GPIO(Z, 4)
+#define HDR40_PIN22_GPIO	TEGRA_MAIN_GPIO(Y, 1)
+#define HDR40_PIN23_GPIO	TEGRA_MAIN_GPIO(Z, 3)
+#define HDR40_PIN24_GPIO	TEGRA_MAIN_GPIO(Z, 6)
+#define HDR40_PIN26_GPIO	TEGRA_MAIN_GPIO(Z, 7)
+#define HDR40_PIN29_GPIO	TEGRA_AON_GPIO(Q, 5)
+#define HDR40_PIN31_GPIO	TEGRA_AON_GPIO(Q, 6)
+#define HDR40_PIN32_GPIO	TEGRA_AON_GPIO(G, 6)
+#define HDR40_PIN33_GPIO	TEGRA_AON_GPIO(H, 0)
+#define HDR40_PIN35_GPIO	TEGRA_MAIN_GPIO(I, 2)
+#define HDR40_PIN36_GPIO	TEGRA_MAIN_GPIO(R, 5)
+#define HDR40_PIN37_GPIO	TEGRA_AON_GPIO(Y, 2)
+#define HDR40_PIN38_GPIO	TEGRA_MAIN_GPIO(I, 1)
+#define HDR40_PIN40_GPIO	TEGRA_MAIN_GPIO(I, 0)

nv-platform/Makefile

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# SPDX-FileCopyrightText: Copyright (c) 2023-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+DTC_FLAGS += -@
+
+old-dtb := $(dtb-y)
+old-dtbo := $(dtbo-y)
+dtb-y :=
+dtbo-y :=
+makefile-path := t23x/nv-public/nv-platform
+
+dtb-y += tegra234-p3737-0000+p3701-0000-nv.dtb
+dtb-y += tegra234-p3737-0000+p3701-0004-nv.dtb
+dtb-y += tegra234-p3737-0000+p3701-0005-nv.dtb
+dtb-y += tegra234-p3737-0000+p3701-0008-nv.dtb
+dtb-y += tegra234-p3740-0002+p3701-0008-nv.dtb
+dtb-y += tegra234-p3740-0002+p3701-0008-nv-safety.dtb
+dtb-y += tegra234-p3768-0000+p3767-0000-nv.dtb
+dtb-y += tegra234-p3768-0000+p3767-0000-nv-super.dtb
+dtb-y += tegra234-p3768-0000+p3767-0000-nv-taylor-high.dtb
+dtb-y += tegra234-p3768-0000+p3767-0000-nv-taylor-low.dtb
+dtb-y += tegra234-p3768-0000+p3767-0001-nv.dtb
+dtb-y += tegra234-p3768-0000+p3767-0001-nv-super.dtb
+dtb-y += tegra234-p3768-0000+p3767-0003-nv.dtb
+dtb-y += tegra234-p3768-0000+p3767-0003-nv-super.dtb
+dtb-y += tegra234-p3768-0000+p3767-0004-nv.dtb
+dtb-y += tegra234-p3768-0000+p3767-0004-nv-super.dtb
+dtb-y += tegra234-p3768-0000+p3767-0005-nv.dtb
+dtb-y += tegra234-p3768-0000+p3767-0005-nv-super.dtb
+dtb-y += tegra234-p3971-0000+p3701-0000-nv.dtb
+dtb-y += tegra234-p3971-0000+p3701-0008-nv.dtb
+dtb-y += tegra234-p3971-0000+p3701-0008-nv-safety.dtb
+
+ifneq ($(dtb-y),)
+dtb-y := $(addprefix $(makefile-path)/,$(dtb-y))
+endif
+ifneq ($(dtbo-y),)
+dtbo-y := $(addprefix $(makefile-path)/,$(dtbo-y))
+endif
+
+dtb-y += $(old-dtb)
+dtbo-y += $(old-dtbo)
+

nv-platform/tegra234-camera-p3785.dtsi

@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include <dt-bindings/clock/tegra234-clock.h>
+
+#define CAM0_PWDN	TEGRA234_AON_GPIO(AA, 4)
+
+/ {
+	gpio@c2f0000 {
+		camera-control-output-high {
+			gpio-hog;
+			output-high;
+			gpios = <CAM0_PWDN 0>;
+			label = "cam0-pwdn";
+		};
+	};
+
+	tegra-capture-vi {
+		nvidia,vi-mapping =
+			<0 0>,
+			<1 0>,
+			<2 0>,
+			<3 0>,
+			<4 1>,
+			<5 1>;
+		num-channels = <1>;
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				p3785_vi_in0: endpoint {
+					port-index = <0>;
+					bus-width = <8>;
+					remote-endpoint = <&p3785_csi_out0>;
+				};
+			};
+		};
+	};
+	bus@0 {
+		host1x@13e00000 {
+			nvcsi@15a00000 {
+				num-channels = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				channel@0 {
+					reg = <0>;
+					ports {
+						#address-cells = <1>;
+						#size-cells = <0>;
+						port@0 {
+							reg = <0>;
+							p3785_csi_in0: endpoint@0 {
+								port-index = <0>;
+								bus-width = <8>;
+								remote-endpoint = <&p3785_out0>;
+							};
+						};
+						port@1 {
+							reg = <1>;
+							p3785_csi_out0: endpoint@1 {
+								remote-endpoint = <&p3785_vi_in0>;
+							};
+						};
+					};
+				};
+			};
+		};
+
+		i2c@3180000 {
+			p3785@56 {
+				compatible = "nvidia,lt6911uxc";
+				/* I2C device address */
+				reg = <0x2b>;
+
+				/* V4L2 device node location */
+				devnode = "video0";
+
+				/* Physical dimensions of sensor */
+				physical_w = "3.674";
+				physical_h = "2.738";
+
+				sensor_model = "p3785";
+
+				/* Define any required hw resources needed by driver */
+				/* ie. clocks, io pins, power sources
+				avdd-reg = "vana";
+				iovdd-reg = "vif";
+				dvdd-reg = "vdig";*/
+
+				/* Defines number of frames to be dropped by driver internally after applying */
+				/* sensor crop settings. Some sensors send corrupt frames after applying */
+				/* crop co-ordinates */
+				/*post_crop_frame_drop = "0";*/
+
+				/* Define any required hw resources needed by driver */
+				/* ie. clocks, io pins, power sources */
+				clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
+					<&bpmp TEGRA234_CLK_EXTPERIPH1>;
+				clock-names = "extperiph1", "pllp_grtba";
+				mclk = "extperiph1";
+				reset-gpios = <&gpio_aon CAM0_PWDN GPIO_ACTIVE_HIGH>;
+
+				/**
+				* ==== Modes ====
+				* A modeX node is required to support v4l2 driver
+				* implementation with NVIDIA camera software stack
+				*
+				* == Signal properties ==
+				*
+				* phy_mode = "";
+				* PHY mode used by the MIPI lanes for this device
+				*
+				* tegra_sinterface = "";
+				* CSI Serial interface connected to tegra
+				* Incase of virtual HW devices, use virtual
+				* For SW emulated devices, use host
+				*
+				* pix_clk_hz = "";
+				* Sensor pixel clock used for calculations like exposure and framerate
+				*
+				* readout_orientation = "0";
+				* Based on camera module orientation.
+				* Only change readout_orientation if you specifically
+				* Program a different readout order for this mode
+				*
+				* == Image format Properties ==
+				*
+				* active_w = "";
+				* Pixel active region width
+				*
+				* active_h = "";
+				* Pixel active region height
+				*
+				* pixel_t = "";
+				* The sensor readout pixel pattern
+				*
+				* line_length = "";
+				* Pixel line length (width) for sensor mode.
+				*
+				* == Source Control Settings ==
+				*
+				* Gain factor used to convert fixed point integer to float
+				* Gain range [min_gain/gain_factor, max_gain/gain_factor]
+				* Gain step [step_gain/gain_factor is the smallest step that can be configured]
+				* Default gain [Default gain to be initialized for the control.
+						*     use min_gain_val as default for optimal results]
+				* Framerate factor used to convert fixed point integer to float
+				* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
+				* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
+				* Default Framerate [Default framerate to be initialized for the control.
+						*     use max_framerate to get required performance]
+				* Exposure factor used to convert fixed point integer to float
+				* For convenience use 1 sec = 1000000us as conversion factor
+				* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
+				* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
+				* Default Exposure Time [Default exposure to be initialized for the control.
+						*     Set default exposure based on the default_framerate for optimal exposure settings]
+				* For convenience use 1 sec = 1000000us as conversion factor
+				*
+				* gain_factor = ""; (integer factor used for floating to fixed point conversion)
+				* min_gain_val = ""; (ceil to integer)
+				* max_gain_val = ""; (ceil to integer)
+				* step_gain_val = ""; (ceil to integer)
+				* default_gain = ""; (ceil to integer)
+				* Gain limits for mode
+				*
+				* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
+				* min_exp_time = ""; (ceil to integer)
+				* max_exp_time = ""; (ceil to integer)
+				* step_exp_time = ""; (ceil to integer)
+				* default_exp_time = ""; (ceil to integer)
+				* Exposure Time limits for mode (sec)
+				*
+				* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
+				* min_framerate = ""; (ceil to integer)
+				* max_framerate = ""; (ceil to integer)
+				* step_framerate = ""; (ceil to integer)
+				* default_framerate = ""; (ceil to integer)
+				* Framerate limits for mode (fps)
+				*
+				* embedded_metadata_height = "";
+				* Sensor embedded metadata height in units of rows.
+				* If sensor does not support embedded metadata value should be 0.
+
+				* num_of_exposure = "";
+				* Digital overlap(Dol) frames
+				*
+				* num_of_ignored_lines = "";
+				* Used for cropping, eg. OB lines + Ignored area of effective pixel lines
+				*
+				* num_of_lines_offset_0 = "";
+				* Used for cropping, vertical blanking in front of short exposure data
+				* If more Dol frames are used, it can be extended, eg. num_of_lines_offset_1
+				*
+				* num_of_ignored_pixels = "";
+				* Used for cropping, The length of line info(pixels)
+				*
+				* num_of_left_margin_pixels = "";
+				* Used for cropping, the size of the left edge margin before
+				* the active pixel area (after ignored pixels)
+				*
+				* num_of_right_margin_pixels = "";
+				* Used for cropping, the size of the right edge margin after
+				* the active pixel area
+				*
+				*/
+				mode0 { // E2832_1920x1080_60Fps
+					mclk_khz = "24000";
+					num_lanes = "4";
+					tegra_sinterface = "serial_a";
+					phy_mode = "DPHY";
+					discontinuous_clk = "yes";
+					dpcm_enable = "false";
+					cil_settletime = "0";
+
+					active_w = "1920";
+					active_h = "1080";
+					mode_type = "rgb";
+					pixel_phase = "rgb888";
+					csi_pixel_bit_depth = "24";
+					readout_orientation = "0";
+					line_length = "1920";
+					inherent_gain = "1";
+					mclk_multiplier = "24";
+					pix_clk_hz = "250000000";
+
+					gain_factor = "16";
+					framerate_factor = "1000000";
+					exposure_factor = "1000000";
+					min_gain_val = "16"; /* 1.00x */
+					max_gain_val = "170"; /* 10.66x */
+					step_gain_val = "1";
+					default_gain = "16"; /* 1.00x */
+					min_hdr_ratio = "1";
+					max_hdr_ratio = "1";
+					min_framerate = "2000000"; /* 2.0 fps */
+					max_framerate = "60000000"; /* 60.0 fps */
+					step_framerate = "1";
+					default_framerate = "60000000"; /* 60.0 fps */
+					min_exp_time = "13"; /* us */
+					max_exp_time = "683709"; /* us */
+					step_exp_time = "1";
+					default_exp_time = "16667"; /* us  */
+				};
+				mode1 { // E2832_3840x2160
+					mclk_khz = "24000";
+					num_lanes = "8";
+					tegra_sinterface = "serial_a";
+					phy_mode = "DPHY";
+					discontinuous_clk = "yes";
+					dpcm_enable = "false";
+					cil_settletime = "0";
+
+					active_w = "3840";
+					active_h = "2160";
+					mode_type = "rgb";
+					pixel_phase = "rgb888";
+					csi_pixel_bit_depth = "24";
+					readout_orientation = "0";
+					line_length = "3840";
+					inherent_gain = "1";
+					mclk_multiplier = "24";
+					pix_clk_hz = "500000000";
+
+					gain_factor = "16";
+					framerate_factor = "1000000";
+					exposure_factor = "1000000";
+					min_gain_val = "16"; /* 1.00x */
+					max_gain_val = "170"; /* 10.66x */
+					step_gain_val = "1";
+					default_gain = "16"; /* 1.00x */
+					min_hdr_ratio = "1";
+					max_hdr_ratio = "1";
+					min_framerate = "2000000"; /* 2.0 fps */
+					max_framerate = "60000000"; /* 60.0 fps */
+					step_framerate = "1";
+					default_framerate = "60000000"; /* 60.0 fps */
+					min_exp_time = "13"; /* us */
+					max_exp_time = "683709"; /* us */
+					step_exp_time = "1";
+					default_exp_time = "16667"; /* us  */
+				};
+
+				mode2 { // E2832_1280x720_60Fps
+					mclk_khz = "24000";
+					num_lanes = "4";
+					tegra_sinterface = "serial_a";
+					phy_mode = "DPHY";
+					discontinuous_clk = "yes";
+					dpcm_enable = "false";
+					cil_settletime = "0";
+
+					active_w = "1280";
+					active_h = "720";
+					mode_type = "rgb";
+					pixel_phase = "rgb888";
+					csi_pixel_bit_depth = "24";
+					readout_orientation = "0";
+					line_length = "1280";
+					inherent_gain = "1";
+					mclk_multiplier = "24";
+					pix_clk_hz = "250000000";
+
+					gain_factor = "16";
+					framerate_factor = "1000000";
+					exposure_factor = "1000000";
+					min_gain_val = "16"; /* 1.00x */
+					max_gain_val = "170"; /* 10.66x */
+					step_gain_val = "1";
+					default_gain = "16"; /* 1.00x */
+					min_hdr_ratio = "1";
+					max_hdr_ratio = "1";
+					min_framerate = "2000000"; /* 2.0 fps */
+					max_framerate = "60000000"; /* 60.0 fps */
+					step_framerate = "1";
+					default_framerate = "60000000"; /* 60.0 fps */
+					min_exp_time = "13"; /* us */
+					max_exp_time = "683709"; /* us */
+					step_exp_time = "1";
+					default_exp_time = "16667"; /* us  */
+				};
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					port@0 {
+						reg = <0>;
+						p3785_out0: endpoint {
+							port-index = <0>;
+							bus-width = <8>;
+							remote-endpoint = <&p3785_csi_in0>;
+						};
+					};
+				};
+			};
+		};
+	};
+
+	tegra-camera-platform {
+		compatible = "nvidia, tegra-camera-platform";
+
+		/**
+		* The general guideline for naming badge_info contains 3 parts, and is as follows,
+		* The first part is the camera_board_id for the module; if the module is in a FFD
+		* platform, then use the platform name for this part.
+		* The second part contains the position of the module, ex. "rear" or "front".
+		* The third part contains the last 6 characters of a part number which is found
+		* in the module's specsheet from the vender.
+		*/
+		modules {
+			module0 {
+				badge = "p3785_ltx6911";
+				position = "bottom";
+				orientation = "1";
+				drivernode0 {
+					/* Declare PCL support driver (classically known as guid)  */
+					pcl_id = "v4l2_sensor";
+					/* Declare the device-tree hierarchy to driver instance */
+					sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/p3785@56";
+				};
+			};
+		};
+	};
+};

nv-platform/tegra234-dcb-p3737-0000-p3701-0000.dtsi

@@ -0,0 +1,534 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/ {
+	display@13800000 {
+		nvidia,dcb-image = [
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+	};
+};

nv-platform/tegra234-dcb-p3971-0000+p3701-0000.dtsi

@@ -0,0 +1,534 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+/ {
+	display@13800000 {
+		nvidia,dcb-image = [
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+			1f 1f 1f 1f 0f 46 40 00 0e 0e 0e 0e 29 29 29 29
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+			1c 1c 1c 1c 0f 46 40 00 0e 0e 0e 0e 26 26 26 26
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+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 09
+			00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 08
+			00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 06
+			00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
+			08 00 00 00 10 08 00 1e 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 14 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 10 00 00 00 00 03 00 01 00
+			50 00 00 00 00 00 00 0c 00 00 00 00 03 00 01 00
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+			40 00 00 00 00 00 00 08 00 00 00 00 03 00 01 00
+			40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
+			00 00 00 00 00 00 00 ];
+	};
+};

nv-platform/tegra234-p3701-0000-prod-overlay.dtsi

@@ -0,0 +1,327 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/ {
+	bus@0 {
+		aon@c000000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					board {
+						prod = <
+							0 0x00260004 0x0000003f 0x00000020>;            //SPI_COMMAND2_0
+					};
+				};
+			};
+		};
+
+		i2c@3160000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_fm {
+					nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+					nvidia,i2c-sclk-high-period = <0x02>;
+					nvidia,i2c-sclk-low-period = <0x02>;
+					nvidia,i2c-bus-free-time = <0x02>;
+					nvidia,i2c-stop-setup-time = <0x02>;
+					nvidia,i2c-start-hold-time = <0x02>;
+					nvidia,i2c-start-setup-time = <0x02>;
+					board {
+						prod = <
+							0 0x0000006c 0xffff0000 0x003c0000              //I2C_I2C_CLK_DIVISOR_REGISTER_0
+							0 0x00000094 0x0000ffff 0x00000202              //I2C_I2C_INTERFACE_TIMING_0_0
+							0 0x00000098 0xffffffff 0x02020202>;            //I2C_I2C_INTERFACE_TIMING_1_0
+					};
+				};
+				prod_c_fmplus {
+					nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+					nvidia,i2c-sclk-high-period = <0x02>;
+					nvidia,i2c-sclk-low-period = <0x02>;
+					nvidia,i2c-bus-free-time = <0x02>;
+					nvidia,i2c-stop-setup-time = <0x02>;
+					nvidia,i2c-start-hold-time = <0x02>;
+					nvidia,i2c-start-setup-time = <0x02>;
+					board {
+						prod = <
+							0 0x0000006c 0xffff0000 0x00160000              //I2C_I2C_CLK_DIVISOR_REGISTER_0
+							0 0x00000094 0x0000ffff 0x00000202              //I2C_I2C_INTERFACE_TIMING_0_0
+							0 0x00000098 0xffffffff 0x02020202>;            //I2C_I2C_INTERFACE_TIMING_1_0
+					};
+				};
+			};
+		};
+
+		i2c@3180000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_fmplus {
+					nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+					nvidia,i2c-sclk-high-period = <0x02>;
+					nvidia,i2c-sclk-low-period = <0x02>;
+					nvidia,i2c-bus-free-time = <0x02>;
+					nvidia,i2c-stop-setup-time = <0x02>;
+					nvidia,i2c-start-hold-time = <0x02>;
+					nvidia,i2c-start-setup-time = <0x02>;
+					board {
+						prod = <
+							0 0x0000006c 0xffff0000 0x00160000              //I2C_I2C_CLK_DIVISOR_REGISTER_0
+							0 0x00000094 0x0000ffff 0x00000202              //I2C_I2C_INTERFACE_TIMING_0_0
+							0 0x00000098 0xffffffff 0x02020202>;            //I2C_I2C_INTERFACE_TIMING_1_0
+					};
+				};
+				prod_c_sm {
+					nvidia,i2c-clk-divisor-fs-mode = <0x4f>;
+					nvidia,i2c-sclk-high-period = <0x07>;
+					nvidia,i2c-sclk-low-period = <0x08>;
+					nvidia,i2c-bus-free-time = <0x08>;
+					nvidia,i2c-stop-setup-time = <0x08>;
+					nvidia,i2c-start-hold-time = <0x08>;
+					nvidia,i2c-start-setup-time = <0x08>;
+					board {
+						prod = <
+							0 0x0000006c 0xffff0000 0x004f0000              //I2C_I2C_CLK_DIVISOR_REGISTER_0
+							0 0x00000094 0x0000ffff 0x00000708              //I2C_I2C_INTERFACE_TIMING_0_0
+							0 0x00000098 0xffffffff 0x08080808>;            //I2C_I2C_INTERFACE_TIMING_1_0
+					};
+				};
+			};
+		};
+
+		i2c@3190000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_fm {
+					nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+					nvidia,i2c-sclk-high-period = <0x02>;
+					nvidia,i2c-sclk-low-period = <0x02>;
+					nvidia,i2c-bus-free-time = <0x02>;
+					nvidia,i2c-stop-setup-time = <0x02>;
+					nvidia,i2c-start-hold-time = <0x02>;
+					nvidia,i2c-start-setup-time = <0x02>;
+					board {
+						prod = <
+							0 0x0000006c 0xffff0000 0x003c0000              //I2C_I2C_CLK_DIVISOR_REGISTER_0
+							0 0x00000094 0x0000ffff 0x00000202              //I2C_I2C_INTERFACE_TIMING_0_0
+							0 0x00000098 0xffffffff 0x02020202>;            //I2C_I2C_INTERFACE_TIMING_1_0
+					};
+				};
+			};
+		};
+
+		i2c@31c0000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_fm {
+					nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+					nvidia,i2c-sclk-high-period = <0x02>;
+					nvidia,i2c-sclk-low-period = <0x02>;
+					nvidia,i2c-bus-free-time = <0x02>;
+					nvidia,i2c-stop-setup-time = <0x02>;
+					nvidia,i2c-start-hold-time = <0x02>;
+					nvidia,i2c-start-setup-time = <0x02>;
+					board {
+						prod = <
+							0 0x0000006c 0xffff0000 0x003c0000              //I2C_I2C_CLK_DIVISOR_REGISTER_0
+							0 0x00000094 0x0000ffff 0x00000202              //I2C_I2C_INTERFACE_TIMING_0_0
+							0 0x00000098 0xffffffff 0x02020202>;            //I2C_I2C_INTERFACE_TIMING_1_0
+					};
+				};
+			};
+		};
+
+		i2c@31e0000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_fm {
+					nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+					nvidia,i2c-sclk-high-period = <0x02>;
+					nvidia,i2c-sclk-low-period = <0x02>;
+					nvidia,i2c-bus-free-time = <0x02>;
+					nvidia,i2c-stop-setup-time = <0x02>;
+					nvidia,i2c-start-hold-time = <0x02>;
+					nvidia,i2c-start-setup-time = <0x02>;
+					board {
+						prod = <
+							0 0x0000006c 0xffff0000 0x003c0000              //I2C_I2C_CLK_DIVISOR_REGISTER_0
+							0 0x00000094 0x0000ffff 0x00000202              //I2C_I2C_INTERFACE_TIMING_0_0
+							0 0x00000098 0xffffffff 0x02020202>;            //I2C_I2C_INTERFACE_TIMING_1_0
+					};
+				};
+			};
+		};
+
+		i2c@c240000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_fmplus {
+					nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+					nvidia,i2c-sclk-high-period = <0x02>;
+					nvidia,i2c-sclk-low-period = <0x02>;
+					nvidia,i2c-bus-free-time = <0x02>;
+					nvidia,i2c-stop-setup-time = <0x02>;
+					nvidia,i2c-start-hold-time = <0x02>;
+					nvidia,i2c-start-setup-time = <0x02>;
+					board {
+						prod = <
+							0 0x0000006c 0xffff0000 0x00160000              //I2C_I2C_CLK_DIVISOR_REGISTER_0
+							0 0x00000094 0x0000ffff 0x00000202              //I2C_I2C_INTERFACE_TIMING_0_0
+							0 0x00000098 0xffffffff 0x02020202>;            //I2C_I2C_INTERFACE_TIMING_1_0
+					};
+				};
+			};
+		};
+
+		i2c@c250000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_fmplus {
+					nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+					nvidia,i2c-sclk-high-period = <0x02>;
+					nvidia,i2c-sclk-low-period = <0x02>;
+					nvidia,i2c-bus-free-time = <0x02>;
+					nvidia,i2c-stop-setup-time = <0x02>;
+					nvidia,i2c-start-hold-time = <0x02>;
+					nvidia,i2c-start-setup-time = <0x02>;
+					board {
+						prod = <
+							0 0x0000006c 0xffff0000 0x00160000              //I2C_I2C_CLK_DIVISOR_REGISTER_0
+							0 0x00000094 0x0000ffff 0x00000202              //I2C_I2C_INTERFACE_TIMING_0_0
+							0 0x00000098 0xffffffff 0x02020202>;            //I2C_I2C_INTERFACE_TIMING_1_0
+					};
+				};
+			};
+		};
+
+		mttcan@c310000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_can_2m_1m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000000>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+				prod_c_can_5m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000600>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+				prod_c_can_8m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000400>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+			};
+		};
+
+		mttcan@c320000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_can_2m_1m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000000>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+				prod_c_can_5m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000600>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+				prod_c_can_8m {
+					board {
+						prod = <
+							0 0x00000048 0x00007f00 0x00000400>;            //M_TTCAN_CORE_TDCR_0
+					};
+				};
+			};
+		};
+
+		spi@3210000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					nvidia,spi-cmd2-rx-tap-delay = <0x30>;
+					board {
+						prod = <
+							0 0x00000004 0x0000003f 0x00000030>;            //SPI_COMMAND2_0
+					};
+				};
+			};
+		};
+
+		spi@3230000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					nvidia,spi-cmd2-rx-tap-delay = <0x20>;
+					board {
+						prod = <
+							0 0x00000004 0x0000003f 0x00000020>;            //SPI_COMMAND2_0
+					};
+				};
+			};
+		};
+
+		spi@3270000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					nvidia,qspi-rx-tap-delay = <0x10>;
+					nvidia,qspi-comp-pad-drv-dn-ovr = <0x0a>;
+					nvidia,qspi-comp-pad-drv-up-ovr = <0x0a>;
+					board {
+						prod = <
+							0 0x00000004 0x00007cff 0x00000010              //QSPI_COMMAND2_0
+							0 0x000001ec 0x01f1f000 0x00a0a000>;            //QSPI_QSPI_COMP_CONTROL_0
+					};
+				};
+			};
+		};
+
+		ufshci@2500000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					board {
+						prod = <
+							0x02470000 0x00002220 0xffffffff 0x001aadb5            //MPHY_RX_APB_VENDOR3B_0
+							0x02480000 0x00002220 0xffffffff 0x001aadb5>;            //MPHY_RX_APB_VENDOR3B_0
+					};
+				};
+			};
+		};
+
+		padctl@3520000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					nvidia,xusb-pad0-ls-rise-slew = <0x6>;
+					nvidia,xusb-pad0-ls-fall-slew = <0x6>;
+					nvidia,xusb-pad0-hs-txeq = <0x2>;
+					nvidia,xusb-pad1-ls-rise-slew = <0x6>;
+					nvidia,xusb-pad1-ls-fall-slew = <0x6>;
+					nvidia,xusb-pad1-hs-txeq = <0x2>;
+					nvidia,xusb-pad2-ls-rise-slew = <0x6>;
+					nvidia,xusb-pad2-ls-fall-slew = <0x6>;
+					nvidia,xusb-pad2-hs-txeq = <0x0>;
+					nvidia,xusb-pad3-ls-rise-slew = <0x6>;
+					nvidia,xusb-pad3-ls-fall-slew = <0x6>;
+					board {
+						prod = <
+							0 0x00000088 0x01fe0000 0x00cc0000              //XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0
+							0 0x00000094 0x0000000e 0x00000004              //XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0
+							0 0x000000c8 0x01fe0000 0x00cc0000              //XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0
+							0 0x000000d4 0x0000000e 0x00000004              //XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0
+							0 0x00000108 0x01fe0000 0x00cc0000              //XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0
+							0 0x00000114 0x0000000e 0x00000000              //XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0
+							0 0x00000148 0x01fe0000 0x00cc0000>;            //XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0
+					};
+				};
+			};
+		};
+	};
+};

nv-platform/tegra234-p3701-0000.dtsi

@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "tegra234-p3701-0000-prod-overlay.dtsi"
+#include "nv-soc/tegra234-soc-thermal.dtsi"
+#include "nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi"
+#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
+#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
+
+/ {
+	bus@0 {
+		spi@3270000 {
+			flash@0 {
+				spi-max-frequency = <51000000>;
+				spi-tx-bus-width = <1>;
+				spi-rx-bus-width = <1>;
+			};
+		};
+
+		nvrng@3ae0000 {
+			status = "okay";
+		};
+	};
+
+	bpmp {
+		i2c {
+			vrs@3c {
+				compatible = "nvidia,vrs-pseq";
+				reg = <0x3c>;
+				interrupt-parent = <&pmc>;
+				/* VRS Wake ID is 24 */
+				interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "okay";
+			};
+
+			tegra_tmp451: thermal-sensor@4c {
+				#thermal-sensor-cells = <1>;
+			};
+
+			vrs11_1@20 {
+				compatible = "nvidia,vrs11";
+				reg = <0x20>;
+				rail-name-loopA = "GPU";
+				rail-name-loopB = "CPU";
+			};
+
+			vrs11_2@22 {
+				compatible = "nvidia,vrs11";
+				reg = <0x22>;
+				rail-name-loopA = "SOC";
+				rail-name-loopB = "CV";
+			};
+		};
+	};
+
+	eeprom-manager {
+		bus@0 {
+			i2c-bus = <&gen1_i2c>;
+			eeprom@0 {
+				slave-address = <0x50>;
+				label = "cvm";
+			};
+		};
+	};
+
+	reserved-memory {
+		linux,cma { /* Needed for nvgpu comptags */
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x10000000>; /* 256MB */
+			alignment = <0x0 0x10000>;
+			linux,cma-default;
+			status = "okay";
+		};
+	};
+};

nv-platform/tegra234-p3701-0005.dtsi

@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "tegra234-p3701-0000.dtsi"
+
+/ {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma { /* Needed for nvgpu comptags */
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x20000000>; /* 512MB */
+			alignment = <0x0 0x10000>;
+			linux,cma-default;
+			status = "okay";
+		};
+	};
+};

nv-platform/tegra234-p3701-0008.dtsi

@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "tegra234-p3701-0000.dtsi"
+
+#define TEGRA234_INDUSTRIAL_THERMAL_SLOWDOWN_TEMP 112000
+#define TEGRA234_INDUSTRIAL_THERMAL_SHUTDOWN_TEMP 117500
+
+/ {
+	opp-table-cluster0 {
+		opp-1971200000 {
+			opp-hz = /bits/ 64 <1971200000>;
+			opp-peak-kBps = <3200000>;
+		};
+	};
+
+	opp-table-cluster1 {
+		opp-1971200000 {
+			opp-hz = /bits/ 64 <1971200000>;
+			opp-peak-kBps = <3200000>;
+		};
+	};
+
+	opp-table-cluster2 {
+		opp-1971200000 {
+			opp-hz = /bits/ 64 <1971200000>;
+			opp-peak-kBps = <3200000>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma { /* Needed for nvgpu comptags */
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x20000000>; /* 512MB */
+			alignment = <0x0 0x10000>;
+			linux,cma-default;
+			status = "okay";
+		};
+	};
+
+	thermal-zones {
+		cpu-thermal {
+			trips {
+				cpu-sw-slowdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SLOWDOWN_TEMP>;
+				};
+
+				cpu-sw-shutdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SHUTDOWN_TEMP>;
+				};
+			};
+		};
+
+		cv0-thermal {
+			trips {
+				cv0-sw-slowdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SLOWDOWN_TEMP>;
+				};
+
+				cv0-sw-shutdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SHUTDOWN_TEMP>;
+				};
+			};
+		};
+
+		cv1-thermal {
+			trips {
+				cv1-sw-slowdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SLOWDOWN_TEMP>;
+				};
+
+				cv1-sw-shutdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SHUTDOWN_TEMP>;
+				};
+			};
+		};
+
+		cv2-thermal {
+			trips {
+				cv2-sw-slowdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SLOWDOWN_TEMP>;
+				};
+
+				cv2-sw-shutdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SHUTDOWN_TEMP>;
+				};
+			};
+		};
+
+		gpu-thermal {
+			trips {
+				gpu-sw-slowdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SLOWDOWN_TEMP>;
+				};
+
+				gpu-sw-shutdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SHUTDOWN_TEMP>;
+				};
+			};
+		};
+
+		soc0-thermal {
+			trips {
+				soc0-sw-slowdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SLOWDOWN_TEMP>;
+				};
+
+				soc0-sw-shutdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SHUTDOWN_TEMP>;
+				};
+			};
+		};
+
+		soc1-thermal {
+			trips {
+				soc1-sw-slowdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SLOWDOWN_TEMP>;
+				};
+
+				soc1-sw-shutdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SHUTDOWN_TEMP>;
+				};
+			};
+		};
+
+		soc2-thermal {
+			trips {
+				soc2-sw-slowdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SLOWDOWN_TEMP>;
+				};
+
+				soc2-sw-shutdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SHUTDOWN_TEMP>;
+				};
+			};
+		};
+
+		tj-thermal {
+			trips {
+				tj-sw-shutdown {
+					temperature = <TEGRA234_INDUSTRIAL_THERMAL_SHUTDOWN_TEMP>;
+				};
+			};
+		};
+	};
+};

nv-platform/tegra234-p3737-0000+p3701-0000-nv.dts

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3737-0000+p3701-0000.dts"
+#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"
+#include "tegra234-p3701-0000.dtsi"

nv-platform/tegra234-p3737-0000+p3701-0004-nv.dts

@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3737-0000+p3701-0000.dts"
+#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"
+#include "tegra234-p3701-0000.dtsi"
+
+/ {
+	compatible = "nvidia,p3737-0000+p3701-0004", "nvidia,p3701-0004", "nvidia,tegra234";
+};

nv-platform/tegra234-p3737-0000+p3701-0005-nv.dts

@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3737-0000+p3701-0000.dts"
+#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"
+#include "tegra234-p3701-0005.dtsi"
+
+/ {
+	compatible = "nvidia,p3737-0000+p3701-0005", "nvidia,p3701-0005", "nvidia,tegra234";
+};

nv-platform/tegra234-p3737-0000+p3701-0008-nv.dts

@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3737-0000+p3701-0008.dts"
+#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"
+#include "tegra234-p3701-0008.dtsi"

nv-platform/tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi

@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "nv-soc/tegra234-overlay.dtsi"
+#include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
+#include "nv-soc/tegra234-soc-camera.dtsi"
+#include "tegra234-p3737-0000.dtsi"
+#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
+
+/ {
+	aliases {
+		ethernet0 = "/bus@0/ethernet@6800000";
+		serial2 = "/bus@0/serial@3110000";
+	};
+
+	cpus {
+		idle-states {
+			c7 {
+				status = "okay";
+			};
+		};
+	};
+
+	nvpmodel {
+		status = "okay";
+	};
+
+	scf-pmu {
+		status = "okay";
+	};
+
+	soctherm-oc-event {
+		status = "okay";
+	};
+
+	bus@0 {
+		smmu_test {
+			compatible = "nvidia,smmu_test";
+			iommus = <&smmu_niso0 TEGRA234_SID_SMMU_TEST>;
+			status = "okay";
+		};
+
+		pinmux@2430000 {
+			status = "okay";
+		};
+
+		aconnect@2900000 {
+			adsp@2993000 {
+				status = "okay";
+			};
+		};
+
+		serial@3110000 {
+			compatible = "nvidia,tegra194-hsuart";
+			reset-names = "serial";
+			status = "okay";
+		};
+
+		i2c@3180000 {
+			status = "okay";
+		};
+
+		i2c@3190000 {
+			status = "okay";
+		};
+
+		i2c@31b0000 {
+			nvidia,hw-instance-id = <0x5>;
+			status = "okay";
+		};
+
+		i2c@31c0000 {
+			status = "okay";
+		};
+
+		i2c@31e0000 {
+			status = "okay";
+		};
+
+		tachometer@39c0000 {
+			status = "okay";
+		};
+
+		hsp@3d00000 {
+			status = "okay";
+		};
+
+		ethernet@6800000 {
+			status = "okay";
+		};
+
+		aon@c000000 {
+			status = "okay";
+		};
+
+		hardware-timestamp@c1e0000 {
+			status = "okay";
+		};
+
+		i2c@c240000 {
+			status = "okay";
+		};
+
+		hdr40_i2c1: i2c@c250000 {
+			status = "okay";
+		};
+
+		rtc@c2a0000 {
+			status = "okay";
+		};
+
+		mttcan@c310000 {
+			status = "okay";
+		};
+
+		mttcan@c320000 {
+			status = "okay";
+		};
+
+		actmon@d230000 {
+			status = "okay";
+		};
+
+		hwpm@f100000 {
+			status = "okay";
+		};
+
+		mc-hwpm@2c10000 {
+			status = "okay";
+		};
+
+		host1x@13e00000 {
+			nvjpg@15380000 {
+				status = "okay";
+			};
+
+			nvdec@15480000 {
+				status = "okay";
+			};
+
+			nvenc@154c0000 {
+				status = "okay";
+			};
+
+			tsec@15500000 {
+				status = "okay";
+			};
+
+			nvjpg@15540000 {
+				status = "okay";
+			};
+
+			crypto@15820000 {
+				status = "okay";
+			};
+
+			crypto@15840000 {
+				status = "okay";
+			};
+
+			nvdla0@15880000 {
+				status = "okay";
+			};
+
+			nvdla1@158c0000 {
+				status = "okay";
+			};
+
+			ofa@15a50000 {
+				status = "okay";
+			};
+
+			pva0@16000000 {
+				status = "okay";
+
+				pva0_niso1_ctx0 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx1 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx2 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx3 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx4 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx5 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx6 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx7 {
+					status = "okay";
+				};
+			};
+		};
+
+		gpu@17000000 {
+			status = "okay";
+		};
+
+		pcie-ep@141a0000 {
+			nvidia,refclk-select-gpios = <&gpio
+							TEGRA234_MAIN_GPIO(Q, 4)
+							GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	tegra-hsp@b950000 {
+		status = "okay";
+	};
+
+	dce@d800000 {
+		status = "okay";
+	};
+
+	tegra_mce@e100000 {
+		status = "okay";
+	};
+
+	display@13800000 {
+		status = "okay";
+	};
+};

nv-platform/tegra234-p3737-0000.dtsi

@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/ {
+	bus@0 {
+		spi@3210000{ /* SPI1 in 40 pin conn */
+			status = "okay";
+			spi@0 { /* chip select 0 */
+				compatible = "tegra-spidev";
+				reg = <0x0>;
+				spi-max-frequency = <50000000>;
+			};
+			spi@1 { /* chips select 1 */
+				compatible = "tegra-spidev";
+				reg = <0x1>;
+				spi-max-frequency = <50000000>;
+			};
+		};
+
+		spi@3230000{ /* SPI3 in 40 pin conn */
+			status = "okay";
+			spi@0 { /* chip select 0 */
+				compatible = "tegra-spidev";
+				reg = <0x0>;
+				spi-max-frequency = <50000000>;
+			};
+			spi@1 { /* chips select 1 */
+				compatible = "tegra-spidev";
+				reg = <0x1>;
+				spi-max-frequency = <50000000>;
+			};
+		};
+
+		mmc@3400000 {
+			vmmc-supply = <&vdd_3v3_sd>;
+		};
+
+		padctl@3520000 {
+			ports {
+				usb2-0 {
+					mode = "otg";
+					usb-role-switch;
+				};
+			};
+		};
+
+		aconnect@2900000 {
+			ahub@2900800 {
+				i2s@2901000 {
+					ports {
+						port@1 {
+							endpoint {
+								/delete-property/ remote-endpoint;
+							};
+						};
+					};
+				};
+
+				i2s@2901100 {
+					ports {
+						port@1 {
+							hdr40_snd_i2s_dap_ep: endpoint {
+							};
+						};
+					};
+				};
+			};
+		};
+
+		i2c@31e0000 {
+			audio-codec@1c {
+				port {
+					endpoint {
+						/delete-property/ remote-endpoint;
+					};
+				};
+			};
+		};
+
+		mgbe0: ethernet@6800000 {
+			nvidia,mac-addr-idx = <0>;
+			nvidia,max-platform-mtu = <16383>;
+			/* 1=enable, 0=disable */
+			nvidia,pause_frames = <1>;
+			phy-handle = <&mgbe0_aqr113c_phy>;
+			/* 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */
+			nvidia,phy-iface-mode = <0>;
+			nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(Y, 1) 0>;
+			nvidia,mdio_addr = <0>;
+
+			mdio {
+				compatible = "nvidia,eqos-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mgbe0_aqr113c_phy: phy@0 {
+					compatible = "ethernet-phy-ieee802.3-c45";
+					reg = <0x0>;
+					nvidia,phy-rst-pdelay-msec = <150>; /* msec */
+					nvidia,phy-rst-duration-usec = <221000>; /* usec */
+					interrupt-parent = <&gpio>;
+					interrupts = <TEGRA234_MAIN_GPIO(Y, 3) IRQ_TYPE_LEVEL_LOW>;
+				};
+			};
+		};
+
+		nvpps {
+			status = "okay";
+			compatible = "nvidia,tegra234-nvpps";
+			primary-emac = <&mgbe0>;
+			sec-emac = <&mgbe0>;
+			reg = <0x0 0xc6a0000 0x0 0x1000>;
+		};
+	};
+
+	hdr40_vdd_3v3: regulator@3 {
+		compatible = "regulator-fixed";
+		reg = <3>;
+		regulator-name = "vdd-3v3-sys";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	tegra_sound: sound {
+		clocks = <&bpmp TEGRA234_CLK_PLLA>,
+			 <&bpmp TEGRA234_CLK_PLLA_OUT0>,
+			 <&bpmp TEGRA234_CLK_AUD_MCLK>;
+		clock-names = "pll_a", "plla_out0", "extern1";
+		assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+		assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+
+		mclk-fs = <256>;
+
+		/delete-property/ widgets;
+		/delete-property/ routing;
+	};
+
+	eeprom-manager {
+		data-size = <0x100>;
+		bus@0 {
+			i2c-bus = <&gen1_i2c>;
+			eeprom@1 {
+				slave-address = <0x56>;
+				label = "cvb";
+			};
+		};
+		bus@1 {
+			i2c-bus = <&cam_i2c>;
+			eeprom@0 {
+				slave-address = <0x54>;
+				label = "sensor0";
+			};
+			eeprom@1 {
+				slave-address = <0x57>;
+				label = "sensor1";
+			};
+			eeprom@2 {
+				slave-address = <0x52>;
+				label = "sensor2";
+			};
+		};
+	};
+
+	vdd_3v3_sd: regulator-vdd-3v3-sd {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_3V3_SD";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio TEGRA234_MAIN_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+	};
+};

nv-platform/tegra234-p3740-0002+p3701-0008-nv-common.dtsi

@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "nv-soc/tegra234-overlay.dtsi"
+#include "nv-soc/tegra234-soc-camera.dtsi"
+#include "tegra234-camera-p3785.dtsi"
+#include "tegra234-p3740-0002.dtsi"
+#include "tegra234-p3701-0008.dtsi"
+#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
+
+/ {
+	aliases {
+		serial2 = "/bus@0/serial@3110000";
+	};
+
+	chosen {
+		bootargs = "console=ttyTCU0,115200n8";
+	};
+
+	cpus {
+		idle-states {
+			c7 {
+				status = "okay";
+			};
+		};
+	};
+
+	nvpmodel {
+		status = "okay";
+	};
+
+	soctherm-oc-event {
+		status = "okay";
+	};
+
+	thermal-zones {
+		cpu-thermal {
+			cooling-maps {
+				map-hot-surface-alert {
+					cooling-device = <&hot_surface_alert 0 0>;
+				};
+			};
+		};
+
+		cv0-thermal {
+			cooling-maps {
+				map-hot-surface-alert {
+					cooling-device = <&hot_surface_alert 0 0>;
+				};
+			};
+		};
+
+		cv1-thermal {
+			cooling-maps {
+				map-hot-surface-alert {
+					cooling-device = <&hot_surface_alert 0 0>;
+				};
+			};
+		};
+
+		cv2-thermal {
+			cooling-maps {
+				map-hot-surface-alert {
+					cooling-device = <&hot_surface_alert 0 0>;
+				};
+			};
+		};
+
+		gpu-thermal {
+			cooling-maps {
+				map-hot-surface-alert {
+					cooling-device = <&hot_surface_alert 0 0>;
+				};
+			};
+		};
+
+		soc0-thermal {
+			cooling-maps {
+				map-hot-surface-alert {
+					cooling-device = <&hot_surface_alert 0 0>;
+				};
+			};
+		};
+
+		soc1-thermal {
+			cooling-maps {
+				map-hot-surface-alert {
+					cooling-device = <&hot_surface_alert 0 0>;
+				};
+			};
+		};
+
+		soc2-thermal {
+			cooling-maps {
+				map-hot-surface-alert {
+					cooling-device = <&hot_surface_alert 0 0>;
+				};
+			};
+		};
+	};
+
+	bus@0 {
+		smmu_test {
+			compatible = "nvidia,smmu_test";
+			iommus = <&smmu_niso0 TEGRA234_SID_SMMU_TEST>;
+			status = "okay";
+		};
+
+		pinmux@2430000 {
+			status = "okay";
+		};
+
+		serial@3110000 {
+			compatible = "nvidia,tegra194-hsuart";
+			reset-names = "serial";
+			status = "okay";
+		};
+
+		serial@31d0000 {
+			current-speed = <115200>;
+			status = "okay";                        
+		};
+
+		tachometer@39c0000 {
+			status = "okay";
+		};
+
+		hsp@3c00000 {
+			status = "okay";
+		};
+
+		hsp@c150000 {
+			status = "okay";
+		};
+
+		mttcan@c310000 {
+			status = "okay";
+		};
+
+		mttcan@c320000 {
+			status = "okay";
+		};
+
+		actmon@d230000 {
+			status = "okay";
+		};
+
+		hwpm@f100000 {
+			status = "okay";
+		};
+
+		mc-hwpm@2c10000 {
+			status = "okay";
+		};
+
+		aconnect@2900000 {
+			adsp@2993000 {
+				status = "okay";
+			};
+		};
+
+		host1x@13e00000 {
+			nvjpg@15380000 {
+				status = "okay";
+			};
+
+			nvenc@154c0000 {
+				status = "okay";
+			};
+
+			tsec@15500000 {
+				status = "okay";
+			};
+
+			nvjpg@15540000 {
+				status = "okay";
+			};
+
+			crypto@15820000 {
+				status = "okay";
+			};
+
+			crypto@15840000 {
+				status = "okay";
+			};
+
+			nvdla0@15880000 {
+				status = "okay";
+			};
+
+			nvdla1@158c0000 {
+				status = "okay";
+			};
+
+			ofa@15a50000 {
+				status = "okay";
+			};
+
+			pva0@16000000 {
+				status = "okay";
+
+				pva0_niso1_ctx0 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx1 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx2 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx3 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx4 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx5 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx6 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx7 {
+					status = "okay";
+				};
+			};
+		};
+
+		gpu@17000000 {
+			status = "okay";
+		};
+	};
+
+	tegra-hsp@b950000 {
+		status = "okay";
+	};
+
+	dce@d800000 {
+		status = "okay";
+	};
+
+	tegra_mce@e100000 {
+		status = "okay";
+	};
+
+	display@13800000 {
+		status = "okay";
+	};
+};

nv-platform/tegra234-p3740-0002+p3701-0008-nv-safety.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+//
+// ### WARNING ###
+// DO NOT ENABLE TPM DEVICE IN THE IGX DEVICE TREE
+// IF NEEDED, PLEASE REACH OUT TO THE NVIDIA IGX PRODUCT TEAM
+// IT IS ILLEGAL TO ENABLE TPM FOR DEVICE GETTING SHIPPED TO CHINA
+
+/dts-v1/;
+
+#include "tegra234-p3740-0002+p3701-0008.dts"
+#include "tegra234-p3740-0002+p3701-0008-nv-common.dtsi"
+#include "tegra234-p3740-0002+p3701-0008-safety.dtsi"

nv-platform/tegra234-p3740-0002+p3701-0008-nv.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+// 
+// ### WARNING ###
+// DO NOT ENABLE TPM DEVICE IN THE IGX DEVICE TREE
+// IF NEEDED, PLEASE REACH OUT TO THE NVIDIA IGX PRODUCT TEAM
+// IT IS ILLEGAL TO ENABLE TPM FOR DEVICE GETTING SHIPPED TO CHINA
+
+/dts-v1/;
+
+#include "tegra234-p3740-0002+p3701-0008.dts"
+#include "tegra234-p3740-0002+p3701-0008-nv-common.dtsi"

nv-platform/tegra234-p3740-0002+p3701-0008-safety.dtsi

@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "nv-soc/tegra234-soc-safetyservice-fsicom.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt/tegra234-irq.h>
+
+/ {
+	compatible = "nvidia,p3740-0002+p3701-0008", "safety", "nvidia,p3701-0008", "nvidia,tegra234";
+
+	bus@0 {
+		i2c@3160000 {
+			nvidia,epl-reporter-id = <0x8050>;
+		};
+
+		i2c@c240000 {
+			nvidia,epl-reporter-id = <0x8051>;
+		};
+
+		i2c@3180000 {
+			nvidia,epl-reporter-id = <0x8052>;
+		};
+
+		i2c@3190000 {
+			nvidia,epl-reporter-id = <0x8053>;
+		};
+
+		i2c@31b0000 {
+			nvidia,epl-reporter-id = <0x8054>;
+		};
+
+		i2c@31c0000 {
+			nvidia,epl-reporter-id = <0x8056>;
+		};
+
+		i2c@c250000 {
+			nvidia,epl-reporter-id = <0x8057>;
+		};
+
+		i2c@31e0000 {
+			nvidia,epl-reporter-id = <0x8058>;
+		};
+
+		hsp_top2: hsp@1600000 {
+			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "shared1", "shared2";
+			status = "okay";
+		};
+
+		spi@3230000  {
+			compatible = "nvidia,tegra186-spi-slave";
+			status = "okay";
+			spi@0 {
+				compatible = "nvidia,tegra-spidev";
+				reg = <0>;
+				spi-max-frequency = <50000000>;
+				controller-data {
+					nvidia,lsbyte-first;
+				};
+			};
+		};
+	};
+
+	chosen {
+		/*
+		 * The ideal approach for disabling rail-gating
+		 * for GPU should be deleting the power-domains
+		 * property in GPU node. But /delete-property/
+		 * is not a valid syntax in the device tree
+		 * overlay, the nvidia,tegra-joint_xpu_rail is
+		 * specified to achieve the same as an
+		 * alternative.
+		 */
+		nvidia,tegra-joint_xpu_rail;
+	};
+
+	cpus {
+		idle-states {
+			c7 {
+				status = "disabled";
+			};
+		};
+	};
+
+	fsicom_client {
+		status = "okay";
+	};
+
+	FsiComIvc {
+		status = "okay";
+	};
+
+	/* FSI<->CCPLEX Communication through DRAM Carveout demo app */
+	FsiComAppChConfApp1 {
+		compatible = "nvidia,tegra-fsicom-sampleApp1";
+		status = "okay";
+		channelid_list = <3>;
+	};
+
+	hsierrrptinj {
+		compatible = "nvidia,tegra23x-hsierrrptinj";
+		mboxes = <&hsp_top0 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(1)>;
+		mbox-names = "hsierrrptinj-tx";
+		status = "okay";
+	};
+
+	safetyservices_epl_client@110000 {
+		/* userspace app uses this driver to send error code */
+		status = "okay";
+	};
+
+	thermal-zones {
+		cpu-thermal {
+			cooling-maps {
+				map-cpufreq {
+					cooling-device = <&cpu0_0 0 0>,
+							 <&cpu1_0 0 0>,
+							 <&cpu2_0 0 0>;
+				};
+
+				map-devfreq {
+					cooling-device = <&ga10b 0 0>;
+				};
+
+				map-throttle-alert {
+					cooling-device = <&cpu_throttle_alert 0 0>;
+				};
+			};
+		};
+
+		gpu-thermal {
+			cooling-maps {
+				map-cpufreq {
+					cooling-device = <&cpu0_0 0 0>,
+							 <&cpu1_0 0 0>,
+							 <&cpu2_0 0 0>;
+				};
+
+				map-devfreq {
+					cooling-device = <&ga10b 0 0>;
+				};
+
+				map-throttle-alert {
+					cooling-device = <&gpu_throttle_alert 0 0>;
+				};
+			};
+		};
+
+		cv0-thermal {
+			cooling-maps {
+				map-cpufreq {
+					cooling-device = <&cpu0_0 0 0>,
+							 <&cpu1_0 0 0>,
+							 <&cpu2_0 0 0>;
+				};
+
+				map-devfreq {
+					cooling-device = <&ga10b 0 0>;
+				};
+
+				map-throttle-alert {
+					cooling-device = <&cv0_throttle_alert 0 0>;
+				};
+			};
+		};
+
+		cv1-thermal {
+			cooling-maps {
+				map-cpufreq {
+					cooling-device = <&cpu0_0 0 0>,
+							 <&cpu1_0 0 0>,
+							 <&cpu2_0 0 0>;
+				};
+
+				map-devfreq {
+					cooling-device = <&ga10b 0 0>;
+				};
+
+				map-throttle-alert {
+					cooling-device = <&cv1_throttle_alert 0 0>;
+				};
+			};
+		};
+
+		cv2-thermal {
+			cooling-maps {
+				map-cpufreq {
+					cooling-device = <&cpu0_0 0 0>,
+							 <&cpu1_0 0 0>,
+							 <&cpu2_0 0 0>;
+				};
+
+				map-devfreq {
+					cooling-device = <&ga10b 0 0>;
+				};
+
+				map-throttle-alert {
+					cooling-device = <&cv2_throttle_alert 0 0>;
+				};
+			};
+		};
+
+		soc0-thermal {
+			cooling-maps {
+				map-cpufreq {
+					cooling-device = <&cpu0_0 0 0>,
+							 <&cpu1_0 0 0>,
+							 <&cpu2_0 0 0>;
+				};
+
+				map-devfreq {
+					cooling-device = <&ga10b 0 0>;
+				};
+
+				map-throttle-alert {
+					cooling-device = <&soc0_throttle_alert 0 0>;
+				};
+			};
+		};
+
+		soc1-thermal {
+			cooling-maps {
+				map-cpufreq {
+					cooling-device = <&cpu0_0 0 0>,
+							 <&cpu1_0 0 0>,
+							 <&cpu2_0 0 0>;
+				};
+
+				map-devfreq {
+					cooling-device = <&ga10b 0 0>;
+				};
+
+				map-throttle-alert {
+					cooling-device = <&soc1_throttle_alert 0 0>;
+				};
+			};
+		};
+
+		soc2-thermal {
+			cooling-maps {
+				map-cpufreq {
+					cooling-device = <&cpu0_0 0 0>,
+							 <&cpu1_0 0 0>,
+							 <&cpu2_0 0 0>;
+				};
+
+				map-devfreq {
+					cooling-device = <&ga10b 0 0>;
+				};
+
+				map-throttle-alert {
+					cooling-device = <&soc2_throttle_alert 0 0>;
+				};
+			};
+		};
+	};
+};

nv-platform/tegra234-p3740-0002.dtsi

@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
+
+/ {
+	bus@0 {
+		i2c@31c0000 {
+			audio-codec@1c {
+				port {
+					endpoint {
+						link-name = "rt5640-playback";
+					};
+				};
+			};
+
+			typec: stusb1600@28 {
+				status = "okay";
+				compatible = "st,stusb1600";
+				reg = <0x28>;
+				vdd-supply = <&p3740_vdd_5v_sys>;
+				vsys-supply = <&vdd_3v3_sys>;
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA234_MAIN_GPIO(K, 6) IRQ_TYPE_LEVEL_LOW>;
+				typec_con: connector {
+					compatible = "usb-c-connector";
+					label = "USB-C";
+					data-role = "dual";
+					power-role = "dual";
+					typec-power-opmode = "default";
+
+					port {
+						typec_con_ep: endpoint {
+							remote-endpoint = <&usb_role_switch0>;
+						};
+					};
+				};
+			};
+		};
+
+		i2c@c250000 {
+			power-sensor@44 {
+				label = "CVB_ATX_12V_8P";
+			};
+
+			f75308@4d {
+				compatible = "fintek,f75308";
+				reg = <0x4d>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				fan@0 {
+					reg = <0x0>;
+					type = "pwm";
+					duty = "manual_duty";
+					5seg = <100 80 60 40 20>;
+				};
+
+				fan@1 {
+					reg = <0x1>;
+					type = "pwm";
+					duty = "manual_duty";
+					5seg = <100 80 60 40 20>;
+				};
+
+				fan@2 {
+					reg = <0x2>;
+					type = "pwm";
+					duty = "manual_duty";
+					5seg = <100 80 60 40 20>;
+				};
+
+				fan@3 {
+					reg = <0x3>;
+					type = "pwm";
+					duty = "manual_duty";
+					5seg = <100 80 60 40 20>;
+				};
+			};
+
+			tca9539@74 {
+				compatible = "ti,tca9539";
+				reg = <0x74>;
+
+				status = "okay";
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA234_MAIN_GPIO(G, 5) IRQ_TYPE_LEVEL_LOW>;
+				vcc-supply = <&vdd_3v3_ao>;
+				#gpio-cells = <2>;
+				gpio-controller;
+			};
+		};
+
+		padctl@3520000 {
+			ports {
+				usb2-0 {
+					port {
+						usb_role_switch0: endpoint {
+							remote-endpoint = <&typec_con_ep>;
+						};
+					};
+				};
+			};
+		};
+	};
+
+
+	sound {
+		clocks = <&bpmp TEGRA234_CLK_PLLA>,
+			 <&bpmp TEGRA234_CLK_PLLA_OUT0>,
+			 <&bpmp TEGRA234_CLK_AUD_MCLK>;
+		clock-names = "pll_a", "plla_out0", "extern1";
+		assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+		assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+
+		mclk-fs = <256>;
+
+		widgets =
+			"Headphone",    "CVB-RT Headphone Jack",
+			"Microphone",   "CVB-RT Mic Jack",
+			"Speaker",      "CVB-RT Int Spk",
+			"Microphone",   "CVB-RT Int Mic";
+
+		routing =
+			/* I2S4 <-> RT5640 */
+			"CVB-RT AIF1 Playback",       "I2S4 DAP-Playback",
+			"I2S4 DAP-Capture",           "CVB-RT AIF1 Capture",
+			/* RT5640 codec controls */
+			"CVB-RT Headphone Jack",     "CVB-RT HPOL",
+			"CVB-RT Headphone Jack",     "CVB-RT HPOR",
+			"CVB-RT IN1P",               "CVB-RT Mic Jack",
+			"CVB-RT IN2P",               "CVB-RT Mic Jack",
+			"CVB-RT IN2N",               "CVB-RT Mic Jack",
+			"CVB-RT IN3P",               "CVB-RT Mic Jack",
+			"CVB-RT Int Spk",            "CVB-RT SPOLP",
+			"CVB-RT Int Spk",            "CVB-RT SPORP",
+			"CVB-RT Int Spk",            "CVB-RT LOUTL",
+			"CVB-RT Int Spk",            "CVB-RT LOUTR",
+			"CVB-RT DMIC1",              "CVB-RT Int Mic",
+			"CVB-RT DMIC2",              "CVB-RT Int Mic";
+	};
+
+	eeprom-manager {
+		bus@1 {
+			i2c-bus = <&dp_aux_ch2_i2c>;
+			eeprom@0 {
+				slave-address = <0x55>;
+				label = "cvb";
+			};
+		};
+	};
+
+	p3740_vdd_0v95_AO: regulator-vdd-0v95-AO {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-0v95-AO";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <950000>;
+	};
+	p3740_vdd_12v_sys: regulator-vdd-12v-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-12v-sys";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+	p3740_vdd_1v05_AO: regulator-vdd-1v05-AO {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-1v05-AO";
+		regulator-min-microvolt = <1050000>;
+		regulator-max-microvolt = <1050000>;
+	};
+	p3740_vdd_1v0_sys: regulator-vdd-1v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-1v0-sys";
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <1000000>;
+	};
+	p3740_vdd_1v1_sys: regulator-vdd-1v1-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-1v1-sys";
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+	};
+	p3740_vdd_1v8_AO: regulator-vdd-1v8-AO {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-1v8-AO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+	p3740_vdd_1v8_sys: regulator-vdd-1v8-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-1v8-sys";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+	p3740_vdd_2v5_sys: regulator-vdd-2v5-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-2v5-sys";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+	};
+	p3740_vdd_2v8_sys: regulator-vdd-2v8-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-2v8-sys";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+	};
+	p3740_vdd_3v3_AO: regulator-vdd-3v3-AO {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-3v3-AO";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+	p3740_vdd_3v7_AO: regulator-vdd-3v7-AO {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-3v7-AO";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+	};
+	p3740_vdd_5v_sys: regulator-vdd-5v-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-5v-sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+};

nv-platform/tegra234-p3767-0000.dtsi

@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include <dt-bindings/gpio/tegra234-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt/tegra234-irq.h>
+#include "nv-soc/tegra234-soc-thermal.dtsi"
+#include "nv-soc/tegra234-soc-thermal-slowdown-corepair.dtsi"
+#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
+#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
+
+/ {
+	bus@0 {
+		mmc@3400000 {
+			no-sdio;
+			no-mmc;
+			nvidia,cd-wakeup-capable;
+			nvidia,boot-detect-delay = <1000>;
+			vmmc-supply = <&vdd_3v3_sd>;
+		};
+
+		nvrng@3ae0000 {
+			status = "okay";
+		};
+
+		gpu@17000000 {
+			status = "okay";
+		};
+	};
+
+	chosen {
+		nvidia,tegra-joint_xpu_rail;
+	};
+
+	opp-table-cluster0 {
+		opp-1510400000 { /* Max CPU freq for Orin Nano */
+			opp-hz = /bits/ 64 <1510400000>;
+			opp-peak-kBps = <3200000>;
+		};
+
+		opp-1984000000 { /* Max CPU freq for ONX */
+			opp-hz = /bits/ 64 <1984000000>;
+			opp-peak-kBps = <3200000>;
+		};
+	};
+
+	opp-table-cluster1 {
+		opp-1510400000 { /* Max CPU freq for Orin Nano */
+			opp-hz = /bits/ 64 <1510400000>;
+			opp-peak-kBps = <3200000>;
+		};
+
+		opp-1984000000 { /* Max CPU freq for ONX */
+			opp-hz = /bits/ 64 <1984000000>;
+			opp-peak-kBps = <3200000>;
+		};
+	};
+
+	opp-table-cluster2 {
+		opp-1510400000 { /* Max CPU freq for Orin Nano */
+			opp-hz = /bits/ 64 <1510400000>;
+			opp-peak-kBps = <3200000>;
+		};
+
+		opp-1984000000 { /* Max CPU freq for ONX */
+			opp-hz = /bits/ 64 <1984000000>;
+			opp-peak-kBps = <3200000>;
+		};
+	};
+
+	reserved-memory {
+		linux,cma { /* Needed for nvgpu comptags */
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x10000000>; /* 256MB */
+			alignment = <0x0 0x10000>;
+			linux,cma-default;
+			status = "okay";
+		};
+	};
+
+	vdd_3v3_sd: regulator-vdd-3v3-sd {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_3V3_SD";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio TEGRA234_MAIN_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+	};
+
+        hdr40_vdd_3v3: regulator-vdd-3v3-sys {
+		/* BUCK_3V3_EN enable is driven by button MCU */
+		compatible = "regulator-fixed";
+		regulator-name = "VDD-3V3-SYS";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+};

nv-platform/tegra234-p3768-0000+p3767-0000-nv-super.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0000-nv.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0000-super", "nvidia,p3767-0000", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin NX Engineering Reference Developer Kit Super";
+};

nv-platform/tegra234-p3768-0000+p3767-0000-nv-taylor-high.dts

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0000.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0000-taylor-high", "nvidia,p3767-0000", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin NX Taylor High";
+};

nv-platform/tegra234-p3768-0000+p3767-0000-nv-taylor-low.dts

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0000.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0000-taylor-low", "nvidia,p3767-0000", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin NX Taylor Low";
+};

nv-platform/tegra234-p3768-0000+p3767-0000-nv.dts

@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0000.dts"
+#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"

nv-platform/tegra234-p3768-0000+p3767-0001-nv-super.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0001-nv.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0001-super", "nvidia,p3767-0001", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin NX Engineering Reference Developer Kit Super";
+};

nv-platform/tegra234-p3768-0000+p3767-0001-nv.dts

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0000.dts"
+#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0001", "nvidia,p3767-0001", "nvidia,tegra234";
+};

nv-platform/tegra234-p3768-0000+p3767-0003-nv-super.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0003-nv.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0003-super", "nvidia,p3767-0003", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin Nano Engineering Reference Developer Kit Super";
+};
+
+/delete-node/ &{/opp-table-cluster0/opp-1510400000};
+/delete-node/ &{/opp-table-cluster1/opp-1510400000};
+/delete-node/ &{/opp-table-cluster2/opp-1510400000};

nv-platform/tegra234-p3768-0000+p3767-0003-nv.dts

@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0005.dts"
+#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0003", "nvidia,p3767-0003", "nvidia,tegra234";
+
+	bus@0 {
+		host1x@13e00000 {
+			nvdla0@15880000 {
+				status = "disabled";
+			};
+
+			nvdla1@158c0000 {
+				status = "disabled";
+			};
+
+			pva0@16000000 {
+				status = "disabled";
+			};
+		};
+	};
+};

nv-platform/tegra234-p3768-0000+p3767-0004-nv-super.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0004-nv.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0004-super", "nvidia,p3767-0004", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin Nano Engineering Reference Developer Kit Super";
+};
+
+/delete-node/ &{/opp-table-cluster0/opp-1510400000};
+/delete-node/ &{/opp-table-cluster1/opp-1510400000};
+/delete-node/ &{/opp-table-cluster2/opp-1510400000};

nv-platform/tegra234-p3768-0000+p3767-0004-nv.dts

@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0005.dts"
+#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0004", "nvidia,p3767-0004", "nvidia,tegra234";
+
+	bus@0 {
+		host1x@13e00000 {
+			nvdla0@15880000 {
+				status = "disabled";
+			};
+
+			nvdla1@158c0000 {
+				status = "disabled";
+			};
+
+			pva0@16000000 {
+				status = "disabled";
+			};
+		};
+	};
+};

nv-platform/tegra234-p3768-0000+p3767-0005-nv-super.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0005-nv.dts"
+
+/ {
+	compatible = "nvidia,p3768-0000+p3767-0005-super", "nvidia,p3767-0005", "nvidia,tegra234";
+	model = "NVIDIA Jetson Orin Nano Engineering Reference Developer Kit Super";
+};
+
+/delete-node/ &{/opp-table-cluster0/opp-1510400000};
+/delete-node/ &{/opp-table-cluster1/opp-1510400000};
+/delete-node/ &{/opp-table-cluster2/opp-1510400000};

nv-platform/tegra234-p3768-0000+p3767-0005-nv.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+
+#include "tegra234-p3768-0000+p3767-0005.dts"
+#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"
+
+/ {
+	bus@0 {
+		host1x@13e00000 {
+			nvdla0@15880000 {
+				status = "disabled";
+			};
+
+			nvdla1@158c0000 {
+				status = "disabled";
+			};
+
+			pva0@16000000 {
+				status = "disabled";
+			};
+		};
+	};
+};

nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi

@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "nv-soc/tegra234-overlay.dtsi"
+#include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
+#include "tegra234-p3768-0000.dtsi"
+#include "tegra234-p3767-0000.dtsi"
+#include "nv-soc/tegra234-soc-camera.dtsi"
+#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
+#include <dt-bindings/gpio/tegra234-gpio.h>
+
+/ {
+	aliases {
+		serial1 = &uarta;
+		serial2 = &uarte;
+	};
+
+	bpmp {
+		i2c {
+			vrs@3c {
+				compatible = "nvidia,vrs-pseq";
+				reg = <0x3c>;
+				interrupt-parent = <&pmc>;
+				/* VRS Wake ID is 24 */
+				interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "okay";
+			};
+		};
+	};
+
+	bus@0 {
+		actmon@d230000 {
+			status = "okay";
+		};
+
+		pinmux@2430000 {
+			status = "okay";
+		};
+
+		i2c@3180000 {
+			status = "okay";
+		};
+
+		aconnect@2900000 {
+			adsp@2993000 {
+				status = "okay";
+			};
+		};
+
+		i2c@31b0000 {
+			status = "okay";
+		};
+
+		hdr40_i2c1: i2c@c250000 {
+			status = "okay";
+		};
+
+		/* SPI1, 40pin header, Pin 19(MOSI), Pin 21(MISO), Pin 23(CLK), Pin 24(CS) */
+		spi@3210000{
+			status = "okay";
+			spi@0 {
+				compatible = "tegra-spidev";
+				reg = <0x0>;
+				spi-max-frequency = <50000000>;
+				controller-data {
+					nvidia,enable-hw-based-cs;
+					nvidia,rx-clk-tap-delay = <0x10>;
+					nvidia,tx-clk-tap-delay = <0x0>;
+				};
+			};
+			spi@1 {
+				compatible = "tegra-spidev";
+				reg = <0x1>;
+				spi-max-frequency = <50000000>;
+				controller-data {
+					nvidia,enable-hw-based-cs;
+					nvidia,rx-clk-tap-delay = <0x10>;
+					nvidia,tx-clk-tap-delay = <0x0>;
+				};
+			};
+
+		};
+
+		/* SPI3, 40pin header, Pin 37(MOSI), Pin 22(MISO), Pin 13(CLK), Pin 18(CS) */
+		spi@3230000{
+			status = "okay";
+			spi@0 {
+				compatible = "tegra-spidev";
+				reg = <0x0>;
+				spi-max-frequency = <50000000>;
+				controller-data {
+					nvidia,enable-hw-based-cs;
+					nvidia,rx-clk-tap-delay = <0x10>;
+					nvidia,tx-clk-tap-delay = <0x0>;
+				};
+			};
+			spi@1 {
+				compatible = "tegra-spidev";
+				reg = <0x1>;
+				spi-max-frequency = <50000000>;
+				controller-data {
+					nvidia,enable-hw-based-cs;
+					nvidia,rx-clk-tap-delay = <0x10>;
+					nvidia,tx-clk-tap-delay = <0x0>;
+				};
+			};
+		};
+
+		padctl@3520000 {
+			ports {
+				usb2-0 {
+					port {
+						typec_p0: endpoint {
+							remote-endpoint = <&fusb_p0>;
+						};
+					};
+				};
+			};
+		};
+
+		i2c@c240000 {
+			status = "okay";
+			fusb301@25 {
+				compatible = "onsemi,fusb301";
+				reg = <0x25>;
+				status = "okay";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA234_MAIN_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>;
+				connector@0 {
+					port@0 {
+						fusb_p0: endpoint {
+							remote-endpoint = <&typec_p0>;
+						};
+					};
+				};
+			};
+		};
+
+		/* PWM1, 40pin header, pin 15 */
+		pwm@3280000 {
+			status = "okay";
+		};
+
+		/* PWM3, FAN */
+		pwm@32a0000 {
+			status = "okay";
+		};
+
+		/* PWM5, 40pin header, pin 33 */
+		pwm@32c0000 {
+			status = "okay";
+		};
+
+		/* PWM7, 40pin header, pin 32 */
+		pwm@32e0000 {
+			status = "okay";
+		};
+
+		tachometer@39c0000 {
+			status = "okay";
+			upper-threshold = <0xfffff>;
+			lower-threshold = <0x0>;
+		};
+
+		hsp@3d00000 {
+			status = "okay";
+		};
+
+		aon@c000000 {
+			status = "okay";
+		};
+
+		hardware-timestamp@c1e0000 {
+			status = "okay";
+		};
+
+		mttcan@c310000 {
+			status = "okay";
+		};
+
+		hwpm@f100000 {
+			status = "okay";
+		};
+
+		mc-hwpm@2c10000 {
+			status = "okay";
+		};
+
+		host1x@13e00000 {
+			nvdec@15480000 {
+				status = "okay";
+			};
+
+			nvenc@154c0000 {
+				status = "okay";
+			};
+
+			crypto@15820000 {
+				status = "okay";
+			};
+
+			crypto@15840000 {
+				status = "okay";
+			};
+
+			nvdla0@15880000 {
+				status = "okay";
+			};
+
+			nvdla1@158c0000 {
+				status = "okay";
+			};
+
+			ofa@15a50000 {
+				status = "okay";
+			};
+
+			pva0@16000000 {
+				status = "okay";
+
+				pva0_niso1_ctx0 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx1 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx2 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx3 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx4 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx5 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx6 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx7 {
+					status = "okay";
+				};
+			};
+
+			nvjpg@15380000 {
+				status = "okay";
+			};
+
+			nvjpg@15540000 {
+				status = "okay";
+			};
+		};
+	};
+
+	cpus {
+		idle-states {
+			c7 {
+				status = "okay";
+			};
+		};
+	};
+
+	nvpmodel {
+		status = "okay";
+	};
+
+	soctherm-oc-event {
+		status = "okay";
+	};
+
+	tegra-hsp@b950000 {
+		status = "okay";
+	};
+
+	dce@d800000 {
+		status = "okay";
+	};
+
+	display@13800000 {
+		os_gpio_hotplug_a = <&gpio TEGRA234_MAIN_GPIO(M, 0) GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+};

nv-platform/tegra234-p3768-0000.dtsi

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/ {
+	bus@0 {
+
+		aconnect@2900000 {
+			ahub@2900800 {
+				i2s@2901100 {
+					ports {
+						port@1 {
+							hdr40_snd_i2s_dap_ep: endpoint {
+							};
+						};
+					};
+				};
+			};
+		};
+
+	};
+
+	tegra_sound: sound {
+		clocks = <&bpmp TEGRA234_CLK_PLLA>,
+			 <&bpmp TEGRA234_CLK_PLLA_OUT0>,
+			 <&bpmp TEGRA234_CLK_AUD_MCLK>;
+		clock-names = "pll_a", "plla_out0", "extern1";
+		assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+		assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
+	};
+};

nv-platform/tegra234-p3971-0000+p3701-0000-nv.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+#include "../tegra234-p3701-0000.dtsi"
+#include "tegra234-p3701-0000.dtsi"
+#include "tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi"
+
+/ {
+        model = "NVIDIA p3971-0000+p3701-0000";
+        compatible = "nvidia,p3971-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";
+
+};

nv-platform/tegra234-p3971-0000+p3701-0008-nv-safety.dts

@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "tegra234-p3971-0000+p3701-0008-nv.dts"
+#include "tegra234-p3740-0002+p3701-0008-safety.dtsi"
+
+/ {
+	compatible = "nvidia,p3971-0000+p3701-0008", "safety", "nvidia,p3701-0008", "nvidia,tegra234";
+
+};

nv-platform/tegra234-p3971-0000+p3701-0008-nv.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+#include "../tegra234-p3701-0008.dtsi"
+#include "tegra234-p3701-0008.dtsi"
+#include "tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi"
+
+/ {
+        model = "NVIDIA p3971-0000+p3701-0008";
+        compatible = "nvidia,p3971-0000+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";
+
+};

nv-platform/tegra234-p3971-0000+p3701-xxxx-nv-common.dtsi

@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include "nv-soc/tegra234-overlay.dtsi"
+#include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
+#include "nv-soc/tegra234-soc-camera.dtsi"
+
+#include "tegra234-p3971-0000.dtsi"
+
+/ {
+	aliases {
+		serial0 = &tcu;
+		serial1 = &uarta;
+	};
+
+	serial {
+		status = "okay";
+	};
+
+	bus@0 {
+		mc-hwpm@2c10000 {
+			status = "okay";
+		};
+
+		serial@3100000 {
+			compatible = "nvidia,tegra194-hsuart";
+			reset-names = "serial";
+			status = "okay";
+		};
+
+		i2c@3160000 {
+			status = "okay";
+		};
+
+		i2c@3180000 {
+			status = "okay";
+		};
+
+		i2c@3190000 {
+			status = "okay";
+		};
+
+		i2c@31b0000 {
+			status = "okay";
+		};
+
+		i2c@31c0000 {
+			status = "okay";
+
+		};
+
+		i2c@31e0000 {
+			status = "okay";
+		};
+
+		padctl@3520000 {
+			status = "okay";
+
+			pads {
+				usb2 {
+					lanes {
+						usb2-0 {
+							status = "okay";
+						};
+
+						usb2-1 {
+							status = "okay";
+						};
+
+						usb2-2 {
+							status = "okay";
+						};
+
+						usb2-3 {
+							status = "okay";
+						};
+					};
+				};
+
+				usb3 {
+					lanes {
+						usb3-0 {
+							status = "okay";
+						};
+
+						usb3-1 {
+							status = "okay";
+						};
+
+						usb3-2 {
+							status = "okay";
+						};
+					};
+				};
+			};
+
+			ports {
+				usb2-0 {
+					mode = "otg";
+					vbus-supply = <&vdd_5v0_sys>;
+					usb-role-switch;
+					role-switch-default-mode = "peripheral";
+					status = "okay";
+				};
+
+				usb2-1 {
+					mode = "host";
+					vbus-supply = <&vdd_5v0_sys>;
+					status = "okay";
+				};
+
+				usb2-2 {
+					mode = "host";
+					vbus-supply = <&vdd_5v0_sys>;
+					status = "okay";
+				};
+
+				usb2-3 {
+					mode = "host";
+					vbus-supply = <&vdd_5v0_sys>;
+					status = "okay";
+				};
+
+				usb3-0 {
+					nvidia,usb2-companion = <0>;
+					status = "okay";
+				};
+
+				usb3-1 {
+					nvidia,usb2-companion = <3>;
+					status = "okay";
+				};
+
+				usb3-2 {
+					nvidia,usb2-companion = <1>;
+					status = "okay";
+				};
+			};
+		};
+
+		usb@3550000 {
+			status = "okay";
+			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>;
+			phy-names = "usb2-0", "usb3-0";
+		};
+
+		usb@3610000 {
+			status = "okay";
+			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+			     <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+			     <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
+			     <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
+			     <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
+			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0", "usb3-1", "usb3-2";
+		};
+
+		hardware-timestamp@3aa0000 {
+			status = "okay";
+		};
+
+		hsp@3c00000 {
+			status = "okay";
+		};
+
+		hsp@c150000 {
+			status = "okay";
+		};
+
+		hardware-timestamp@c1e0000 {
+			status = "okay";
+		};
+
+		i2c@c240000 {
+			status = "okay";
+		};
+
+		i2c@c250000 {
+			status = "okay";
+		};
+
+		mttcan@c310000 {
+			status = "okay";
+		};
+
+		mttcan@c320000 {
+			status = "okay";
+		};
+
+		actmon@d230000 {
+			status = "okay";
+		};
+
+		hwpm@f100000 {
+			status = "okay";
+		};
+
+		host1x@13e00000 {
+			nvjpg@15380000 {
+				status = "okay";
+			};
+
+			nvdec@15480000 {
+				status = "okay";
+			};
+
+			nvenc@154c0000 {
+				status = "okay";
+			};
+
+			tsec@15500000 {
+				status = "okay";
+			};
+
+			nvjpg@15540000 {
+				status = "okay";
+			};
+
+			se@15810000 {
+				status = "okay";
+			};
+
+			se@15820000 {
+				status = "okay";
+			};
+
+			se@15840000 {
+				status = "okay";
+			};
+
+			nvdla0@15880000 {
+				status = "okay";
+			};
+
+			nvdla1@158c0000 {
+				status = "okay";
+			};
+
+			ofa@15a50000 {
+				status = "okay";
+			};
+
+			pva0@16000000 {
+				status = "okay";
+
+				pva0_niso1_ctx0 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx1 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx2 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx3 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx4 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx5 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx6 {
+					status = "okay";
+				};
+
+				pva0_niso1_ctx7 {
+					status = "okay";
+				};
+			};
+		};
+
+		gpu@17000000 {
+			status = "okay";
+		};
+	};
+
+	tegra-hsp@b950000 {
+		status = "okay";
+	};
+
+	dce@d800000 {
+		status = "okay";
+	};
+
+	tegra_mce@e100000 {
+		status = "okay";
+	};
+
+	display@13800000 {
+		status = "okay";
+	};
+
+	cpus {
+		idle-states {
+			c7 {
+				status = "okay";
+			};
+		};
+	};
+
+	nvpmodel {
+		status = "okay";
+	};
+
+	soctherm-oc-event {
+		status = "okay";
+	};
+};

nv-platform/tegra234-p3971-0000.dtsi

@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/input/gpio-keys.h>
+#include "tegra234-dcb-p3971-0000+p3701-0000.dtsi"
+#include <dt-bindings/sound/rt5640.h>
+
+/ {
+	bus@0 {
+		aconnect@2900000 {
+			ahub@2900800 {
+				i2s@2901300 {
+					ports {
+						port@1 {
+							endpoint {
+								dai-format = "i2s";
+								remote-endpoint = <&rt5640_ep>;
+							};
+						};
+					};
+				};
+			};
+		};
+
+		hda@3510000 {
+			nvidia,model = "NVIDIA IGX500 Orin HDA";
+			status = "okay";
+		};
+
+		i2c@3160000 {
+			status = "okay";
+
+			eeprom@56 {
+				compatible = "atmel,24c02";
+				reg = <0x56>;
+
+				label = "system";
+				vcc-supply = <&vdd_1v8_cvb>;
+				address-width = <8>;
+				pagesize = <8>;
+				size = <256>;
+				read-only;
+			};
+		};
+
+		i2c@31b0000 {
+			status = "okay";
+		};
+
+		host1x@13e00000 {
+			tsec@15500000 {
+				status = "okay";
+			};
+		};
+
+		i2c@31c0000 {
+			status = "okay";
+
+			rt5640: audio-codec@1c {
+				compatible = "realtek,rt5640";
+				reg = <0x1c>;
+
+				clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+				clock-names = "mclk";
+
+				realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
+				realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
+				realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
+
+				/* Codec IRQ output */
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+
+				#sound-dai-cells = <1>;
+				sound-name-prefix = "CVB-RT";
+
+				status = "okay";
+
+				port {
+					rt5640_ep: endpoint {
+						remote-endpoint = <&i2s4_dap>;
+						mclk-fs = <256>;
+					};
+				};
+			};
+		};
+
+		/* SPI1 in 40 pin conn */
+		spi@3210000 {
+			status = "okay";
+			spi@0 { /* chip select 0 */
+				compatible = "tegra-spidev";
+				reg = <0x0>;
+				spi-max-frequency = <50000000>;
+			};
+
+			spi@1 { /* chips select 1 */
+				compatible = "tegra-spidev";
+				reg = <0x1>;
+				spi-max-frequency = <50000000>;
+			};
+		};
+
+		/* SPI3 is connected to Aurix */
+		spi@3230000 {
+			status = "disabled";
+		};
+
+		pwm@3280000 {
+			status = "okay";
+		};
+
+
+		pwm@32f0000 {
+			status = "okay";
+		};
+
+		/* Enable fan PWM */
+		pwm@32a0000 {
+			status = "okay";
+		};
+
+		/*
+		 * This is on 40-pin header (pin-18)
+		 * On Orin, the pad control configures it as GPIO/SDMMC.
+		 * No pwm support.
+		 */
+		pwm@32c0000 {
+			status = "disabled";
+		};
+
+		tachometer@39c0000 {
+			status = "okay";
+		};
+
+		pcie@14100000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_hsio_3>;
+			phy-names = "p2u-0";
+		};
+
+		pcie@14160000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+			     <&p2u_hsio_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+		};
+
+		pcie@141a0000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+			     <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+			     <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+				"p2u-5", "p2u-6", "p2u-7";
+		};
+
+		pcie@141e0000 {
+			status = "okay";
+
+			vddio-pex-ctl-supply = <&vdd_3v3_ao_cvb>;
+
+			phys = <&p2u_gbe_0>, <&p2u_gbe_1>, <&p2u_gbe_2>, <&p2u_gbe_3>,
+			     <&p2u_gbe_4>, <&p2u_gbe_5>, <&p2u_gbe_6>, <&p2u_gbe_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+				"p2u-5", "p2u-6", "p2u-7";
+		};
+
+		ufshci@2500000 {
+			status = "okay";
+		};
+	};
+
+	chosen {
+		bootargs = "console=ttyTCU0,115200n8";
+		stdout-path = "serial0:115200n8";
+	};
+
+        display@13800000 {
+                status = "okay";
+        };
+
+	eeprom-manager {
+		data-size = <0x100>;
+		bus@0 {
+			i2c-bus = <&gen1_i2c>;
+			eeprom@1 {
+				slave-address = <0x56>;
+				label = "cvb";
+			};
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		pwms = <&pwm3 0 45334>;
+		#cooling-cells = <2>;
+	};
+
+	/* fan_nvme is no-stuff, same PWM instance is routed to 40-pin header */
+	fan_nvme: pwm-fan-nvme {
+		compatible = "pwm-fan";
+		pwms = <&pwm8 0 45334>;
+		#cooling-cells = <2>;
+		status = "disabled";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		key-force-recovery {
+			label = "Force Recovery";
+			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <BTN_1>;
+		};
+
+		key-power {
+			label = "Power";
+			gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_POWER>;
+			wakeup-event-action = <EV_ACT_ASSERTED>;
+			wakeup-source;
+		};
+	};
+
+	vcc_src_20v_cvb: regulator-vcc-src-fet {
+		compatible = "regulator-fixed";
+		reg = <1>;
+		regulator-name = "VCC_SRC_FET";
+		regulator-min-microvolt = <20000000>;
+		regulator-max-microvolt = <20000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_5v_cvb: vdd_5v_ao_cvb: regulator-vdd-5v-ao {
+		compatible = "regulator-fixed";
+		reg = <2>;
+		regulator-name = "VDD_5V_AO";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	vdd_3v3_cbv: regulator-vdd-3v3 {
+		compatible = "regulator-fixed";
+		reg = <3>;
+		regulator-name = "VDD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vdd_3v3_ao_cvb: regulator-vdd-3v3-ao {
+		compatible = "regulator-fixed";
+		reg = <4>;
+		regulator-name = "VDD_3V3_AO";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vdd_1v8_cvb: regulator-vdd-1v8 {
+		compatible = "regulator-fixed";
+		reg = <5>;
+		regulator-name = "VDD_1V8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vdd_12v_cvb: regulator-vdd-12v {
+		compatible = "regulator-fixed";
+		reg = <6>;
+		regulator-name = "VDD_12V";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
+		regulator-always-on;
+	};
+
+	vdd_3v3_dp_en: regulator-vdd-3v3-dp-en {
+		compatible = "regulator-fixed";
+		reg = <7>;
+		regulator-name = "VDD_3V3_DP_EN";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		enable-active-high;
+	};
+
+	sound {
+		status = "okay";
+
+		compatible = "nvidia,tegra186-audio-graph-card";
+
+		dais = /* ADMAIF (FE) Ports */
+		       <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
+		       <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
+		       <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
+		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
+		       /* XBAR Ports */
+		       <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>,
+		       <&xbar_i2s6_port>, <&xbar_dmic3_port>,
+		       <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
+		       <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
+		       <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
+		       <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
+		       <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
+		       <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
+		       <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
+		       <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
+		       <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
+		       <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
+		       <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
+		       <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
+		       <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
+		       <&xbar_mix_in1_port>, <&xbar_mix_in2_port>,
+		       <&xbar_mix_in3_port>, <&xbar_mix_in4_port>,
+		       <&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
+		       <&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
+		       <&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
+		       <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
+		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
+		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
+		       <&xbar_asrc_in7_port>,
+		       <&xbar_ope1_in_port>,
+		       /* HW accelerators */
+		       <&sfc1_out_port>, <&sfc2_out_port>,
+		       <&sfc3_out_port>, <&sfc4_out_port>,
+		       <&mvc1_out_port>, <&mvc2_out_port>,
+		       <&amx1_out_port>, <&amx2_out_port>,
+		       <&amx3_out_port>, <&amx4_out_port>,
+		       <&adx1_out1_port>, <&adx1_out2_port>,
+		       <&adx1_out3_port>, <&adx1_out4_port>,
+		       <&adx2_out1_port>, <&adx2_out2_port>,
+		       <&adx2_out3_port>, <&adx2_out4_port>,
+		       <&adx3_out1_port>, <&adx3_out2_port>,
+		       <&adx3_out3_port>, <&adx3_out4_port>,
+		       <&adx4_out1_port>, <&adx4_out2_port>,
+		       <&adx4_out3_port>, <&adx4_out4_port>,
+		       <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
+		       <&mix_out4_port>, <&mix_out5_port>,
+		       <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
+		       <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
+		       <&ope1_out_port>,
+		       /* BE I/O Ports */
+		       <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
+		       <&dmic3_port>;
+
+		label = "NVIDIA IGX500 Orin APE";
+
+		widgets = "Microphone",	"CVB-RT MIC Jack",
+			  "Microphone",	"CVB-RT MIC",
+			  "Headphone",	"CVB-RT HP Jack",
+			  "Speaker",	"CVB-RT SPK";
+
+		routing = /* I2S4 <-> RT5640 */
+			  "CVB-RT AIF1 Playback",	"I2S4 DAP-Playback",
+			  "I2S4 DAP-Capture",		"CVB-RT AIF1 Capture",
+			  /* RT5640 codec controls */
+			  "CVB-RT HP Jack",		"CVB-RT HPOL",
+			  "CVB-RT HP Jack",		"CVB-RT HPOR",
+			  "CVB-RT IN1P",		"CVB-RT MIC Jack",
+			  "CVB-RT IN2P",		"CVB-RT MIC Jack",
+			  "CVB-RT IN2N",		"CVB-RT MIC Jack",
+			  "CVB-RT IN3P",		"CVB-RT MIC Jack",
+			  "CVB-RT SPK",			"CVB-RT SPOLP",
+			  "CVB-RT SPK",			"CVB-RT SPORP",
+			  "CVB-RT SPK",			"CVB-RT LOUTL",
+			  "CVB-RT SPK",			"CVB-RT LOUTR",
+			  "CVB-RT DMIC1",		"CVB-RT MIC",
+			  "CVB-RT DMIC2",		"CVB-RT MIC";
+	};
+};

nv-soc/tegra234-base-overlay.dtsi

@@ -0,0 +1,694 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+// This file contains the additional parameters which are missing from DT nodes of T234
+// available in base/tegra234.dtsi
+
+#include <dt-bindings/clock/tegra234-clock.h>
+#include <dt-bindings/reset/tegra234-reset.h>
+#include <dt-bindings/memory/tegra234-mc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt/tegra234-irq.h>
+#include <dt-bindings/gpio/tegra234-gpio.h>
+#include <dt-bindings/p2u/tegra234-p2u.h>
+#include <dt-bindings/power/tegra234-powergate.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+#define TEGRA234_POWER_DOMAIN_PVA		30U
+#define TEGRA234_POWER_DOMAIN_GPU		35U
+#define TEGRA234_POWER_DOMAIN_DLAA		32U
+#define TEGRA234_POWER_DOMAIN_DLAB		33U
+
+/ {
+	aliases {
+		i2c0 = "/bus@0/i2c@3160000";
+		i2c1 = "/bus@0/i2c@c240000";
+		i2c2 = "/bus@0/i2c@3180000";
+		i2c3 = "/bus@0/i2c@3190000";
+		i2c4 = "/bpmp/i2c";
+		i2c5 = "/bus@0/i2c@31b0000";
+		i2c6 = "/bus@0/i2c@31c0000";
+		i2c7 = "/bus@0/i2c@c250000";
+		i2c8 = "/bus@0/i2c@31e0000";
+		qspi0 = "/bus@0/spi@3270000";
+		rtc0 = "/bpmp/i2c/vrs@3c";
+		rtc1 = "/bus@0/rtc@c2a0000";
+	};
+
+	bus@0 {
+		usb@3610000 {
+			/delete-property/ interrupts;
+			interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				     <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 76 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 77 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 78 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 79 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 80 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 81 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 82 IRQ_TYPE_LEVEL_HIGH>;
+			/*
+			   wake0, wake1, wake2 are for USB3.0 ports
+			   wake3, wake4, wake5, wake6 are for USB2.0 ports
+			*/
+			interrupt-names = "xhci", "mbox",
+				  "wake0", "wake1", "wake2", "wake3",
+				  "wake4", "wake5", "wake6";
+		};
+
+		pcie@140a0000 {
+			iommus = <&smmu_niso1 TEGRA234_SID_PCIE8>;
+		};
+
+		pcie@140c0000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE9>;
+		};
+
+		pcie@140e0000 {
+			iommus = <&smmu_niso1 TEGRA234_SID_PCIE10>;
+		};
+
+		pcie@14100000 {
+			iommus = <&smmu_niso1 TEGRA234_SID_PCIE1>;
+		};
+
+		pcie@14120000 {
+			iommus = <&smmu_niso1 TEGRA234_SID_PCIE2>;
+		};
+
+		pcie@14140000 {
+			iommus = <&smmu_niso1 TEGRA234_SID_PCIE3>;
+		};
+
+		pcie@14160000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>;
+		};
+
+		pcie@14180000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE0>;
+		};
+
+		pcie@141a0000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE5>;
+		};
+
+		pcie@141c0000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE6>;
+		};
+
+		pcie@141e0000 {
+			iommus = <&smmu_niso1 TEGRA234_SID_PCIE7>;
+		};
+
+		pcie-ep@141a0000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE5>;
+		};
+
+		pcie-ep@141c0000{
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE6>;
+		};
+
+		pcie-ep@141e0000{
+			iommus = <&smmu_niso1 TEGRA234_SID_PCIE7>;
+		};
+
+		pcie-ep@140e0000{
+			iommus = <&smmu_niso1 TEGRA234_SID_PCIE10>;
+		};
+
+		hda@3510000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
+		};
+
+		aconnect@2900000 {
+			ahub@2900800 {
+				assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
+						  <&bpmp TEGRA234_CLK_PLLA_OUT0>,
+						  <&bpmp TEGRA234_CLK_AHUB>;
+				assigned-clock-parents = <0>,
+						<&bpmp TEGRA234_CLK_PLLA>,
+						<&bpmp TEGRA234_CLK_PLLP_OUT0>;
+				assigned-clock-rates = <294912000>,
+						       <49152000>,
+						       <81600000>;
+
+				/*
+				 * Below modules are upstreamed and present in v5.15,
+				 * but not yet feature complete. Thus use OOT driver
+				 * versions for now.
+				 */
+				i2s@2901000 {
+					nvidia,ahub-i2s-id = <0>;
+				};
+
+				i2s@2901100 {
+					nvidia,ahub-i2s-id = <1>;
+				};
+
+				i2s@2901200 {
+					nvidia,ahub-i2s-id = <2>;
+				};
+
+				i2s@2901300 {
+					nvidia,ahub-i2s-id = <3>;
+				};
+
+				i2s@2901400 {
+					nvidia,ahub-i2s-id = <4>;
+				};
+
+				i2s@2901500 {
+					nvidia,ahub-i2s-id = <5>;
+				};
+			};
+
+			/*
+			 * Placeholder for ADSP audio device.
+			 * Not required for L4T releases, will be
+			 * enabled as and when needed.
+			 */
+			tegra_adsp_audio: adsp_audio {
+				status = "disabled";
+			};
+		};
+
+		ethernet@2310000 {
+			compatible = "nvidia,nveqos";
+			reg = <0x0 0x02310000 0x0 0x10000>,    /* EQOS Base Register */
+			      <0x0 0x023D0000 0x0 0x10000>,    /* MACSEC Base Register */
+			      <0x0 0x02300000 0x0 0x10000>;    /* HV Base Register */
+			reg-names = "mac", "macsec-base", "hypervisor";
+			interrupts = <0 194 0x4>,       /* common */
+				     <0 186 0x4>, /* vm0 */
+				     <0 187 0x4>, /* vm1 */
+				     <0 188 0x4>, /* vm2 */
+				     <0 189 0x4>, /* vm3 */
+				     <0 190 0x4>, /* MACsec non-secure intr */
+				     <0 191 0x4>; /* MACsec secure intr */
+			interrupt-names = "common", "vm0", "vm1", "vm2", "vm3",
+					  "macsec-ns-irq", "macsec-s-irq";
+			resets = <&bpmp TEGRA234_RESET_EQOS>,
+				 <&bpmp TEGRA234_RESET_EQOS_MACSEC>; /* MACsec non-secure reset */
+			reset-names = "mac", "macsec_ns_rst";
+			clocks = <&bpmp TEGRA234_CLK_PLLREFE_VCOOUT>,
+				 <&bpmp TEGRA234_CLK_EQOS_AXI>,
+				 <&bpmp TEGRA234_CLK_EQOS_RX>,
+				 <&bpmp TEGRA234_CLK_EQOS_PTP_REF>,
+				 <&bpmp TEGRA234_CLK_EQOS_TX>,
+				 <&bpmp TEGRA234_CLK_AXI_CBB>,
+				 <&bpmp TEGRA234_CLK_EQOS_RX_M>,
+				 <&bpmp TEGRA234_CLK_EQOS_RX_INPUT>,
+				 <&bpmp TEGRA234_CLK_EQOS_MACSEC_TX>,
+				 <&bpmp TEGRA234_CLK_EQOS_TX_DIVIDER>,
+				 <&bpmp TEGRA234_CLK_EQOS_MACSEC_RX>;
+			clock-names = "pllrefe_vcoout", "eqos_axi", "eqos_rx",
+				      "eqos_ptp_ref", "eqos_tx", "axi_cbb",
+				      "eqos_rx_m", "eqos_rx_input",
+				      "eqos_macsec_tx", "eqos_tx_divider",
+				      "eqos_macsec_rx";
+#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
+			interconnects = <&mc TEGRA234_MEMORY_CLIENT_EQOSR>,
+					<&mc TEGRA234_MEMORY_CLIENT_EQOSW>;
+			interconnect-names = "dma-mem", "write";
+#endif
+			iommus = <&smmu_niso1 TEGRA234_SID_EQOS>;
+			nvidia,num-dma-chans = <8>;
+			nvidia,num-mtl-queues = <8>;
+			nvidia,mtl-queues = <0 1 2 3 4 5 6 7>;
+			nvidia,dma-chans = <0 1 2 3 4 5 6 7>;
+			nvidia,tc-mapping = <0 1 2 3 4 5 6 7>;
+			/* Residual Queue can be any valid queue except RxQ0 */
+			nvidia,residual-queue = <1>;
+			nvidia,rx-queue-prio = <0x2 0x1 0x30 0x48 0x0 0x0 0x0 0x0>;
+			nvidia,tx-queue-prio = <0x0 0x7 0x2 0x3 0x0 0x0 0x0 0x0>;
+			nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2>;
+			nvidia,vm-irq-config = <&eqos_vm_irq_config>;
+			status = "disabled";
+			nvidia,dcs-enable = <0x1>;
+			nvidia,macsec-enable = <0>;
+			nvidia,pad_calibration = <0x1>;
+			/* pad calibration 2's complement offset for pull-down value */
+			nvidia,pad_auto_cal_pd_offset = <0x0>;
+			/* pad calibration 2's complement offset for pull-up value */
+			nvidia,pad_auto_cal_pu_offset = <0x0>;
+			nvidia,rx_riwt = <512>;
+			nvidia,rx_frames = <64>;
+			nvidia,tx_usecs = <256>;
+			nvidia,tx_frames = <5>;
+			nvidia,promisc_mode = <1>;
+			nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
+			nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
+			nvidia,ptp_ref_clock_speed = <208333334>;
+			nvidia,instance_id = <4>; /* EQOS instance */
+			nvidia,ptp-rx-queue = <3>;
+			pinctrl-names = "mii_rx_disable", "mii_rx_enable";
+			pinctrl-0 = <&eqos_mii_rx_input_state_disable>;
+			pinctrl-1 = <&eqos_mii_rx_input_state_enable>;
+			nvidia,dma_rx_ring_sz = <1024>;
+			nvidia,dma_tx_ring_sz = <1024>;
+			dma-coherent;
+		};
+
+		ethernet@6800000 {
+			reg = <0x0 0x06800000 0x0 0x10000>, /* HV base */
+			      <0x0 0x06810000 0x0 0x10000>, /* MGBE base */
+			      <0x0 0x068A0000 0x0 0x10000>, /* XPCS base */
+			      <0x0 0x068D0000 0x0 0x10000>; /* MACsec RM base */
+			reg-names = "hypervisor", "mac", "xpcs", "macsec-base";
+			interrupts =    <0 384 0x4>,    /* common */
+					<0 385 0x4>,    /* vm0 */
+					<0 386 0x4>,    /* vm1 */
+					<0 387 0x4>,    /* vm2 */
+					<0 388 0x4>,    /* vm3 */
+					<0 389 0x4>,    /* vm4 */
+					<0 390 0x4>,    /* MACsec non-secure intr */
+					<0 391 0x4>;    /* MACsec secure intr */
+			interrupt-names = "common", "vm0", "vm1", "vm2", "vm3", "vm4",
+					  "macsec-ns-irq", "macsec-s-irq";
+			resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
+				 <&bpmp TEGRA234_RESET_MGBE0_PCS>,
+				 <&bpmp TEGRA234_RESET_MGBE0_MACSEC>; /* MACsec non-secure reset */
+			reset-names = "mac", "pcs", "macsec_ns_rst";
+			clocks = <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
+				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
+				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
+				 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
+				 <&bpmp TEGRA234_CLK_MGBE0_TX>,
+				 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>,
+				 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
+				 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
+				 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
+				 <&bpmp TEGRA234_CLK_MGBE0_APP>,
+				 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
+				 <&bpmp TEGRA234_CLK_MGBE0_MACSEC>,
+				 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>;
+			clock-names = "rx-input-m", "rx-pcs-m", "rx-pcs-input",
+				      "rx-pcs", "tx", "tx-pcs", "mac-divider",
+				      "mac", "eee-pcs", "mgbe", "ptp-ref",
+				      "mgbe_macsec", "rx-input";
+			interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD>,
+					<&mc TEGRA234_MEMORY_CLIENT_MGBEAWR>;
+			nvidia,vm-irq-config = <&mgbe_vm_irq_config>;
+			nvidia,num-dma-chans = <10>;
+			nvidia,dma-chans = <0 1 2 3 4 5 6 7 8 9>;
+			nvidia,num-mtl-queues = <10>;
+			nvidia,mtl-queues = <0 1 2 3 4 5 6 7 8 9>;
+			nvidia,tc-mapping = <0 1 2 3 4 5 6 7 0 1>;
+			/* Residual Queue can be any valid queue except RxQ0 */
+			nvidia,residual-queue = <1>;
+			nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2 2 2>;
+			nvidia,tx-queue-prio = <0 1 2 3 4 5 6 7 0 0>;
+			nvidia,rx-queue-prio = <0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80 0x0 0x0>;
+			nvidia,dcs-enable = <0x1>;
+			nvidia,macsec-enable = <0>;
+			nvidia,rx_riwt = <512>;
+			nvidia,rx_frames = <64>;
+			nvidia,tx_usecs = <256>;
+			nvidia,tx_frames = <16>;
+			nvidia,promisc_mode = <1>;
+			nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
+			nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
+			nvidia,ptp_ref_clock_speed = <312500000>;
+			nvidia,instance_id = <0>; /* MGBE0 instance */
+			nvidia,ptp-rx-queue = <3>;
+			nvidia,dma_rx_ring_sz = <4096>;
+			nvidia,dma_tx_ring_sz = <4096>;
+			dma-coherent;
+		};
+
+		host1x@13e00000 {
+			interrupt-parent = <&gic>;
+
+			ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>,
+				 <0x0 0x24700000 0x0 0x24700000 0x0 0x00080000>;
+		};
+
+		spi@3270000 {
+			dma-names = "rx", "tx";
+			dma-coherent;
+			iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>;
+			assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
+					   <&bpmp TEGRA234_CLK_QSPI0_PM>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>,
+						 <&bpmp TEGRA234_CLK_QSPI0_2X_PM>;
+			assigned-clock-rates = <199999998 99999999>;
+		};
+
+		hardware-timestamp@3aa0000 {
+			status = "disabled";
+		};
+
+		hardware-timestamp@c1e0000 {
+			status = "disabled";
+		};
+
+		i2c@3160000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+			dma-coherent;
+		};
+
+		i2c@3180000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+			dma-coherent;
+		};
+
+		i2c@3190000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+			dma-coherent;
+		};
+
+		i2c@31b0000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+			dma-coherent;
+		};
+
+		i2c@31c0000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+			dma-coherent;
+		};
+
+		i2c@31e0000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+			dma-coherent;
+		};
+
+		i2c@c240000 {
+			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+			dma-coherent;
+		};
+
+		i2c@c250000 {
+			nvidia,hw-instance-id = <0x7>;
+			iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+			dma-coherent;
+		};
+
+		pwm@3280000 {
+			compatible = "nvidia,tegra234-pwm",
+				     "nvidia,tegra194-pwm";
+		};
+
+		phy@3e00000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L0_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID0>;
+		};
+
+		phy@3e10000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L1_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID1>;
+		};
+
+		phy@3e20000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L2_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID2>;
+		};
+
+		phy@3e30000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L3_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID3>;
+		};
+
+		phy@3e40000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L4_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID4>;
+		};
+
+		phy@3e50000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L5_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID5>;
+		};
+
+		phy@3e60000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L6_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID6>;
+		};
+
+		phy@3e70000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L7_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID7>;
+		};
+
+		phy@3e90000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L0_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID8>;
+		};
+
+		phy@3ea0000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L1_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID9>;
+		};
+
+		phy@3eb0000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L2_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID10>;
+		};
+
+		phy@3ec0000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L3_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID11>;
+		};
+
+		phy@3ed0000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L4_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID12>;
+		};
+
+		phy@3ee0000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L5_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID13>;
+		};
+
+		phy@3ef0000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L6_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID14>;
+		};
+
+		phy@3f00000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L7_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID15>;
+		};
+
+		phy@3f20000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L0_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID16>;
+		};
+
+		phy@3f30000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L1_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID17>;
+		};
+
+		phy@3f40000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L2_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID18>;
+		};
+
+		phy@3f50000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L3_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID19>;
+		};
+
+		phy@3f60000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L4_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID20>;
+		};
+
+		phy@3f70000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L5_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID21>;
+		};
+
+		phy@3f80000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L6_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID22>;
+		};
+
+		phy@3f90000 {
+			interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L7_P2U IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "intr";
+
+			nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID23>;
+		};
+
+		mmc@3460000 {
+			mmc-ddr-1_8v;
+			mmc-hs200-1_8v;
+			mmc-hs400-1_8v;
+			mmc-hs400-enhanced-strobe;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+		};
+	};
+
+	cpus {
+		idle-states {
+			entry-method = "psci";
+
+			C7: c7 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x40000007>;
+				min-residency-us = <30000>;
+				wakeup-latency-us = <5000>;
+				idle-state-name = "Core powergate";
+				status = "disabled";
+			};
+		};
+
+		cpu@0 {
+			cpu-idle-states = <&C7>;
+		};
+
+		cpu@100 {
+			cpu-idle-states = <&C7>;
+		};
+
+		cpu@200 {
+			cpu-idle-states = <&C7>;
+		};
+
+		cpu@300 {
+			cpu-idle-states = <&C7>;
+		};
+
+		cpu@10000 {
+			cpu-idle-states = <&C7>;
+		};
+
+		cpu@10100 {
+			cpu-idle-states = <&C7>;
+		};
+
+		cpu@10200 {
+			cpu-idle-states = <&C7>;
+		};
+
+		cpu@10300 {
+			cpu-idle-states = <&C7>;
+		};
+
+		cpu@20000 {
+			cpu-idle-states = <&C7>;
+		};
+
+		cpu@20100 {
+			cpu-idle-states = <&C7>;
+		};
+
+		cpu@20200 {
+			cpu-idle-states = <&C7>;
+		};
+
+		cpu@20300 {
+			cpu-idle-states = <&C7>;
+		};
+	};
+
+	mgbe_vm_irq_config: mgbe-vm-irq-config {
+		nvidia,num-vm-irqs = <5>;
+		vm_irq1 {
+			nvidia,num-vm-channels = <2>;
+			nvidia,vm-channels = <0 1>;
+			nvidia,vm-num = <0>;
+			nvidia,vm-irq-id = <0>;
+		};
+		vm_irq2 {
+			nvidia,num-vm-channels = <2>;
+			nvidia,vm-channels = <2 3>;
+			nvidia,vm-num = <1>;
+			nvidia,vm-irq-id = <1>;
+		};
+		vm_irq3 {
+			nvidia,num-vm-channels = <2>;
+			nvidia,vm-channels = <4 5>;
+			nvidia,vm-num = <2>;
+			nvidia,vm-irq-id = <2>;
+		};
+		vm_irq4 {
+			nvidia,num-vm-channels = <2>;
+			nvidia,vm-channels = <6 7>;
+			nvidia,vm-num = <3>;
+			nvidia,vm-irq-id = <3>;
+		};
+		vm_irq5 {
+			nvidia,num-vm-channels = <2>;
+			nvidia,vm-channels = <8 9>;
+			nvidia,vm-num = <4>;
+			nvidia,vm-irq-id = <4>;
+		};
+	};
+
+	eqos_vm_irq_config: vm-irq-config {
+		nvidia,num-vm-irqs = <4>;
+		vm_irq1 {
+			nvidia,num-vm-channels = <2>;
+			nvidia,vm-channels = <0 1>;
+			nvidia,vm-num = <0>;
+			nvidia,vm-irq-id = <0>;
+		};
+		vm_irq2 {
+			nvidia,num-vm-channels = <2>;
+			nvidia,vm-channels = <2 3>;
+			nvidia,vm-num = <1>;
+			nvidia,vm-irq-id = <1>;
+		};
+		vm_irq3 {
+			nvidia,num-vm-channels = <2>;
+			nvidia,vm-channels = <4 5>;
+			nvidia,vm-num = <2>;
+			nvidia,vm-irq-id = <2>;
+		};
+		vm_irq4 {
+			nvidia,num-vm-channels = <2>;
+			nvidia,vm-channels = <6 7>;
+			nvidia,vm-num = <3>;
+			nvidia,vm-irq-id = <3>;
+		};
+	};
+};

nv-soc/tegra234-overlay.dtsi

@@ -1,8 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include "tegra234-base-overlay.dtsi"
 #include "tegra234-soc-overlay.dtsi"
+#include "tegra234-soc-prod-overlay.dtsi"
 #include "tegra234-soc-display-overlay.dtsi"
 
 / {

nv-soc/tegra234-soc-audio-dai-links.dtsi

@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2019-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/ {
+	tegra_sound: sound {
+		/* mixer-controls node provide controls to override PCM params */
+		mixer-controls {
+			compatible = "nvidia,tegra234-mixer-control";
+			status = "okay";
+		};
+	};
+};

nv-soc/tegra234-soc-camera.dtsi

@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2025, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/*
+ * tegra234-soc-camera.dtsi: Camera RTCPU DTSI file.
+ */
+
+
+#include <dt-bindings/mailbox/tegra186-hsp.h>
+#include <dt-bindings/interrupt/tegra234-irq.h>
+#include <dt-bindings/power/tegra234-powergate.h>
+#include <dt-bindings/memory/tegra234-mc.h>
+
+/ {
+	aliases { /* RCE is the Camera RTCPU */
+		tegra-camera-rtcpu = "/rtcpu@bc00000";
+	};
+
+	bus@0 {
+		host1x@13e00000 {
+			vi0: vi0@15c00000 {
+				compatible = "nvidia,tegra234-vi";
+				clocks = <&bpmp TEGRA234_CLK_VI>;
+				clock-names = "vi";
+				nvidia,vi-falcon-device = <&vi0_thi>;
+				resets = <&bpmp TEGRA234_RESET_VI>;
+				reset-names = "vi0";
+				iommus = <&smmu_iso TEGRA234_SID_ISO_VI>;
+				interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIW &emc>;
+				interconnect-names = "write";
+				dma-noncoherent;
+				status = "okay";
+			};
+
+			vi0_thi: vi0-thi@15f00000 {
+				compatible = "nvidia,tegra234-vi-thi";
+				resets = <&bpmp TEGRA234_RESET_VI>;
+				reset-names = "vi0_thi";
+				iommus = <&smmu_iso TEGRA234_SID_ISO_VI>;
+				dma-noncoherent;
+				interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2FALR &emc>,
+						<&mc TEGRA234_MEMORY_CLIENT_VI2FALW &emc>;
+				interconnect-names = "dma-mem", "write";
+				status = "okay";
+			};
+
+			vi1: vi1@14c00000 {
+				compatible = "nvidia,tegra234-vi";
+				clocks = <&bpmp TEGRA234_CLK_VI>;
+				clock-names = "vi";
+				nvidia,vi-falcon-device = <&vi1_thi>;
+				resets = <&bpmp TEGRA234_RESET_VI2>;
+				reset-names = "vi1";
+				iommus = <&smmu_iso TEGRA234_SID_ISO_VI2>;
+				interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2W &emc>;
+				interconnect-names = "write";
+				dma-noncoherent;
+				status = "okay";
+			};
+
+			vi1_thi: vi1-thi@14f00000 {
+				compatible = "nvidia,tegra234-vi-thi";
+				resets = <&bpmp TEGRA234_RESET_VI2>;
+				reset-names = "vi1_thi";
+				iommus = <&smmu_iso TEGRA234_SID_ISO_VI2>;
+				dma-noncoherent;
+				interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIFALR &emc>,
+						<&mc TEGRA234_MEMORY_CLIENT_VIFALW &emc>;
+				interconnect-names = "dma-mem", "write";
+				status = "okay";
+			};
+
+			isp: isp@14800000 {
+				compatible = "nvidia,tegra194-isp";
+				reg = <0x0 0x14800000 0x0 0x00010000>;
+
+				resets = <&bpmp TEGRA234_RESET_ISP>;
+				reset-names = "isp";
+				clocks = <&bpmp TEGRA234_CLK_ISP>;
+				clock-names = "isp";
+				nvidia,isp-falcon-device = <&isp_thi>;
+
+				iommus = <&smmu_niso1 TEGRA234_SID_ISP>;
+				dma-coherent;
+				status = "okay";
+			};
+
+			isp_thi: isp-thi@14b00000 {
+				compatible = "nvidia,tegra194-isp-thi";
+				resets = <&bpmp TEGRA234_RESET_ISP>;
+				iommus = <&smmu_niso1 TEGRA234_SID_ISP>;
+				dma-coherent;
+				status = "okay";
+			};
+
+			nvcsi: nvcsi@15a00000 {
+				compatible = "nvidia,tegra194-nvcsi";
+				resets = <&bpmp TEGRA234_RESET_NVCSI>;
+				reset-names = "nvcsi";
+				clocks = <&bpmp TEGRA234_CLK_NVCSI>;
+				clock-names = "nvcsi";
+				status = "okay";
+			};
+		};
+	};
+
+	tegra_rce: rtcpu@bc00000 {
+		compatible = "nvidia,tegra194-rce";
+
+		nvidia,cpu-name = "rce";
+
+		reg =	<0 0xbc00000 0 0x1000>,   /* RCE EVP (RCE_ATCM_EVP) */
+			<0 0xb9f0000 0 0x40000>,  /* RCE PM */
+			<0 0xb840000 0 0x10000>,
+			<0 0xb850000 0 0x10000>;
+
+		reg-names = "rce-evp", "rce-pm",
+				"ast-cpu", "ast-dma";
+
+		clocks =
+			<&bpmp TEGRA234_CLK_RCE_CPU_NIC>,
+			<&bpmp TEGRA234_CLK_RCE_NIC>,
+			<&bpmp TEGRA234_CLK_RCE_CPU>;
+		clock-names = "rce-cpu-nic", "rce-nic", "rce-cpu";
+
+		nvidia,clock-rates =
+			<115200000 601600000>,
+			<115200000 601600000>,
+			<115200000 601600000>;
+
+		resets = <&bpmp TEGRA234_RESET_RCE_ALL>;
+		reset-names = "rce-all";
+
+		interrupts = <GIC_SPI TEGRA234_IRQ_RCE_WDT_REMOTE IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "wdt-remote";
+
+		iommus = <&smmu_niso0 TEGRA234_SID_RCE>;
+		memory-region = <&rce_resv>;
+		dma-coherent;
+
+		/* Memory bandwidth in kB/s during boot */
+		nvidia,test-bw = <2400000>;
+
+		nvidia,trace = <&rtcpu_trace 4 0x70100000 0x100000>;
+		nvidia,ivc-channels = <&camera_ivc_channels 2 0x90000000 0x10000>;
+
+		interconnects = <&mc TEGRA234_MEMORY_CLIENT_RCER &emc>,
+				<&mc TEGRA234_MEMORY_CLIENT_RCEW &emc>;
+		interconnect-names = "dma-mem", "write";
+
+		nvidia,autosuspend-delay-ms = <5000>;
+		status = "okay";
+
+		hsp-vm1 {
+			compatible = "nvidia,tegra-camrtc-hsp-vm";
+			mboxes =
+				<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(0)>,
+				<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(1)>,
+				<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 0>;
+			mbox-names = "vm-tx", "vm-rx", "vm-ss";
+			status = "okay";
+		};
+
+		hsp-vm2 {
+			compatible = "nvidia,tegra-camrtc-hsp-vm";
+			mboxes =
+				<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(2)>,
+				<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(3)>,
+				<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 1>;
+			mbox-names = "vm-tx", "vm-rx", "vm-ss";
+			status = "disabled";
+		};
+	};
+
+	camera_ivc_channels: camera-ivc-channels {
+		echo@0 {
+			compatible = "nvidia,tegra186-camera-ivc-protocol-echo";
+			nvidia,service = "echo";
+			nvidia,version = <0>;
+			nvidia,group = <1>;
+			nvidia,frame-count = <16>;
+			nvidia,frame-size = <64>;
+		};
+		dbg@1 {
+			/* This is raw channel exposed as device */
+			compatible = "nvidia,tegra186-camera-ivc-protocol-dbg";
+			nvidia,service = "debug";
+			nvidia,version = <0>;
+			nvidia,group = <1>;
+			nvidia,frame-count = <1>;
+			nvidia,frame-size = <512>;
+		};
+		dbg@2 {
+			/* This is exposed in debugfs */
+			compatible = "nvidia,tegra186-camera-ivc-protocol-debug";
+			nvidia,service = "debug";
+			nvidia,version = <0>;
+			nvidia,group = <1>;
+			nvidia,frame-count = <1>;
+			nvidia,frame-size = <8192>;
+			nvidia,ivc-timeout = <50>;
+			nvidia,test-timeout = <5000>;
+			nvidia,mem-map = <&tegra_rce &vi0 &isp &vi1>;
+			/* Memory bandwidth in kB/s during tests */
+			nvidia,test-bw = <2400000>;
+		};
+		ivccontrol@3 {
+			compatible = "nvidia,tegra186-camera-ivc-protocol-capture-control";
+			nvidia,service = "capture-control";
+			nvidia,version = <0>;
+			nvidia,group = <1>;
+			nvidia,frame-count = <64>;
+			nvidia,frame-size = <320>;
+		};
+		ivccapture@4 {
+			compatible = "nvidia,tegra186-camera-ivc-protocol-capture";
+			nvidia,service = "capture";
+			nvidia,version = <0>;
+			nvidia,group = <1>;
+			nvidia,frame-count = <512>;
+			nvidia,frame-size = <64>;
+		};
+		diag@5 {
+			compatible = "nvidia,tegra186-camera-diagnostics";
+			nvidia,service = "diag";
+			nvidia,version = <0>;
+			nvidia,group = <1>;
+			nvidia,frame-count = <1>;
+			nvidia,frame-size = <64>;
+		};
+	};
+
+	rtcpu_trace: tegra-rtcpu-trace {
+		nvidia,enable-printk;
+		nvidia,interval-ms = <50>;
+		nvidia,log-prefix = "[RCE]";
+	};
+
+	capture_vi: tegra-capture-vi {
+		compatible = "nvidia,tegra-camrtc-capture-vi";
+
+		nvidia,vi-devices = <&vi0 &vi1>;
+		nvidia,vi-mapping-size = <6>;
+		nvidia,vi-mapping =
+			<0 0>,
+			<1 0>,
+			<2 1>,
+			<3 1>,
+			<4 0>,
+			<5 1>;
+		nvidia,vi-mapping-names = "csi-stream-id", "vi-unit-id";
+		nvidia,vi-max-channels = <72>;
+	};
+
+	capture_isp: tegra-capture-isp {
+		compatible = "nvidia,tegra-camrtc-capture-isp";
+		nvidia,isp-devices = <&isp>;
+		nvidia,isp-max-channels = <16>;
+	};
+
+	reserved-memory {
+		rce_resv: rce-reservation {
+			iommu-addresses = <&tegra_rce 0x0 0x00000000 0x00000000 0xA0000000>,
+					  <&tegra_rce 0x0 0xC0000000 0xffffffff 0x3fffffff>;
+		};
+
+		camdbg_reserved: camdbg_carveout {
+			compatible = "nvidia,camdbg_carveout";
+			size = <0 0x3200000>;
+			alignment = <0 0x100000>;
+			alloc-ranges = <0x1 0 0x1 0>;
+			status = "disabled";
+		};
+	};
+};

nv-soc/tegra234-soc-display-overlay.dtsi

@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include <dt-bindings/power/tegra234-powergate.h>
+
+/ {
+	reserved-memory {
+		fb0_reserved: framebuffer@0,0 {
+			compatible = "framebuffer";
+			reg = <0x00 0x00 0x00 0x00>;
+			iommu-addresses = <&nvdisplay 0x0 0x0 0x0 0x0>;
+			no-map;
+			status = "disabled";
+		};
+	};
+
+	chosen {
+		framebuffer {
+			compatible = "simple-framebuffer";
+			status = "disabled";
+			memory-region = <&fb0_reserved>;
+			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
+			clocks = <&bpmp TEGRA234_CLK_HUB>,
+				 <&bpmp TEGRA234_CLK_DISP>,
+				 <&bpmp TEGRA234_CLK_NVDISPLAY_P0>,
+				 <&bpmp TEGRA234_CLK_NVDISPLAY_P1>,
+				 <&bpmp TEGRA234_CLK_DPAUX>,
+				 <&bpmp TEGRA234_CLK_FUSE>,
+				 <&bpmp TEGRA234_CLK_DSIPLL_VCO>,
+				 <&bpmp TEGRA234_CLK_DSIPLL_CLKOUTPN>,
+				 <&bpmp TEGRA234_CLK_DSIPLL_CLKOUTA>,
+				 <&bpmp TEGRA234_CLK_SPPLL0_VCO>,
+				 <&bpmp TEGRA234_CLK_SPPLL0_CLKOUTPN>,
+				 <&bpmp TEGRA234_CLK_SPPLL0_CLKOUTA>,
+				 <&bpmp TEGRA234_CLK_SPPLL0_CLKOUTB>,
+				 <&bpmp TEGRA234_CLK_SPPLL0_DIV10>,
+				 <&bpmp TEGRA234_CLK_SPPLL0_DIV25>,
+				 <&bpmp TEGRA234_CLK_SPPLL0_DIV27PN>,
+				 <&bpmp TEGRA234_CLK_SPPLL1_VCO>,
+				 <&bpmp TEGRA234_CLK_SPPLL1_CLKOUTPN>,
+				 <&bpmp TEGRA234_CLK_SPPLL1_DIV27PN>,
+				 <&bpmp TEGRA234_CLK_VPLL0_REF>,
+				 <&bpmp TEGRA234_CLK_VPLL0>,
+				 <&bpmp TEGRA234_CLK_VPLL1>,
+				 <&bpmp TEGRA234_CLK_NVDISPLAY_P0_REF>,
+				 <&bpmp TEGRA234_CLK_RG0>,
+				 <&bpmp TEGRA234_CLK_RG1>,
+				 <&bpmp TEGRA234_CLK_DISPPLL>,
+				 <&bpmp TEGRA234_CLK_DISPHUBPLL>,
+				 <&bpmp TEGRA234_CLK_DSI_LP>,
+				 <&bpmp TEGRA234_CLK_DSI_CORE>,
+				 <&bpmp TEGRA234_CLK_DSI_PIXEL>,
+				 <&bpmp TEGRA234_CLK_PRE_SOR0>,
+				 <&bpmp TEGRA234_CLK_PRE_SOR1>,
+				 <&bpmp TEGRA234_CLK_DP_LINK_REF>,
+				 <&bpmp TEGRA234_CLK_SOR_LINKA_INPUT>,
+				 <&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO>,
+				 <&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO_M>,
+				 <&bpmp TEGRA234_CLK_RG0_M>,
+				 <&bpmp TEGRA234_CLK_RG1_M>,
+				 <&bpmp TEGRA234_CLK_SOR0_M>,
+				 <&bpmp TEGRA234_CLK_SOR1_M>,
+				 <&bpmp TEGRA234_CLK_PLLHUB>,
+				 <&bpmp TEGRA234_CLK_SOR0>,
+				 <&bpmp TEGRA234_CLK_SOR1>,
+				 <&bpmp TEGRA234_CLK_SOR_PAD_INPUT>,
+				 <&bpmp TEGRA234_CLK_PRE_SF0>,
+				 <&bpmp TEGRA234_CLK_SF0>,
+				 <&bpmp TEGRA234_CLK_SF1>,
+				 <&bpmp TEGRA234_CLK_DSI_PAD_INPUT>,
+				 <&bpmp TEGRA234_CLK_PRE_SOR0_REF>,
+				 <&bpmp TEGRA234_CLK_PRE_SOR1_REF>,
+				 <&bpmp TEGRA234_CLK_SOR0_PLL_REF>,
+				 <&bpmp TEGRA234_CLK_SOR1_PLL_REF>,
+				 <&bpmp TEGRA234_CLK_SOR0_REF>,
+				 <&bpmp TEGRA234_CLK_SOR1_REF>,
+				 <&bpmp TEGRA234_CLK_OSC>,
+				 <&bpmp TEGRA234_CLK_DSC>,
+				 <&bpmp TEGRA234_CLK_MAUD>,
+				 <&bpmp TEGRA234_CLK_AZA_2XBIT>,
+				 <&bpmp TEGRA234_CLK_AZA_BIT>,
+				 <&bpmp TEGRA234_CLK_MIPI_CAL>,
+				 <&bpmp TEGRA234_CLK_UART_FST_MIPI_CAL>,
+				 <&bpmp TEGRA234_CLK_SOR0_DIV>;
+			width  = <0>;
+			height = <0>;
+			stride = <0>;
+			format = "x8b8g8r8";
+		};
+	};
+
+	dce@d800000 {
+		compatible = "nvidia,tegra234-dce";
+		reg = <0x0 0x0d800000 0x0 0x00800000>;
+		interrupts =
+			<0 376 0x4>,
+			<0 377 0x4>;
+		interrupt-names = "wdt-remote",
+			"dce-sm0";
+		iommus = <&smmu_niso0 TEGRA234_SID_DCE>;
+		status = "disabled";
+	};
+
+	nvdisplay: display@13800000 {
+		compatible = "nvidia,tegra234-display";
+		power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
+		nvidia,num-dpaux-instance = <1>;
+		reg-names = "nvdisplay", "dpaux0", "hdacodec", "mipical";
+		reg = <0x0 0x13800000 0x0 0xEFFFF    /* nvdisplay */
+			0x0 0x155C0000 0x0 0xFFFF     /* dpaux0 */
+			0x0 0x0242c000 0x0 0x1000     /* hdacodec */
+			0x0 0x03990000 0x0 0x10000>;  /* mipical */
+		interrupt-names = "nvdisplay", "dpaux0", "hdacodec";
+		interrupts = <0 416 4
+			0 419 4
+			0  61 4>;
+		nvidia,bpmp = <&bpmp>;
+		clocks = <&bpmp TEGRA234_CLK_HUB>,
+		       <&bpmp TEGRA234_CLK_DISP>,
+		       <&bpmp TEGRA234_CLK_NVDISPLAY_P0>,
+		       <&bpmp TEGRA234_CLK_NVDISPLAY_P1>,
+		       <&bpmp TEGRA234_CLK_DPAUX>,
+		       <&bpmp TEGRA234_CLK_FUSE>,
+		       <&bpmp TEGRA234_CLK_DSIPLL_VCO>,
+		       <&bpmp TEGRA234_CLK_DSIPLL_CLKOUTPN>,
+		       <&bpmp TEGRA234_CLK_DSIPLL_CLKOUTA>,
+		       <&bpmp TEGRA234_CLK_SPPLL0_VCO>,
+		       <&bpmp TEGRA234_CLK_SPPLL0_CLKOUTPN>,
+		       <&bpmp TEGRA234_CLK_SPPLL0_CLKOUTA>,
+		       <&bpmp TEGRA234_CLK_SPPLL0_CLKOUTB>,
+		       <&bpmp TEGRA234_CLK_SPPLL0_DIV10>,
+		       <&bpmp TEGRA234_CLK_SPPLL0_DIV25>,
+		       <&bpmp TEGRA234_CLK_SPPLL0_DIV27PN>,
+		       <&bpmp TEGRA234_CLK_SPPLL1_VCO>,
+		       <&bpmp TEGRA234_CLK_SPPLL1_CLKOUTPN>,
+		       <&bpmp TEGRA234_CLK_SPPLL1_DIV27PN>,
+		       <&bpmp TEGRA234_CLK_VPLL0_REF>,
+		       <&bpmp TEGRA234_CLK_VPLL0>,
+		       <&bpmp TEGRA234_CLK_VPLL1>,
+		       <&bpmp TEGRA234_CLK_NVDISPLAY_P0_REF>,
+		       <&bpmp TEGRA234_CLK_RG0>,
+		       <&bpmp TEGRA234_CLK_RG1>,
+		       <&bpmp TEGRA234_CLK_DISPPLL>,
+		       <&bpmp TEGRA234_CLK_DISPHUBPLL>,
+		       <&bpmp TEGRA234_CLK_DSI_LP>,
+		       <&bpmp TEGRA234_CLK_DSI_CORE>,
+		       <&bpmp TEGRA234_CLK_DSI_PIXEL>,
+		       <&bpmp TEGRA234_CLK_PRE_SOR0>,
+		       <&bpmp TEGRA234_CLK_PRE_SOR1>,
+		       <&bpmp TEGRA234_CLK_DP_LINK_REF>,
+		       <&bpmp TEGRA234_CLK_SOR_LINKA_INPUT>,
+		       <&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO>,
+		       <&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO_M>,
+		       <&bpmp TEGRA234_CLK_RG0_M>,
+		       <&bpmp TEGRA234_CLK_RG1_M>,
+		       <&bpmp TEGRA234_CLK_SOR0_M>,
+		       <&bpmp TEGRA234_CLK_SOR1_M>,
+		       <&bpmp TEGRA234_CLK_PLLHUB>,
+		       <&bpmp TEGRA234_CLK_SOR0>,
+		       <&bpmp TEGRA234_CLK_SOR1>,
+		       <&bpmp TEGRA234_CLK_SOR_PAD_INPUT>,
+		       <&bpmp TEGRA234_CLK_PRE_SF0>,
+		       <&bpmp TEGRA234_CLK_SF0>,
+		       <&bpmp TEGRA234_CLK_SF1>,
+		       <&bpmp TEGRA234_CLK_DSI_PAD_INPUT>,
+		       <&bpmp TEGRA234_CLK_PRE_SOR0_REF>,
+		       <&bpmp TEGRA234_CLK_PRE_SOR1_REF>,
+		       <&bpmp TEGRA234_CLK_SOR0_PLL_REF>,
+		       <&bpmp TEGRA234_CLK_SOR1_PLL_REF>,
+		       <&bpmp TEGRA234_CLK_SOR0_REF>,
+		       <&bpmp TEGRA234_CLK_SOR1_REF>,
+		       <&bpmp TEGRA234_CLK_OSC>,
+		       <&bpmp TEGRA234_CLK_DSC>,
+		       <&bpmp TEGRA234_CLK_MAUD>,
+		       <&bpmp TEGRA234_CLK_AZA_2XBIT>,
+		       <&bpmp TEGRA234_CLK_AZA_BIT>,
+		       <&bpmp TEGRA234_CLK_MIPI_CAL>,
+		       <&bpmp TEGRA234_CLK_UART_FST_MIPI_CAL>,
+		       <&bpmp TEGRA234_CLK_SOR0_DIV>;
+		clock-names = "nvdisplayhub_clk",
+			"nvdisplay_disp_clk",
+			"nvdisplay_p0_clk",
+			"nvdisplay_p1_clk",
+			"dpaux0_clk",
+			"fuse_clk",
+			"dsipll_vco_clk",
+			"dsipll_clkoutpn_clk",
+			"dsipll_clkouta_clk",
+			"sppll0_vco_clk",
+			"sppll0_clkoutpn_clk",
+			"sppll0_clkouta_clk",
+			"sppll0_clkoutb_clk",
+			"sppll0_div10_clk",
+			"sppll0_div25_clk",
+			"sppll0_div27_clk",
+			"sppll1_vco_clk",
+			"sppll1_clkoutpn_clk",
+			"sppll1_div27_clk",
+			"vpll0_ref_clk",
+			"vpll0_clk",
+			"vpll1_clk",
+			"nvdisplay_p0_ref_clk",
+			"rg0_clk",
+			"rg1_clk",
+			"disppll_clk",
+			"disphubpll_clk",
+			"dsi_lp_clk",
+			"dsi_core_clk",
+			"dsi_pixel_clk",
+			"pre_sor0_clk",
+			"pre_sor1_clk",
+			"dp_link_ref_clk",
+			"sor_linka_input_clk",
+			"sor_linka_afifo_clk",
+			"sor_linka_afifo_m_clk",
+			"rg0_m_clk",
+			"rg1_m_clk",
+			"sor0_m_clk",
+			"sor1_m_clk",
+			"pllhub_clk",
+			"sor0_clk",
+			"sor1_clk",
+			"sor_pad_input_clk",
+			"pre_sf0_clk",
+			"sf0_clk",
+			"sf1_clk",
+			"dsi_pad_input_clk",
+			"pre_sor0_ref_clk",
+			"pre_sor1_ref_clk",
+			"sor0_ref_pll_clk",
+			"sor1_ref_pll_clk",
+			"sor0_ref_clk",
+			"sor1_ref_clk",
+			"osc_clk",
+			"dsc_clk",
+			"maud_clk",
+			"aza_2xbit_clk",
+			"aza_bit_clk",
+			"mipi_cal_clk",
+			"uart_fst_mipi_cal_clk",
+			"sor0_div_clk";
+		resets = <&bpmp TEGRA234_RESET_NVDISPLAY>,
+		       <&bpmp TEGRA234_RESET_DPAUX>,
+		       <&bpmp TEGRA234_RESET_DSI_CORE>,
+		       <&bpmp TEGRA234_RESET_MIPI_CAL>;
+		reset-names = "nvdisplay_reset",
+			"dpaux0_reset",
+			"dsi_core_reset",
+			"mipi_cal_reset";
+		hdcp_enabled;
+		status = "disabled";
+		memory-region = <&fb0_reserved>;
+		nvidia,disp-sw-soc-chip-id = <0x2350>;
+		interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR &emc>,
+			      <&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
+		interconnect-names = "dma-mem", "read-1";
+		iommus = <&smmu_iso TEGRA234_SID_ISO_NVDISPLAY>;
+		non-coherent;
+		nvdisplay-niso {
+			compatible = "nvidia,tegra234-display-niso";
+			iommus = <&smmu_niso0 TEGRA234_SID_NVDISPLAY>;
+			dma-coherent;
+		};
+	};
+};

nv-soc/tegra234-soc-prod-overlay.dtsi

@@ -0,0 +1,554 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/ {
+	bus@0 {
+		i2c@3160000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x0000009c 0x0000ffff 0x00000308              //i2c_i2c_hs_interface_timing_0_0
+						0 0x000000d4 0x000000ff 0x00000000              //i2c_i2c_interface_timing_2_0
+						0 0x000000d8 0x000000ff 0x00000000              //i2c_i2c_hs_interface_timing_2_0
+						0 0x000000dc 0x0000ffff 0x00000001              //i2c_i2c_mstr_data_capture_timing_0
+						0 0x000000e0 0x0000ffff 0x00000002>;            //i2c_i2c_slv_data_capture_timing_0
+				};
+				prod_c_fm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x003c0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_fmplus {
+					prod = <
+						0 0x0000006c 0xffff0000 0x00160000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_hs {
+					prod = <
+						0 0x0000006c 0xffffffff 0x00160002              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202              //i2c_i2c_interface_timing_1_0
+						0 0x000000a0 0x00ffffff 0x00090909>;            //i2c_i2c_hs_interface_timing_1_0
+				};
+				prod_c_sm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x004f0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000708              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x08080808>;            //i2c_i2c_interface_timing_1_0
+				};
+			};
+		};
+
+		i2c@3180000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x0000009c 0x0000ffff 0x00000308              //i2c_i2c_hs_interface_timing_0_0
+						0 0x000000d4 0x000000ff 0x00000000              //i2c_i2c_interface_timing_2_0
+						0 0x000000d8 0x000000ff 0x00000000              //i2c_i2c_hs_interface_timing_2_0
+						0 0x000000dc 0x0000ffff 0x00000001              //i2c_i2c_mstr_data_capture_timing_0
+						0 0x000000e0 0x0000ffff 0x00000002>;            //i2c_i2c_slv_data_capture_timing_0
+				};
+				prod_c_fm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x003c0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_fmplus {
+					prod = <
+						0 0x0000006c 0xffff0000 0x00160000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_hs {
+					prod = <
+						0 0x0000006c 0xffffffff 0x00160002              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202              //i2c_i2c_interface_timing_1_0
+						0 0x000000a0 0x00ffffff 0x00090909>;            //i2c_i2c_hs_interface_timing_1_0
+				};
+				prod_c_sm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x004f0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000708              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x08080808>;            //i2c_i2c_interface_timing_1_0
+				};
+			};
+		};
+
+		i2c@3190000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x0000009c 0x0000ffff 0x00000308              //i2c_i2c_hs_interface_timing_0_0
+						0 0x000000d4 0x000000ff 0x00000000              //i2c_i2c_interface_timing_2_0
+						0 0x000000d8 0x000000ff 0x00000000              //i2c_i2c_hs_interface_timing_2_0
+						0 0x000000dc 0x0000ffff 0x00000001              //i2c_i2c_mstr_data_capture_timing_0
+						0 0x000000e0 0x0000ffff 0x00000002>;            //i2c_i2c_slv_data_capture_timing_0
+				};
+				prod_c_fm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x003c0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_fmplus {
+					prod = <
+						0 0x0000006c 0xffff0000 0x00160000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_hs {
+					prod = <
+						0 0x0000006c 0xffffffff 0x00160002              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202              //i2c_i2c_interface_timing_1_0
+						0 0x000000a0 0x00ffffff 0x00090909>;            //i2c_i2c_hs_interface_timing_1_0
+				};
+				prod_c_sm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x004f0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000708              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x08080808>;            //i2c_i2c_interface_timing_1_0
+				};
+			};
+		};
+
+		i2c@31b0000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x0000009c 0x0000ffff 0x00000308              //i2c_i2c_hs_interface_timing_0_0
+						0 0x000000d4 0x000000ff 0x00000000              //i2c_i2c_interface_timing_2_0
+						0 0x000000d8 0x000000ff 0x00000000              //i2c_i2c_hs_interface_timing_2_0
+						0 0x000000dc 0x0000ffff 0x00000001              //i2c_i2c_mstr_data_capture_timing_0
+						0 0x000000e0 0x0000ffff 0x00000002>;            //i2c_i2c_slv_data_capture_timing_0
+				};
+				prod_c_fm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x003c0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_fmplus {
+					prod = <
+						0 0x0000006c 0xffff0000 0x00160000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_hs {
+					prod = <
+						0 0x0000006c 0xffffffff 0x00160002              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202              //i2c_i2c_interface_timing_1_0
+						0 0x000000a0 0x00ffffff 0x00090909>;            //i2c_i2c_hs_interface_timing_1_0
+				};
+				prod_c_sm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x004f0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000708              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x08080808>;            //i2c_i2c_interface_timing_1_0
+				};
+			};
+		};
+
+		i2c@31c0000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x0000009c 0x0000ffff 0x00000308              //i2c_i2c_hs_interface_timing_0_0
+						0 0x000000d4 0x000000ff 0x00000000              //i2c_i2c_interface_timing_2_0
+						0 0x000000d8 0x000000ff 0x00000000              //i2c_i2c_hs_interface_timing_2_0
+						0 0x000000dc 0x0000ffff 0x00000001              //i2c_i2c_mstr_data_capture_timing_0
+						0 0x000000e0 0x0000ffff 0x00000002>;            //i2c_i2c_slv_data_capture_timing_0
+				};
+				prod_c_fm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x003c0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_fmplus {
+					prod = <
+						0 0x0000006c 0xffff0000 0x00160000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_hs {
+					prod = <
+						0 0x0000006c 0xffffffff 0x00160002              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202              //i2c_i2c_interface_timing_1_0
+						0 0x000000a0 0x00ffffff 0x00090909>;            //i2c_i2c_hs_interface_timing_1_0
+				};
+				prod_c_sm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x004f0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000708              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x08080808>;            //i2c_i2c_interface_timing_1_0
+				};
+			};
+		};
+
+		i2c@31e0000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x0000009c 0x0000ffff 0x00000308              //i2c_i2c_hs_interface_timing_0_0
+						0 0x000000d4 0x000000ff 0x00000000              //i2c_i2c_interface_timing_2_0
+						0 0x000000d8 0x000000ff 0x00000000              //i2c_i2c_hs_interface_timing_2_0
+						0 0x000000dc 0x0000ffff 0x00000001              //i2c_i2c_mstr_data_capture_timing_0
+						0 0x000000e0 0x0000ffff 0x00000002>;            //i2c_i2c_slv_data_capture_timing_0
+				};
+				prod_c_fm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x003c0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_fmplus {
+					prod = <
+						0 0x0000006c 0xffff0000 0x00160000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_hs {
+					prod = <
+						0 0x0000006c 0xffffffff 0x00160002              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202              //i2c_i2c_interface_timing_1_0
+						0 0x000000a0 0x00ffffff 0x00090909>;            //i2c_i2c_hs_interface_timing_1_0
+				};
+				prod_c_sm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x004f0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000708              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x08080808>;            //i2c_i2c_interface_timing_1_0
+				};
+			};
+		};
+
+		i2c@c240000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x0000009c 0x0000ffff 0x00000308              //i2c_i2c_hs_interface_timing_0_0
+						0 0x000000d4 0x000000ff 0x00000000              //i2c_i2c_interface_timing_2_0
+						0 0x000000d8 0x000000ff 0x00000000              //i2c_i2c_hs_interface_timing_2_0
+						0 0x000000dc 0x0000ffff 0x00000001              //i2c_i2c_mstr_data_capture_timing_0
+						0 0x000000e0 0x0000ffff 0x00000002>;            //i2c_i2c_slv_data_capture_timing_0
+				};
+				prod_c_fm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x003c0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_fmplus {
+					prod = <
+						0 0x0000006c 0xffff0000 0x00160000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_hs {
+					prod = <
+						0 0x0000006c 0xffffffff 0x00160002              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202              //i2c_i2c_interface_timing_1_0
+						0 0x000000a0 0x00ffffff 0x00090909>;            //i2c_i2c_hs_interface_timing_1_0
+				};
+				prod_c_sm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x004f0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000708              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x08080808>;            //i2c_i2c_interface_timing_1_0
+				};
+			};
+		};
+
+		i2c@c250000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x0000009c 0x0000ffff 0x00000308              //i2c_i2c_hs_interface_timing_0_0
+						0 0x000000d4 0x000000ff 0x00000000              //i2c_i2c_interface_timing_2_0
+						0 0x000000d8 0x000000ff 0x00000000              //i2c_i2c_hs_interface_timing_2_0
+						0 0x000000dc 0x0000ffff 0x00000001              //i2c_i2c_mstr_data_capture_timing_0
+						0 0x000000e0 0x0000ffff 0x00000002>;            //i2c_i2c_slv_data_capture_timing_0
+				};
+				prod_c_fm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x003c0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_fmplus {
+					prod = <
+						0 0x0000006c 0xffff0000 0x00160000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202>;            //i2c_i2c_interface_timing_1_0
+				};
+				prod_c_hs {
+					prod = <
+						0 0x0000006c 0xffffffff 0x00160002              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000202              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x02020202              //i2c_i2c_interface_timing_1_0
+						0 0x000000a0 0x00ffffff 0x00090909>;            //i2c_i2c_hs_interface_timing_1_0
+				};
+				prod_c_sm {
+					prod = <
+						0 0x0000006c 0xffff0000 0x004f0000              //i2c_i2c_clk_divisor_register_0
+						0 0x00000094 0x0000ffff 0x00000708              //i2c_i2c_interface_timing_0_0
+						0 0x00000098 0xffffffff 0x08080808>;            //i2c_i2c_interface_timing_1_0
+				};
+			};
+		};
+
+		mmc@3400000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_1_8v {
+					prod = <
+						0 0x000001e0 0x01f00000 0x00800000>;            //SDMMCA_SDMEMCOMPPADCTRL_0
+				};
+				prod_c_3_3v {
+					prod = <
+						0 0x000001e0 0x01f00000 0x00900000>;            //SDMMCA_SDMEMCOMPPADCTRL_0
+				};
+				prod {
+					prod = <
+						0 0x00000028 0x00000022 0x00000002              //SDMMCA_POWER_CONTROL_HOST_0
+						0 0x00000100 0x1fff006a 0x0e080020              //SDMMCA_VENDOR_CLOCK_CNTRL_0
+						0 0x00000128 0x42000000 0x00000000              //SDMMCA_VENDOR_MISC_CNTRL2_0
+						0 0x000001c0 0x00001fc0 0x00000040              //SDMMCA_VENDOR_TUNING_CNTRL0_0
+						0 0x000001e0 0x0001f000 0x00009000              //SDMMCA_SDMEMCOMPPADCTRL_0
+						0 0x000001e4 0x20000000 0x20000000>;            //SDMMCA_AUTO_CAL_CONFIG_0
+				};
+				prod_c_ddr50 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00040000>;            //SDMMCA_AUTO_CMD12_ERR_STATUS_0
+				};
+				prod_c_ddr52 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00040000>;            //SDMMCA_AUTO_CMD12_ERR_STATUS_0
+				};
+				prod_c_hs200 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00030000              //SDMMCA_AUTO_CMD12_ERR_STATUS_0
+						0 0x000001c0 0x0000e000 0x00004000>;            //SDMMCA_VENDOR_TUNING_CNTRL0_0
+				};
+				prod_c_nopwrsave {
+					prod = <
+						0 0x00000100 0x00000001 0x00000001              //SDMMCA_VENDOR_CLOCK_CNTRL_0
+						0 0x000001ac 0x00000004 0x00000000>;            //SDMMCA_VENDOR_IO_TRIM_CNTRL_0
+				};
+				prod_c_pwrsave {
+					prod = <
+						0 0x00000100 0x00000001 0x00000000              //SDMMCA_VENDOR_CLOCK_CNTRL_0
+						0 0x000001ac 0x00000004 0x00000004>;            //SDMMCA_VENDOR_IO_TRIM_CNTRL_0
+				};
+				prod_c_sdr104 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00030000              //SDMMCA_AUTO_CMD12_ERR_STATUS_0
+						0 0x000001c0 0x0000e000 0x00004000>;            //SDMMCA_VENDOR_TUNING_CNTRL0_0
+				};
+				prod_c_sdr12 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00000000>;            //SDMMCA_AUTO_CMD12_ERR_STATUS_0
+				};
+				prod_c_sdr25 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00010000>;            //SDMMCA_AUTO_CMD12_ERR_STATUS_0
+				};
+				prod_c_sdr50 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00020000              //SDMMCA_AUTO_CMD12_ERR_STATUS_0
+						0 0x000001c0 0x0000e000 0x00008000>;            //SDMMCA_VENDOR_TUNING_CNTRL0_0
+				};
+			};
+		};
+		mmc@3460000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x00000004 0x00000fff 0x00000200              //sdmmcab_block_size_block_count_0
+						0 0x00000028 0x00000020 0x00000020              //sdmmcab_power_control_host_0
+						0 0x00000100 0x1f00006a 0x12000020              //sdmmcab_vendor_clock_cntrl_0
+						0 0x00000128 0x43000000 0x00000000              //sdmmcab_vendor_misc_cntrl2_0
+						0 0x000001c0 0x00001fc0 0x00000040              //sdmmcab_vendor_tuning_cntrl0_0
+						0 0x000001e0 0x01f1f000 0x00a0a000              //sdmmcab_sdmemcomppadctrl_0
+						0 0x000001e4 0x20000000 0x20000000>;            //sdmmcab_auto_cal_config_0
+				};
+				prod_c_ddr50 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00040000              //sdmmcab_auto_cmd12_err_status_0
+						0 0x00000100 0x1fff0000 0x12070000>;            //sdmmcab_vendor_clock_cntrl_0
+				};
+				prod_c_ddr52 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00040000              //sdmmcab_auto_cmd12_err_status_0
+						0 0x00000100 0x1fff0000 0x12070000>;            //sdmmcab_vendor_clock_cntrl_0
+				};
+				prod_c_hs200 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00030000              //sdmmcab_auto_cmd12_err_status_0
+						0 0x000001c0 0x0000e000 0x00004000>;            //sdmmcab_vendor_tuning_cntrl0_0
+				};
+				prod_c_hs400 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00050000              //sdmmcab_auto_cmd12_err_status_0
+						0 0x00000100 0x00000008 0x00000008              //sdmmcab_vendor_clock_cntrl_0
+						0 0x0000010c 0x00003f00 0x00002800              //sdmmcab_vendor_cap_overrides_0
+						0 0x000001c0 0x0000e000 0x00004000>;            //sdmmcab_vendor_tuning_cntrl0_0
+				};
+				prod_c_nopwrsave {
+					prod = <
+						0 0x00000100 0x00000001 0x00000001              //sdmmcab_vendor_clock_cntrl_0
+						0 0x000001ac 0x00000004 0x00000000>;            //sdmmcab_vendor_io_trim_cntrl_0
+				};
+				prod_c_pwrsave {
+					prod = <
+						0 0x00000100 0x00000001 0x00000000              //sdmmcab_vendor_clock_cntrl_0
+						0 0x000001ac 0x00000004 0x00000004>;            //sdmmcab_vendor_io_trim_cntrl_0
+				};
+				prod_c_sdr12 {
+					prod = <
+						0 0x00000100 0x1fff0000 0x12070000>;            //sdmmcab_vendor_clock_cntrl_0
+				};
+				prod_c_sdr25 {
+					prod = <
+						0 0x00000100 0x1fff0000 0x12070000>;            //sdmmcab_vendor_clock_cntrl_0
+				};
+				prod_c_sdr50 {
+					prod = <
+						0 0x0000003c 0x00070000 0x00020000>;            //sdmmcab_auto_cmd12_err_status_0
+				};
+			};
+		};
+
+		spi@3210000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x00000194 0x80000000 0x00000000>;            //spi_misc_0
+				};
+			};
+		};
+
+		spi@3230000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x00000194 0x80000000 0x00000000>;            //spi_misc_0
+				};
+			};
+		};
+
+		spi@3240000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x00000194 0x80000000 0x00000000>;            //spi_misc_0
+				};
+			};
+		};
+
+		spi@3250000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x00000194 0x80000000 0x00000000>;            //spi_misc_0
+				};
+			};
+		};
+
+		spi@3270000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_nonsecure {
+					prod = <
+						0 0x0000f000 0x0000003f 0x00000012>;            //qspi_secure_axi_ctl_0
+				};
+				prod_c_nopwrsave {
+					prod = <
+						0 0x00000194 0x80000000 0x80000000              //qspi_misc_0
+						0 0x000001ec 0x00000002 0x00000000              //qspi_qspi_comp_control_0
+						0 0x000001fc 0x00000002 0x00000000>;            //qspi_io_trim_cntrl_0
+				};
+				prod_c_pwrsave {
+					prod = <
+						0 0x00000194 0x80000000 0x00000000              //qspi_misc_0
+						0 0x000001ec 0x00000002 0x00000002              //qspi_qspi_comp_control_0
+						0 0x000001fc 0x00000002 0x00000002>;            //qspi_io_trim_cntrl_0
+				};
+				prod_c_secure {
+					prod = <
+						0 0x0000f000 0x0000003f 0x00000000>;            //qspi_secure_axi_ctl_0
+				};
+			};
+		};
+
+		spi@3300000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod_c_nonsecure {
+					prod = <
+						0 0x0000f000 0x0000003f 0x00000012>;            //qspi_secure_axi_ctl_0
+				};
+				prod_c_nopwrsave {
+					prod = <
+						0 0x00000194 0x80000000 0x80000000              //qspi_misc_0
+						0 0x000001ec 0x00000002 0x00000000              //qspi_qspi_comp_control_0
+						0 0x000001fc 0x00000002 0x00000000>;            //qspi_io_trim_cntrl_0
+				};
+				prod_c_pwrsave {
+					prod = <
+						0 0x00000194 0x80000000 0x00000000              //qspi_misc_0
+						0 0x000001ec 0x00000002 0x00000002              //qspi_qspi_comp_control_0
+						0 0x000001fc 0x00000002 0x00000002>;            //qspi_io_trim_cntrl_0
+				};
+				prod_c_secure {
+					prod = <
+						0 0x0000f000 0x0000003f 0x00000000>;            //qspi_secure_axi_ctl_0
+				};
+			};
+		};
+
+		spi@c260000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x00000194 0x80000000 0x00000000>;            //spi_misc_0
+				};
+			};
+		};
+
+		padctl@3520000 {
+			prod-settings {
+				#prod-cells = <4>;
+				prod {
+					prod = <
+						0 0x00000284 0x00000038 0x00000038              //XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0
+						0 0x00000288 0x03fff000 0x0051e000>;            //XUSB_PADCTL_USB2_BIAS_PAD_CTL_1_0
+				};
+			};
+		};
+	};
+};

nv-soc/tegra234-soc-safetyservice-fsicom.dtsi

@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include <dt-bindings/mailbox/tegra186-hsp.h>
+#include <dt-bindings/memory/tegra234-mc.h>
+
+/ {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		fsicom_resv: reservation-fsicom {
+			iommu-addresses = <&fsicom_client 0x0 0x0 0x0 0xf0000000>,
+				<&fsicom_client 0x0 0xf1000000 0xffffffff 0x0effffff>;
+		};
+		fsicom_resv_inst1: reservation-fsicom_inst1 {
+			iommu-addresses = <&fsicom_client_inst1 0x0 0x0 0x0 0xf0000000>,
+				<&fsicom_client_inst1 0x0 0xf1000000 0xffffffff 0x0effffff>;
+		};
+	};
+
+	fsicom_client: fsicom_client {
+		compatible = "nvidia,tegra234-fsicom-client";
+#if TEGRA_HSP_DT_VERSION >= DT_VERSION_2
+		mboxes =
+			<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(2)>,
+			<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(1)>,
+			<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(5)>,
+			<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(4)>;
+#else
+		mboxes =
+			<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(2)>,
+			<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_RX(1)>,
+			<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(5)>,
+			<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_RX(4)>;
+#endif
+		mbox-names = "fsi-tx-cpu0", "fsi-rx-cpu0", "fsi-tx-cpu1", "fsi-rx-cpu1";
+		iommus = <&smmu_niso1 TEGRA234_SID_NISO1_FSI_CPU0>;
+		memory-region = <&fsicom_resv>;
+		dma-coherent;
+#if defined(ENABLE_FSI) && !defined(ENABLE_MODS_CONFIG)
+		enable-deinit-notify;
+#endif
+		smmu_inst = <0>;
+		max_fsi_core=<1>; /*Value 1 <-> core 0, value 2 <-> core0,1*/
+		status = "disabled";
+	};
+	fsicom_client_inst1: fsicom_client_inst1 {
+		compatible = "nvidia,tegra234-fsicom-client";
+		iommus = <&smmu_niso1 TEGRA234_SID_NISO1_FSI_CPU1>;
+		memory-region = <&fsicom_resv_inst1>;
+		dma-coherent;
+		smmu_inst = <1>;
+		status = "okay";
+	};
+	safetyservices_epl_client@110000 {
+		compatible = "nvidia,tegra234-epl-client";
+#if TEGRA_HSP_DT_VERSION >= DT_VERSION_2
+		mboxes =
+			<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(0)>;
+#else
+		mboxes =
+			<&hsp_top2 TEGRA_HSP_MBOX_TYPE_SM_128BIT TEGRA_HSP_SM_TX(0)>;
+#endif
+		mbox-names = "epl-tx";
+
+		reg = <0x0 0x00110000 0x0 0x4>,
+			  <0x0 0x00110004 0x0 0x4>,
+			  <0x0 0x00120000 0x0 0x4>,
+			  <0x0 0x00120004 0x0 0x4>,
+			  <0x0 0x00130000 0x0 0x4>,
+			  <0x0 0x00130004 0x0 0x4>,
+			  <0x0 0x00140000 0x0 0x4>,
+			  <0x0 0x00140004 0x0 0x4>,
+			  <0x0 0x00150000 0x0 0x4>,
+			  <0x0 0x00150004 0x0 0x4>,
+			  <0x0 0x024e0038 0x0 0x4>;
+
+		/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR0_SW_ERR_CODE_0 */
+		client-misc-sw-generic-err0 = "fsicom_client";
+		/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR1_SW_ERR_CODE_0 */
+		client-misc-sw-generic-err1 = "gk20b";
+		/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR3_SW_ERR_CODE_0 */
+		client-misc-sw-generic-err3 = "gk20d";
+		/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR4_SW_ERR_CODE_0 */
+		client-misc-sw-generic-err4 = "gk20e";
+
+#if defined(ENABLE_FSI) && !defined(ENABLE_MODS_CONFIG)
+		enable-deinit-notify;
+#endif
+		status = "disabled";
+
+	};
+	FsiComIvc {
+		compatible = "nvidia,tegra-fsicom-channels";
+		status = "disabled";
+		nChannel=<7>;
+		channel_0{
+			frame-count = <4>;
+			frame-size = <1024>;
+			core-id = <0>;
+			NvSciCh = "nvfsicom_EPD";
+		};
+		channel_1{
+			frame-count = <30>;
+			frame-size = <64>;
+			core-id = <0>;
+			NvSciCh = "nvfsicom_CcplexApp";
+		};
+		channel_2{
+			frame-count = <4>;
+			frame-size = <64>;
+			core-id = <0>;
+			NvSciCh = "nvfsicom_CcplexApp_state_change";
+		};
+		channel_3{
+			frame-count = <4>;
+			frame-size = <64>;
+			core-id = <0>;
+			NvSciCh = "nvfsicom_app1";
+		};
+		channel_4{
+			frame-count = <2>;
+			frame-size = <64>;
+			core-id = <1>;
+			NvSciCh = "nvfsicom_app2";
+		};
+		channel_5{
+			frame-count = <4>;
+			frame-size = <64>;
+			core-id = <0>;
+			NvSciCh = "nvfsicom_appGR";
+		};
+		channel_6{
+			frame-count = <4>;
+			frame-size = <10240>;
+			core-id = <0>;
+		};
+	};
+
+	FsiComClientChConfigEpd{
+		compatible = "nvidia,tegra-fsicom-EPD";
+		status = "disabled";
+		channelid_list = <0>;
+	};
+};

nv-soc/tegra234-soc-thermal-shutdown.dtsi

@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#define TEGRA234_THERMAL_SHUTDOWN_TEMP 104500
+
+/ {
+	thermal-zones {
+		cpu-thermal {
+			trips {
+				cpu_sw_shutdown: cpu-sw-shutdown {
+					temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpu-thermal {
+			trips {
+				gpu_sw_shutdown: gpu-sw-shutdown {
+					temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		cv0-thermal {
+			trips {
+				cv0_sw_shutdown: cv0-sw-shutdown {
+					temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		cv1-thermal {
+			trips {
+				cv1_sw_shutdown: cv1-sw-shutdown {
+					temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		cv2-thermal {
+			trips {
+				cv2_sw_shutdown: cv2-sw-shutdown {
+					temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		soc0-thermal {
+			trips {
+				soc0_sw_shutdown: soc0-sw-shutdown {
+					temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		soc1-thermal {
+			trips {
+				soc1_sw_shutdown: soc1-sw-shutdown {
+					temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		soc2-thermal {
+			trips {
+				soc2_sw_shutdown: soc2-sw-shutdown {
+					temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		tj-thermal {
+			trips {
+				tj_sw_shutdown: tj-sw-shutdown {
+					temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};

nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi

@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include <dt-bindings/thermal/thermal.h>
+
+#define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
+
+/ {
+	bus@0 {
+		gpu@17000000 {
+			#cooling-cells = <2>;
+		};
+	};
+
+	cpus{
+		cpu@0 {
+			#cooling-cells = <2>;
+		};
+
+		cpu@10000 {
+			#cooling-cells = <2>;
+		};
+
+		cpu@20000 {
+			#cooling-cells = <2>;
+		};
+	};
+
+	thermal-zones {
+		cpu-thermal {
+			trips {
+				cpu_sw_slowdown: cpu-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&cpu_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&cpu_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpu-thermal {
+			trips {
+				gpu_sw_slowdown: gpu-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&gpu_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&gpu_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cv0-thermal {
+			trips {
+				cv0_sw_slowdown: cv0-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&cv0_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&cv0_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cv1-thermal {
+			trips {
+				cv1_sw_slowdown: cv1-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&cv1_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&cv1_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cv2-thermal {
+			trips {
+				cv2_sw_slowdown: cv2-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&cv2_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&cv2_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		soc0-thermal {
+			trips {
+				soc0_sw_slowdown: soc0-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&soc0_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&soc0_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		soc1-thermal {
+			trips {
+				soc1_sw_slowdown: soc1-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&soc1_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&soc1_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		soc2-thermal {
+			trips {
+				soc2_sw_slowdown: soc2-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&soc2_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&soc2_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+};

nv-soc/tegra234-soc-thermal-slowdown-corepair.dtsi

@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#include <dt-bindings/thermal/thermal.h>
+
+#define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
+
+/ {
+	bus@0 {
+		gpu@17000000 {
+			#cooling-cells = <2>;
+		};
+	};
+
+	cpus{
+		cpu@0 {
+			#cooling-cells = <2>;
+		};
+
+		cpu@200 {
+			#cooling-cells = <2>;
+		};
+
+		cpu@10000 {
+			#cooling-cells = <2>;
+		};
+
+		cpu@10200 {
+			#cooling-cells = <2>;
+		};
+
+		cpu@20000 {
+			#cooling-cells = <2>;
+		};
+
+		cpu@20200 {
+			#cooling-cells = <2>;
+		};
+	};
+
+	thermal-zones {
+		cpu-thermal {
+			trips {
+				cpu_sw_slowdown: cpu-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&cpu_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&cpu_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpu-thermal {
+			trips {
+				gpu_sw_slowdown: gpu-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&gpu_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&gpu_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cv0-thermal {
+			trips {
+				cv0_sw_slowdown: cv0-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&cv0_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&cv0_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cv1-thermal {
+			trips {
+				cv1_sw_slowdown: cv1-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&cv1_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&cv1_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cv2-thermal {
+			trips {
+				cv2_sw_slowdown: cv2-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&cv2_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&cv2_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		soc0-thermal {
+			trips {
+				soc0_sw_slowdown: soc0-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&soc0_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&soc0_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		soc1-thermal {
+			trips {
+				soc1_sw_slowdown: soc1-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&soc1_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&soc1_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		soc2-thermal {
+			trips {
+				soc2_sw_slowdown: soc2-sw-slowdown {
+					temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-cpufreq {
+					trip = <&soc2_sw_slowdown>;
+					cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+
+				map-devfreq {
+					trip = <&soc2_sw_slowdown>;
+					cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+};

nv-soc/tegra234-soc-thermal-trip-event.dtsi

@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#define TEGRA234_THERMAL_HOT_SURFACE_TEMP 70000
+#define TEGRA234_THERMAL_HOT_SURFACE_HYST 8000
+
+/ {
+	cpu_throttle_alert: cpu-throttle-alert {
+		compatible = "thermal-trip-event";
+		cdev-type = "cpu-throttle-alert";
+		#cooling-cells = <2>;
+	};
+
+	gpu_throttle_alert: gpu-throttle-alert {
+		compatible = "thermal-trip-event";
+		cdev-type = "gpu-throttle-alert";
+		#cooling-cells = <2>;
+	};
+
+	cv0_throttle_alert: cv0-throttle-alert {
+		compatible = "thermal-trip-event";
+		cdev-type = "cv0-throttle-alert";
+		#cooling-cells = <2>;
+	};
+
+	cv1_throttle_alert: cv1-throttle-alert {
+		compatible = "thermal-trip-event";
+		cdev-type = "cv1-throttle-alert";
+		#cooling-cells = <2>;
+	};
+
+	cv2_throttle_alert: cv2-throttle-alert {
+		compatible = "thermal-trip-event";
+		cdev-type = "cv2-throttle-alert";
+		#cooling-cells = <2>;
+	};
+
+	soc0_throttle_alert: soc0-throttle-alert {
+		compatible = "thermal-trip-event";
+		cdev-type = "soc0-throttle-alert";
+		#cooling-cells = <2>;
+	};
+
+	soc1_throttle_alert: soc1-throttle-alert {
+		compatible = "thermal-trip-event";
+		cdev-type = "soc1-throttle-alert";
+		#cooling-cells = <2>;
+	};
+
+	soc2_throttle_alert: soc2-throttle-alert {
+		compatible = "thermal-trip-event";
+		cdev-type = "soc2-throttle-alert";
+		#cooling-cells = <2>;
+	};
+
+	hot_surface_alert: hot-surface-alert {
+		compatible = "thermal-trip-event";
+		cdev-type = "hot-surface-alert";
+		#cooling-cells = <2>;
+	};
+
+	thermal-zones {
+		cpu-thermal {
+			trips {
+				cpu_trip_hot_surface: hot-surface {
+					temperature = <TEGRA234_THERMAL_HOT_SURFACE_TEMP>;
+					hysteresis = <TEGRA234_THERMAL_HOT_SURFACE_HYST>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-throttle-alert {
+					trip = <&cpu_sw_slowdown>;
+					cooling-device = <&cpu_throttle_alert 1 1>;
+				};
+
+				map-hot-surface-alert {
+					trip = <&cpu_trip_hot_surface>;
+					cooling-device = <&hot_surface_alert 1 1>;
+				};
+			};
+		};
+
+		gpu-thermal {
+			trips {
+				gpu_trip_hot_surface: hot-surface {
+					temperature = <TEGRA234_THERMAL_HOT_SURFACE_TEMP>;
+					hysteresis = <TEGRA234_THERMAL_HOT_SURFACE_HYST>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-throttle-alert {
+					trip = <&gpu_sw_slowdown>;
+					cooling-device = <&gpu_throttle_alert 1 1>;
+				};
+
+				map-hot-surface-alert {
+					trip = <&gpu_trip_hot_surface>;
+					cooling-device = <&hot_surface_alert 1 1>;
+				};
+			};
+		};
+
+		cv0-thermal {
+			trips {
+				cv0_trip_hot_surface: hot-surface {
+					temperature = <TEGRA234_THERMAL_HOT_SURFACE_TEMP>;
+					hysteresis = <TEGRA234_THERMAL_HOT_SURFACE_HYST>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-throttle-alert {
+					trip = <&cv0_sw_slowdown>;
+					cooling-device = <&cv0_throttle_alert 1 1>;
+				};
+
+				map-hot-surface-alert {
+					trip = <&cv0_trip_hot_surface>;
+					cooling-device = <&hot_surface_alert 1 1>;
+				};
+			};
+		};
+
+		cv1-thermal {
+			trips {
+				cv1_trip_hot_surface: hot-surface {
+					temperature = <TEGRA234_THERMAL_HOT_SURFACE_TEMP>;
+					hysteresis = <TEGRA234_THERMAL_HOT_SURFACE_HYST>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-throttle-alert {
+					trip = <&cv1_sw_slowdown>;
+					cooling-device = <&cv1_throttle_alert 1 1>;
+				};
+
+				map-hot-surface-alert {
+					trip = <&cv1_trip_hot_surface>;
+					cooling-device = <&hot_surface_alert 1 1>;
+				};
+			};
+		};
+
+		cv2-thermal {
+			trips {
+				cv2_trip_hot_surface: hot-surface {
+					temperature = <TEGRA234_THERMAL_HOT_SURFACE_TEMP>;
+					hysteresis = <TEGRA234_THERMAL_HOT_SURFACE_HYST>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-throttle-alert {
+					trip = <&cv2_sw_slowdown>;
+					cooling-device = <&cv2_throttle_alert 1 1>;
+				};
+
+				map-hot-surface-alert {
+					trip = <&cv2_trip_hot_surface>;
+					cooling-device = <&hot_surface_alert 1 1>;
+				};
+			};
+		};
+
+		soc0-thermal {
+			trips {
+				soc0_trip_hot_surface: hot-surface {
+					temperature = <TEGRA234_THERMAL_HOT_SURFACE_TEMP>;
+					hysteresis = <TEGRA234_THERMAL_HOT_SURFACE_HYST>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-throttle-alert {
+					trip = <&soc0_sw_slowdown>;
+					cooling-device = <&soc0_throttle_alert 1 1>;
+				};
+
+				map-hot-surface-alert {
+					trip = <&soc0_trip_hot_surface>;
+					cooling-device = <&hot_surface_alert 1 1>;
+				};
+			};
+		};
+
+		soc1-thermal {
+			trips {
+				soc1_trip_hot_surface: hot-surface {
+					temperature = <TEGRA234_THERMAL_HOT_SURFACE_TEMP>;
+					hysteresis = <TEGRA234_THERMAL_HOT_SURFACE_HYST>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-throttle-alert {
+					trip = <&soc1_sw_slowdown>;
+					cooling-device = <&soc1_throttle_alert 1 1>;
+				};
+
+				map-hot-surface-alert {
+					trip = <&soc1_trip_hot_surface>;
+					cooling-device = <&hot_surface_alert 1 1>;
+				};
+			};
+		};
+
+		soc2-thermal {
+			trips {
+				soc2_trip_hot_surface: hot-surface {
+					temperature = <TEGRA234_THERMAL_HOT_SURFACE_TEMP>;
+					hysteresis = <TEGRA234_THERMAL_HOT_SURFACE_HYST>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map-throttle-alert {
+					trip = <&soc2_sw_slowdown>;
+					cooling-device = <&soc2_throttle_alert 1 1>;
+				};
+
+				map-hot-surface-alert {
+					trip = <&soc2_trip_hot_surface>;
+					cooling-device = <&hot_surface_alert 1 1>;
+				};
+			};
+		};
+	};
+};

nv-soc/tegra234-soc-thermal.dtsi

@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+#define TEGRA234_THERMAL_POLLING_DELAY 1000
+
+/ {
+	thermal-zones {
+		cpu-thermal {
+			status = "okay";
+
+			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
+			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
+		};
+
+		gpu-thermal {
+			status = "okay";
+
+			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
+			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
+		};
+
+		cv0-thermal {
+			status = "okay";
+
+			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
+			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
+		};
+
+		cv1-thermal {
+			status = "okay";
+
+			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
+			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
+		};
+
+		cv2-thermal {
+			status = "okay";
+
+			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
+			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
+		};
+
+		soc0-thermal {
+			status = "okay";
+
+			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
+			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
+		};
+
+		soc1-thermal {
+			status = "okay";
+
+			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
+			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
+		};
+
+		soc2-thermal {
+			status = "okay";
+
+			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
+			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
+		};
+
+		tj-thermal {
+			status = "okay";
+
+			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
+			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
+		};
+	};
+};

optee-dts/tegra234-optee.dts

@@ -0,0 +1,193 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2025, NVIDIA CORPORATION. All rights reserved.
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	/* MB2 fills the non-secure memory chucks here in order to
+	 * enable the dynamic shared memory in OP-TEE.
+	 * Example:
+	 * nsec-memory@<xxx> {
+	 * 	device_type = "memory";
+	 *	reg = <xxx xxx xxx xxx>;
+	 * };
+	 */
+
+	secure-chosen {
+		stdout-path = "stdout";
+	};
+
+	aliases {
+		stdout = &console;
+	};
+
+	console: serial@0c198000 {
+		compatible = "nvidia,tegra234-tcu";
+		reg = <0x0 0x0c198000 0x0 0x1000>;
+		secure-status = "okay";
+		status = "disabled";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		/* MB2 will fill the DICE identities in the DICE node. */
+		dice {
+			compatible = "nvidia,dice-identity";
+			status = "disabled";
+			secure-status = "disabled";
+			#address-cells = <2>;
+			#size-cells = <2>;
+
+			eca-csr@0 {
+				compatible = "nvidia,dice-eca-csr";
+				reg = <0 0 0 0>;
+				status = "disabled";
+				secure-status = "disabled";
+			};
+
+			device-id-cert@0 {
+				compatible = "nvidia,dice-device-id-cert";
+				reg = <0 0 0 0>;
+				status = "disabled";
+				secure-status = "disabled";
+			};
+
+			device-id-key-pub@0 {
+				compatible = "nvidia,dice-device-id-key-pub";
+				reg = <0 0 0 0>;
+				status = "disabled";
+				secure-status = "disabled";
+			};
+
+			alias-key-cert@0 {
+				compatible = "nvidia,dice-alias-key-cert";
+				reg = <0 0 0 0>;
+				status = "disabled";
+				secure-status = "disabled";
+			};
+
+			alias-key-pub@0 {
+				compatible = "nvidia,dice-alias-key-pub";
+				reg = <0 0 0 0>;
+				status = "disabled";
+				secure-status = "disabled";
+			};
+
+			alias-key-priv@0 {
+				compatible = "nvidia,dice-alias-key-priv";
+				reg = <0 0 0 0>;
+				status = "disabled";
+				secure-status = "disabled";
+			};
+		};
+
+		/*
+		 * The fTPM node is created to pass fTPM information from MB2 to OP-TEE.
+		 * The reg attribute indicates the address and the size of the component,
+		 * which will be filled by MB2 at runtime. All addresses are inside TZDRAM.
+		 * The status of the nodes below will always be set to disabled and the
+		 * secure-status will be set to okay by MB2 at runtime.
+		 */
+		ftpm {
+			compatible = "nvidia,ftpm-contents";
+			status = "disabled";
+			secure-status = "disabled";
+			#address-cells = <2>;
+			#size-cells = <2>;
+
+			/* This is the ftpm seed. */
+			ftpm-seed@0 {
+				compatible = "nvidia,ftpm-seed";
+				reg = <0 0 0 0>;
+				status = "disabled";
+				secure-status = "disabled";
+			};
+
+			/*
+			 * This is the Firmware ID private key.
+			 * OP-TEE needs it to sign the EK CSR.
+			 */
+			firmware-id-privkey@0 {
+				compatible = "nvidia,ftpm-firmware-id-privkey";
+				reg = <0 0 0 0>;
+				status = "disabled";
+				secure-status = "disabled";
+			};
+
+			/* This is the Firmware ID certificate. */
+			firmware-id-certificate@0 {
+				compatible = "nvidia,ftpm-firmware-id-certificate";
+				reg = <0 0 0 0>;
+				status = "disabled";
+				secure-status = "disabled";
+			};
+		};
+
+		/* MB2 will fill the address and size of EKB blob. */
+		ekb-blob@0 {
+			compatible = "jetson-ekb-blob";
+			reg = <0 0 0 0>;
+		};
+
+		/* MB2 will fill the address and size. */
+		tpm-event-log@0 {
+			compatible = "arm,tpm_event_log";
+			tpm_event_log_addr = <0x0 0x0>;
+			tpm_event_log_size = <0x0>;
+		};
+	};
+
+	efuse@03810000 {
+		compatible = "nvidia,tegra234-efuse";
+		reg = <0x0 0x03810000 0x0 0x600>;
+		status = "disabled";
+		secure-status = "okay";
+	};
+
+	se0@03b50000 {
+		compatible = "nvidia,tegra234-se0";
+		reg = <0x0 0x03b50000 0x0 0x30000>;
+		status = "disabled";
+		secure-status = "okay";
+	};
+
+	rng1@03b70000 {
+		compatible = "nvidia,tegra234-rng1";
+		reg = <0x0 0x03b70000 0x0 0x10000>;
+		status = "disabled";
+		secure-status = "okay";
+	};
+
+	stmm-device-mappings {
+		uuid = <0xed32d533 0x99e64209 0x9cc02d72 0xcdd998a7>;
+		description = "UEFI-mm";
+
+		device-regions {
+			combuart-t234 {
+				base-address = <0x00000000 0x0c198000>;
+				pages-count = <0x1>;
+				attributes = <0x3>; /* read-write */
+			};
+
+			qspi0-t234 {
+				base-address = <0x00000000 0x03270000>;
+				pages-count = <0x10>;
+				attributes = <0x3>; /* read-write */
+			};
+
+			scratch-t234 {
+				base-address = <0x00000000 0x0c390000>;
+				pages-count = <0x2>;
+				attributes = <0x3>; /* read-write */
+			};
+		};
+	};
+};

overlay/Makefile

@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
-# Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+# SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 DTC_FLAGS += -@
 
@@ -10,12 +10,70 @@ dtbo-y :=
 makefile-path := t23x/nv-public/overlay
 
 dtbo-y += tegra-optee.dtbo
+dtbo-y += tegra234-android.dtbo
+# Build Kdump DTBOs for Android
+ifeq ($(CONFIG_TEGRA_SYSTEM_TYPE_ACK),y)
+dtbo-y += tegra234-android-kdump.dtbo
+dtbo-y += tegra234-android-crash-kernel.dtbo
+endif
 dtbo-y += tegra234-audio-overlay.dtbo
 dtbo-y += tegra234-carveouts.dtbo
-dtbo-y += tegra234-jetson.dtbo
+dtbo-y += tegra234-dcb-p3767-0000-hdmi.dtbo
-dtbo-y += tegra234-p3737-0000+p3701-0000.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-pcie-no-tra.dtbo
-dtbo-y += tegra234-p3740-0002+p3701-0008.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-as-p3701-0004.dtbo
-dtbo-y += tegra234-p3768-0000+p3767-0000.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-as-p3767-0000.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-as-p3767-0001.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-as-p3767-0003.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-as-p3767-0004.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-dynamic.dtbo
+dtbo-y += tegra234-p3768-0000+p3767-0000-dynamic.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-audio-adafruit-uda1334a.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-audio-adafruit-sph0645lm4h.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-audio-fe-pi.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-audio-respeaker-4-mic-array.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-audio-respeaker-4-mic-lin-array.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-csi.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-hdr40.dtbo
+dtbo-y += tegra234-p3737-0000+p3701-0000-m2ke.dtbo
+dtbo-y += tegra234-p3767-0000+p3509-a02-audio-adafruit-sph0645lm4h.dtbo
+dtbo-y += tegra234-p3767-0000+p3509-a02-audio-adafruit-uda1334a.dtbo
+dtbo-y += tegra234-p3767-0000+p3509-a02-audio-fe-pi.dtbo
+dtbo-y += tegra234-p3767-0000+p3509-a02-audio-respeaker-4-mic-array.dtbo
+dtbo-y += tegra234-p3767-0000+p3509-a02-audio-respeaker-4-mic-lin-array.dtbo
+dtbo-y += tegra234-p3767-0000+p3509-a02-csi.dtbo
+dtbo-y += tegra234-p3767-0000+p3509-a02-hdr40.dtbo
+dtbo-y += tegra234-p3767-0000+p3509-a02-m2ke.dtbo
+dtbo-y += tegra234-p3767-0000+p3768-0000-csi.dtbo
+dtbo-y += tegra234-p3971-0000+p3701-0008-camera-dual-imx274-overlay.dtbo
+dtbo-y += tegra234-p3971-0000+p3701-0008-camera-p3762-a00-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-dual-imx274-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-e3331-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-e3333-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-imx185-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-p3762-a00-overlay.dtbo
+dtbo-y += tegra234-p3740-camera-p3783-a00-overlay.dtbo
+dtbo-y += tegra234-p3767-camera-p3768-imx219-dual.dtbo
+dtbo-y += tegra234-p3767-camera-p3768-imx477-dual.dtbo
+dtbo-y += tegra234-p3767-camera-p3768-imx477-dual-4lane.dtbo
+dtbo-y += tegra234-p3767-camera-p3768-imx477-imx219.dtbo
+dtbo-y += tegra234-p3737-camera-eCAM130A-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-dual-hawk-ar0234-e3653-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-imx390-addr-0x21-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-imx390-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-p3762-a00-1Hawk-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-p3762-a00-2Hawk-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-p3762-a00-3Hawk-3Owl-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-p3762-a00-4Hawk-overlay.dtbo
+dtbo-y += tegra234-p3737-camera-p3762-a00-4Owl-overlay.dtbo
+dtbo-y += tegra234-p3767-camera-p3768-imx219-C.dtbo
+dtbo-y += tegra234-p3767-camera-p3768-imx219-A.dtbo
+dtbo-y += tegra234-p3767-camera-p3768-imx219-imx477.dtbo
+dtbo-y += tegra234-p3740-0002+p3701-0008-hdr20.dtbo
+dtbo-y += tegra234-p3740-0002+p3701-0008-m2ke.dtbo
+dtbo-y += tegra234-p3740-0002+p3701-0008-m2kb.dtbo
+dtbo-y += tegra234-p3767-camera-p3768-imx477-C.dtbo
+dtbo-y += tegra234-p3767-camera-p3768-imx477-A.dtbo
+dtbo-y += tegra234-p3740-0002-p3701-0008-csi.dtbo
 
 ifneq ($(dtb-y),)
 dtb-y := $(addprefix $(makefile-path)/,$(dtb-y))

overlay/tegra-optee.dts

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 // Jetson Device-tree overlay for OP-TEE.
 
 /dts-v1/;
@@ -21,6 +21,10 @@
 					method = "smc";
 					status = "disabled";
 				};
+				ftpm {
+					compatible = "microsoft,ftpm";
+					status = "disabled";
+				};
 			};
 		};
 	};

overlay/tegra234-android-crash-kernel.dts

@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+//
+// This file contains the DT reserved-memory disable nodes of the kdump crash kernel
+
+/dts-v1/;
+/plugin/;
+
+/ {
+    fragment-t234-android@0 {
+ 		target-path = "/";
+		__overlay__ {
+			reserved-memory {
+				linux,cma {
+				    status = "disabled";
+				};
+				generic_carveout {
+				    status = "disabled";
+				};
+				grid-of-semaphores {
+				    status = "disabled";
+				};
+				ivm-carveout0 {
+				    status = "disabled";
+				};
+				ivm-carveout1 {
+				    status = "disabled";
+				};
+				virtio_console_region@c0000000 {
+				    status = "disabled";
+				};
+				fsi-carveout {
+				    status = "disabled";
+				};
+				pva-carveout {
+				    status = "disabled";
+				};
+				rce-reservation {
+				    status = "disabled";
+				};
+				ramoops_carveout {
+				    status = "disabled";
+				};
+				vpr-carveout {
+				    status = "disabled";
+				};
+				camdbg_carveout {
+				    status = "disabled";
+				};
+			};
+			bus@0 {
+				i2c@3160000 {
+				    status = "disabled";
+				};
+				i2c@3180000 {
+				    status = "disabled";
+				};
+				i2c@3190000 {
+				    status = "disabled";
+				};
+				i2c@31b0000 {
+				    status = "disabled";
+				};
+				i2c@31e0000 {
+				    status = "disabled";
+				};
+				aconnect@2900000 {
+				    status = "disabled";
+				};
+				host1x@13e00000 {
+				    status = "disabled";
+				};
+				pcie@140a0000 {
+				    status = "disabled";
+				};
+				pcie@140c0000 {
+				    status = "disabled";
+				};
+				pcie@140e0000 {
+				    status = "disabled";
+				};
+				pcie@14100000 {
+				    status = "disabled";
+				};
+				pcie@14120000 {
+				    status = "disabled";
+				};
+				pcie@14140000 {
+				    status = "disabled";
+				};
+				pcie@14160000 {
+				    status = "disabled";
+				};
+				pcie@14180000 {
+				    status = "disabled";
+				};
+				gpu@17000000 {
+				    status = "disabled";
+				};
+				rtc@c2a0000 {
+				    status = "disabled";
+				};
+				hda@3510000 {
+				    status = "disabled";
+				};
+				cbb-fabric@13a00000 {
+				    status = "disabled";
+				};
+			};
+			display@13800000 {
+				    status = "disabled";
+			};
+		};
+	};
+};

overlay/tegra234-android-kdump.dts

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+//
+// This file contains the Android bootargs for the kdump enabled kernel
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/tegra234-android-bootargs.h>
+
+/ {
+	fragment-t234-android@0 {
+		target-path = "/";
+		 __overlay__ {
+			chosen {
+				bootargs=ANDROID_KDUMP_BOOTARGS;
+			};
+		 };
+	};
+};

overlay/tegra234-android.dts

@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+//
+// This file contains the DT nodes of T234 which are not in base/tegra234.dtsi
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/tegra234-android-bootargs.h>
+
+/ {
+	fragment-t234-android@0 {
+		target-path = "/";
+		 __overlay__ {
+			firmware {
+				android {
+					compatible = "android,firmware";
+					first_stage_delay = "1";
+				};
+				optee {
+					compatible = "linaro,optee-tz";
+					method = "smc";
+					status = "okay";
+				};
+				uefi {
+					use-partition-name-suffixes;
+				};
+			};
+
+			chosen {
+				use_dts_cmdline;
+				bootargs   = ANDROID_BOOTARGS;
+				bootconfig = ANDROID_BOOTCONFIG;
+				/* Test key hash, will got overriden on signing server */
+				avb_key0_sha1 = <0x2597c218 0xaae470a1 0x30f61162 0xfeaae70a 0xfd97f011>;
+				/* RSA2K = 520, RSA4K = 1032, RSA8K = 2056 */
+				avb_key0_size = <1032>;
+			};
+
+			bus@0 {
+				ethernet@6800000 {
+					status = "okay";
+				};
+
+				ethernet@6900000 {
+					status = "okay";
+				};
+
+				ethernet@6a00000 {
+					status = "okay";
+				};
+
+				ethernet@6b00000 {
+					status = "okay";
+				};
+
+				/* SPI1, 40pin header, Pin 19(MOSIsdd, Pin 21(MISO), Pin 23(CLK), Pin 24(CS) */
+				spi@3210000 {
+					status = "okay";
+					spi@0 {
+						compatible = "tegra-spidev";
+						reg = <0x0>;
+						spi-max-frequency = <50000000>;
+						controller-data {
+							nvidia,enable-hw-based-cs;
+							nvidia,rx-clk-tap-delay = <0x10>;
+							nvidia,tx-clk-tap-delay = <0x0>;
+						};
+					};
+					spi@1 {
+						compatible = "tegra-spidev";
+						reg = <0x1>;
+						spi-max-frequency = <50000000>;
+						controller-data {
+							nvidia,enable-hw-based-cs;
+							nvidia,rx-clk-tap-delay = <0x10>;
+							nvidia,tx-clk-tap-delay = <0x0>;
+						};
+					};
+
+				};
+
+				/* SPI3, 40pin header, Pin 37(MOSI), Pin 22(MISO), Pin 13(CLK), Pin 18(CS) */
+				spi@3230000 {
+					status = "okay";
+					spi@0 {
+						compatible = "tegra-spidev";
+						reg = <0x0>;
+						spi-max-frequency = <50000000>;
+						controller-data {
+							nvidia,enable-hw-based-cs;
+							nvidia,rx-clk-tap-delay = <0x10>;
+							nvidia,tx-clk-tap-delay = <0x0>;
+						};
+					};
+					spi@1 {
+						compatible = "tegra-spidev";
+						reg = <0x1>;
+						spi-max-frequency = <50000000>;
+						controller-data {
+							nvidia,enable-hw-based-cs;
+							nvidia,rx-clk-tap-delay = <0x10>;
+							nvidia,tx-clk-tap-delay = <0x0>;
+						};
+					};
+				};
+
+				serial@3100000 {
+					dma-coherent;
+					dmas = <&gpcdma 8>, <&gpcdma 8>;
+					dma-names = "rx", "tx";
+				};
+
+				serial@3110000 {
+					dma-coherent;
+					dmas = <&gpcdma 8>, <&gpcdma 8>;
+					dma-names = "rx", "tx";
+				};
+
+				serial@3140000 {
+					dma-coherent;
+					dmas = <&gpcdma 8>, <&gpcdma 8>;
+					dma-names = "rx", "tx";
+				};
+				host1x@13e00000 {
+					crypto@15810000 {
+						status = "disabled";
+					};
+
+					crypto@15820000 {
+						status = "disabled";
+					};
+
+					crypto@15840000 {
+						status = "disabled";
+					};
+				};
+			};
+
+			display@13800000 {
+				hdcp_enabled;
+				status = "okay";
+			};
+		};
+	};
+
+	fragment-t234-android@1 {
+		target-path = "/bus@0/mmc@3400000";
+		delete_prop = "sd-uhs-ddr50";
+	};
+};

overlay/tegra234-audio-overlay.dts

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 /dts-v1/;
 /plugin/;

overlay/tegra234-camera-e3331-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -193,7 +193,6 @@
 								ports {
 									#address-cells = <1>;
 									#size-cells = <0>;
-
 									port@0 {
 										reg = <0>;
 										e3331_imx318_out0: endpoint {
@@ -211,42 +210,6 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				* Set this to the highest pix_clk_hz out of all available modes.
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <3>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <800000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,
@@ -263,8 +226,7 @@
 						orientation = "1";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							devname = "imx318 30-0010";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9546@70/i2c@0/imx318_a@10";
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9546@70/i2c@0/imx318_a@10";
 						};
 					};
 				};

overlay/tegra234-camera-e3333-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2015-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2015-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -63,42 +63,6 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				* Set this to the highest pix_clk_hz out of all available modes.
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <12>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <160000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,
@@ -115,12 +79,11 @@
 						orientation = "1";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							devname = "ov5693 30-0036";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9548@77/i2c@0/ov5693_a@36";
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9548@77/i2c@0/ov5693_a@36";
 						};
 						drivernode1 {
 							pcl_id = "v4l2_lens";
-							proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/e3333_lens_ov5693@P5V27C/";
 						};
 					};
 					module1 {
@@ -129,12 +92,11 @@
 						orientation = "1";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							devname = "ov5693 31-0036";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9548@77/i2c@1/ov5693_b@36";
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9548@77/i2c@1/ov5693_b@36";
 						};
 						drivernode1 {
 							pcl_id = "v4l2_lens";
-							proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/e3333_lens_ov5693@P5V27C/";
 						};
 					};
 					module2 {
@@ -143,12 +105,11 @@
 						orientation = "1";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							devname = "ov5693 32-0036";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9548@77/i2c@2/ov5693_c@36";
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9548@77/i2c@2/ov5693_c@36";
 						};
 						drivernode1 {
 							pcl_id = "v4l2_lens";
-							proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/e3333_lens_ov5693@P5V27C/";
 						};
 					};
 					module3 {
@@ -157,12 +118,11 @@
 						orientation = "1";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							devname = "ov5693 33-0036";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9548@77/i2c@3/ov5693_d@36";
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9548@77/i2c@3/ov5693_d@36";
 						};
 						drivernode1 {
 							pcl_id = "v4l2_lens";
-							proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/e3333_lens_ov5693@P5V27C/";
 						};
 					};
 					module4 {
@@ -171,12 +131,11 @@
 						orientation = "1";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							devname = "ov5693 34-0036";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9548@77/i2c@4/ov5693_e@36";
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9548@77/i2c@4/ov5693_e@36";
 						};
 						drivernode1 {
 							pcl_id = "v4l2_lens";
-							proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/e3333_lens_ov5693@P5V27C/";
 						};
 					};
 					module5 {
@@ -185,12 +144,11 @@
 						orientation = "1";
 						drivernode0 {
 							pcl_id = "v4l2_sensor";
-							devname = "ov5693 35-0036";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9548@77/i2c@5/ov5693_g@36";
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9548@77/i2c@5/ov5693_g@36";
 						};
 						drivernode1 {
 							pcl_id = "v4l2_lens";
-							proc-device-tree = "/proc/device-tree/e3333_lens_ov5693@P5V27C/";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/e3333_lens_ov5693@P5V27C/";
 						};
 					};
 				};

overlay/tegra234-camera-imx185-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2016-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2016-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -402,40 +402,6 @@
 		__overlay__ {
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,
@@ -453,10 +419,8 @@
 						drivernode0 {
 							/* Declare PCL support driver (classically known as guid)  */
 							pcl_id = "v4l2_sensor";
-							/* Driver v4l2 device name */
-							devname = "imx185 30-001a";
 							/* Declare the device-tree hierarchy to driver instance */
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9546@70/i2c@0/imx185_a@1a";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9546@70/i2c@0/imx185_a@1a";
 						};
 					};
 				};

overlay/tegra234-camera-imx274-dual.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -712,41 +712,7 @@
 		__overlay__ {
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
+
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <8>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <750000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,
 				* The first part is the camera_board_id for the module; if the module is in a FFD
@@ -763,15 +729,13 @@
 						drivernode0 {
 							/* Declare PCL support driver (classically known as guid)  */
 							pcl_id = "v4l2_sensor";
-							/* Driver v4l2 device name */
-							devname = "imx274 30-001a";
 							/* Declare the device-tree hierarchy to driver instance */
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9546@70/i2c@0/imx274_a@1a";
 						};
 						drivernode1 {
 							/* Declare PCL support driver (classically known as guid)  */
 							pcl_id = "v4l2_lens";
-							proc-device-tree = "/proc/device-tree/bus@0/lens_imx274@A6V26/";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/lens_imx274@A6V26/";
 						};
 					};
 					module1 {
@@ -781,15 +745,13 @@
 						drivernode0 {
 							/* Declare PCL support driver (classically known as guid)  */
 							pcl_id = "v4l2_sensor";
-							/* Driver v4l2 device name */
-							devname = "imx274 31-001a";
 							/* Declare the device-tree hierarchy to driver instance */
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9546@70/i2c@1/imx274_c@1a";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9546@70/i2c@1/imx274_c@1a";
 						};
 						drivernode1 {
 							/* Declare PCL support driver (classically known as guid)  */
 							pcl_id = "v4l2_lens";
-							proc-device-tree = "/proc/device-tree/bus@0/lens_imx274@A6V26/";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/lens_imx274@A6V26/";
 						};
 					};
 				};

overlay/tegra234-camera-imx390-a00.dtsi

@@ -1,31 +1,21 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2018-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2016-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 
 / {
 	fragment-camera@0 {
 		target-path = "/";
 		__overlay__ {
 			tegra-capture-vi {
-				num-channels = <2>;
+				num-channels = <1>;
 				ports {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					port@0 {
 						reg = <0>;
-						imx390_vi_in0: endpoint {
+						liimx390_vi_in0: endpoint {
-							vc-id = <0>;
 							port-index = <0>;
-							bus-width = <2>;
+							bus-width = <4>;
-							remote-endpoint = <&imx390_csi_out0>;
+							remote-endpoint = <&liimx390_csi_out0>;
-						};
-					};
-					port@1 {
-						reg = <1>;
-						imx390_vi_in1: endpoint {
-							vc-id = <1>;
-							port-index = <0>;
-							bus-width = <2>;
-							remote-endpoint = <&imx390_csi_out1>;
 						};
 					};
 				};
@@ -34,7 +24,7 @@
 			bus@0{
 				host1x@13e00000 {
 					nvcsi@15a00000 {
-						num-channels = <2>;
+						num-channels = <1>;
 						#address-cells = <1>;
 						#size-cells = <0>;
 						channel@0 {
@@ -44,86 +34,74 @@
 								#size-cells = <0>;
 								port@0 {
 									reg = <0>;
-									imx390_csi_in0: endpoint@0 {
+									liimx390_csi_in0: endpoint@0 {
 										port-index = <0>;
-										bus-width = <2>;
+										bus-width = <4>;
-										remote-endpoint = <&imx390_imx390_out0>;
+										remote-endpoint = <&liimx390_imx390_out0>;
 									};
 								};
 								port@1 {
 									reg = <1>;
-									imx390_csi_out0: endpoint@1 {
+									liimx390_csi_out0: endpoint@1 {
-										remote-endpoint = <&imx390_vi_in0>;
+										remote-endpoint = <&liimx390_vi_in0>;
-									};
-								};
-							};
-						};
-						channel@1 {
-							reg = <1>;
-							ports {
-								#address-cells = <1>;
-								#size-cells = <0>;
-								port@0 {
-									reg = <0>;
-									imx390_csi_in1: endpoint@2 {
-										port-index = <0>;
-										bus-width = <2>;
-										remote-endpoint = <&imx390_imx390_out1>;
-									};
-								};
-								port@1 {
-									reg = <1>;
-									imx390_csi_out1: endpoint@3 {
-										remote-endpoint = <&imx390_vi_in1>;
 									};
 								};
 							};
 						};
 					};
 				};
+
 				i2c@3180000 {
 					tca9546@70 {
 						i2c@0 {
-							imx390_a@1b {
+							imx390_a@21 {
 								compatible = "sony,imx390";
-								reg = <0x1b>;
+								reg = <0x21>;
+								devnode = "video0";
 								/* Physical dimensions of sensor */
 								physical_w = "15.0";
 								physical_h = "12.5";
 								sensor_model ="imx390";
+								/* Define any required hw resources needed by driver */
+								/* ie. clocks, io pins, power sources */
 								/* Defines number of frames to be dropped by driver internally after applying */
 								/* sensor crop settings. Some sensors send corrupt frames after applying */
 								/* crop co-ordinates */
 								post_crop_frame_drop = "0";
+
 								/* Convert Gain to unit of dB (decibel) befor passing to kernel driver */
-								use_decibel_gain = "true";
+
+								/* if true, delay gain setting by one frame to be in sync with exposure */
+
 								/* enable CID_SENSOR_MODE_ID for sensor modes selection */
 								use_sensor_mode_id = "true";
+
+								/* WAR to prevent banding by reducing analog gain. Bug 2229902 */
+
 								/**
+								* ==== Modes ====
 								* A modeX node is required to support v4l2 driver
 								* implementation with NVIDIA camera software stack
 								*
-								* mclk_khz = "";
+								* == Signal properties ==
-								* Standard MIPI driving clock, typically 24MHz
 								*
-								* num_lanes = "";
+								* phy_mode = "";
-								* Number of lane channels sensor is programmed to output
+								* PHY mode used by the MIPI lanes for this device
 								*
 								* tegra_sinterface = "";
-								* The base tegra serial interface lanes are connected to
+								* CSI Serial interface connected to tegra
+								* Incase of virtual HW devices, use virtual
+								* For SW emulated devices, use host
 								*
-								* vc_id = "";
+								* pix_clk_hz = "";
-								* The virtual channel id of the sensor.
+								* Sensor pixel clock used for calculations like exposure and framerate
 								*
-								* discontinuous_clk = "";
+								* readout_orientation = "0";
-								* The sensor is programmed to use a discontinuous clock on MIPI lanes
+								* Based on camera module orientation.
+								* Only change readout_orientation if you specifically
+								* Program a different readout order for this mode
 								*
-								* dpcm_enable = "true";
+								* == Image format Properties ==
-								* The sensor is programmed to use a DPCM modes
-								*
-								* cil_settletime = "";
-								* MIPI lane settle time value.
-								* A "0" value attempts to autocalibrate based on mclk_khz and pix_clk_hz
 								*
 								* active_w = "";
 								* Pixel active region width
@@ -131,61 +109,117 @@
 								* active_h = "";
 								* Pixel active region height
 								*
-								* dynamic_pixel_bit_depth = "";
+								* pixel_t = "";
-								* sensor dynamic bit depth for sensor mode
+								* The sensor readout pixel pattern
-								*
-								* csi_pixel_bit_depth = "";
-								* sensor output bit depth for sensor mode
-								*
-								* mode_type="";
-								* Sensor mode type, For eg: yuv, Rgb, bayer, bayer_wdr_pwl
-								*
-								* pixel_phase="";
-								* Pixel phase for sensor mode, For eg: rggb, vyuy, rgb888
-								*
-								* readout_orientation = "0";
-								* Based on camera module orientation.
-								* Only change readout_orientation if you specifically
-								* Program a different readout order for this mode
 								*
 								* line_length = "";
 								* Pixel line length (width) for sensor mode.
-								* This is used to calibrate features in our camera stack.
 								*
-								* pix_clk_hz = "";
+								* == Source Control Settings ==
-								* Sensor pixel clock used for calculations like exposure and framerate
 								*
+								* Gain factor used to convert fixed point integer to float
+								* Gain range [min_gain/gain_factor, max_gain/gain_factor]
+								* Gain step [step_gain/gain_factor is the smallest step that can be configured]
+								* Default gain [Default gain to be initialized for the control.
+								*     use min_gain_val as default for optimal results]
+								* Framerate factor used to convert fixed point integer to float
+								* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
+								* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
+								* Default Framerate [Default framerate to be initialized for the control.
+								*     use max_framerate to get required performance]
+								* Exposure factor used to convert fixed point integer to float
+								* For convenience use 1 sec = 1000000us as conversion factor
+								* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
+								* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
+								* Default Exposure Time [Default exposure to be initialized for the control.
+								*     Set default exposure based on the default_framerate for optimal exposure settings]
 								*
-								*
+								* gain_factor = ""; (integer factor used for floating to fixed point conversion)
-								*
+								* min_gain_val = ""; (ceil to integer)
-								* inherent_gain = "";
+								* max_gain_val = ""; (ceil to integer)
-								* Gain obtained inherently from mode (ie. pixel binning)
+								* step_gain_val = ""; (ceil to integer)
-								*
+								* default_gain = ""; (ceil to integer)
-								* min_gain_val = ""; (floor to 6 decimal places)
-								* max_gain_val = ""; (floor to 6 decimal places)
 								* Gain limits for mode
-								* if use_decibel_gain = "true", please set the gain as decibel
 								*
+								* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
 								* min_exp_time = ""; (ceil to integer)
 								* max_exp_time = ""; (ceil to integer)
-								* Exposure Time limits for mode (us)
+								* step_exp_time = ""; (ceil to integer)
+								* default_exp_time = ""; (ceil to integer)
+								* Exposure Time limits for mode (sec)
 								*
-								*
+								* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
-								* min_hdr_ratio = "";
+								* min_framerate = ""; (ceil to integer)
-								* max_hdr_ratio = "";
+								* max_framerate = ""; (ceil to integer)
-								* HDR Ratio limits for mode
+								* step_framerate = ""; (ceil to integer)
-								*
+								* default_framerate = ""; (ceil to integer)
-								* min_framerate = "";
-								* max_framerate = "";
 								* Framerate limits for mode (fps)
 								*
 								* embedded_metadata_height = "";
 								* Sensor embedded metadata height in units of rows.
 								* If sensor does not support embedded metadata value should be 0.
 								*/
-								mode0 {/*mode IMX390_MODE_1920X1080_CROP_30FPS*/
+								mode0 {/*mode IMX390_WDR_MODE_1936X1216_CROP_30FPS*/
 									mclk_khz = "24000";
-									num_lanes = "2";
+									num_lanes = "4";
+									tegra_sinterface = "serial_a";
+									discontinuous_clk = "no";
+									dpcm_enable = "false";
+									cil_settletime = "0";
+									dynamic_pixel_bit_depth = "20";
+									csi_pixel_bit_depth = "12";
+									mode_type = "bayer_wdr_pwl";
+									pixel_phase = "rggb";
+									active_w = "1936";
+									active_h = "1216";
+									readout_orientation = "0";
+									line_length = "3300"; /* HMAX */
+									inherent_gain = "1";
+									mclk_multiplier = "14.58";
+									pix_clk_hz = "83250000"; /* 249.75Mbps/Lane * 4Lane / 12bit = 83.25[MPixel] */
+									serdes_pix_clk_hz = "500000000";
+									gain_factor = "10";
+									min_gain_val = "1";
+									max_gain_val = "420";
+									step_gain_val = "3";
+									default_gain = "1";
+									framerate_factor = "1000000";
+									min_framerate = "30000000";
+									max_framerate = "30000000";
+									step_framerate = "1";
+									default_framerate = "30000000";
+									exposure_factor = "1000000";
+									min_exp_time = "134"; /* (ERRWID_BACK/2) + 2 = 5[line] */
+									max_exp_time = "33227"; /* MODE_VMAX - 1 - (ERRWID_BACK/2) = 1250 - 1 - (6/2) = 1246[line] */
+									step_exp_time = "1";
+									default_exp_time = "11000";/* us */
+									embedded_metadata_height = "0";
+									min_hdr_ratio = "64.0";
+									max_hdr_ratio = "64.0";
+									num_control_point = "9";
+									control_point_x_0 = "0";
+									control_point_x_1 = "469";
+									control_point_x_2 = "1582";
+									control_point_x_3 = "4592";
+									control_point_x_4 = "13446";
+									control_point_x_5 = "39550";
+									control_point_x_6 = "117664";
+									control_point_x_7 = "352265";
+									control_point_x_8 = "1048575";
+									control_point_y_0 = "0";
+									control_point_y_1 = "469";
+									control_point_y_2 = "840";
+									control_point_y_3 = "1270";
+									control_point_y_4 = "1736";
+									control_point_y_5 = "2238";
+									control_point_y_6 = "2792";
+									control_point_y_7 = "3411";
+									control_point_y_8 = "4095";
+								};
+
+								mode1 {/*mode IMX390_SDR_MODE_1936X1216_CROP_30FPS*/
+									mclk_khz = "24000";
+									num_lanes = "4";
 									tegra_sinterface = "serial_a";
 									vc_id = "0";
 									discontinuous_clk = "no";
@@ -195,18 +229,20 @@
 									csi_pixel_bit_depth = "12";
 									mode_type = "bayer";
 									pixel_phase = "rggb";
-									active_w = "1920";
+
-									active_h = "1080";
+									active_w = "1936";
+									active_h = "1216";
 									readout_orientation = "0";
-									line_length = "2200";
+									line_length = "3300"; /* HMAX */
 									inherent_gain = "1";
-									pix_clk_hz = "74250000";
+									pix_clk_hz = "83250000"; /* 249.75Mbps/Lane * 4Lane / 12bit = 83.25[MPixel] */
 									serdes_pix_clk_hz = "200000000";
+
 									gain_factor = "10";
-									min_gain_val = "0"; /* dB */
+									min_gain_val = "1";
-									max_gain_val = "300"; /* dB */
+									max_gain_val = "420";
-									step_gain_val = "3"; /* 0.3 */
+									step_gain_val = "3";
-									default_gain = "0";
+									default_gain = "1";
 									min_hdr_ratio = "1";
 									max_hdr_ratio = "1";
 									framerate_factor = "1000000";
@@ -215,196 +251,25 @@
 									step_framerate = "1";
 									default_framerate = "30000000";
 									exposure_factor = "1000000";
-									min_exp_time = "59"; /*us, 2 lines*/
+									min_exp_time = "134"; /* (ERRWID_BACK/2) + 2 = 5[line] */
-									max_exp_time = "33333";
+									max_exp_time = "33227"; /* MODE_VMAX - 1 - (ERRWID_BACK/2) = 1250 - 1 - (6/2) = 1246[line] */
 									step_exp_time = "1";
-									default_exp_time = "33333";/* us */
+									default_exp_time = "11000";/* us */
 									embedded_metadata_height = "0";
 								};
+
 								ports {
 									#address-cells = <1>;
 									#size-cells = <0>;
 									port@0 {
 										reg = <0>;
-										imx390_imx390_out0: endpoint {
+										liimx390_imx390_out0: endpoint {
-											vc-id = <0>;
 											port-index = <0>;
-											bus-width = <2>;
+											bus-width = <4>;
-											remote-endpoint = <&imx390_csi_in0>;
+											remote-endpoint = <&liimx390_csi_in0>;
 										};
 									};
 								};
-								gmsl-link {
-									src-csi-port = "b";
-									dst-csi-port = "a";
-									serdes-csi-link = "a";
-									csi-mode = "1x4";
-									st-vc = <0>;
-									vc-id = <0>;
-									num-lanes = <2>;
-									streams = "ued-u1", "raw12";
-								};
-							};
-							imx390_b@1c {
-								compatible = "sony,imx390";
-								reg = <0x1c>;
-								/* Physical dimensions of sensor */
-								physical_w = "15.0";
-								physical_h = "12.5";
-								sensor_model ="imx390";
-								/* Defines number of frames to be dropped by driver internally after applying */
-								/* sensor crop settings. Some sensors send corrupt frames after applying */
-								/* crop co-ordinates */
-								post_crop_frame_drop = "0";
-								/* Convert Gain to unit of dB (decibel) befor passing to kernel driver */
-								use_decibel_gain = "true";
-								/* enable CID_SENSOR_MODE_ID for sensor modes selection */
-								use_sensor_mode_id = "true";
-								/**
-								* A modeX node is required to support v4l2 driver
-								* implementation with NVIDIA camera software stack
-								*
-								* mclk_khz = "";
-								* Standard MIPI driving clock, typically 24MHz
-								*
-								* num_lanes = "";
-								* Number of lane channels sensor is programmed to output
-								*
-								* tegra_sinterface = "";
-								* The base tegra serial interface lanes are connected to
-								*
-								* vc_id = "";
-								* The virtual channel id of the sensor.
-								*
-								* discontinuous_clk = "";
-								* The sensor is programmed to use a discontinuous clock on MIPI lanes
-								*
-								* dpcm_enable = "true";
-								* The sensor is programmed to use a DPCM modes
-								*
-								* cil_settletime = "";
-								* MIPI lane settle time value.
-								* A "0" value attempts to autocalibrate based on mclk_khz and pix_clk_hz
-								*
-								* active_w = "";
-								* Pixel active region width
-								*
-								* active_h = "";
-								* Pixel active region height
-								*
-								* dynamic_pixel_bit_depth = "";
-								* sensor dynamic bit depth for sensor mode
-								*
-								* csi_pixel_bit_depth = "";
-								* sensor output bit depth for sensor mode
-								*
-								* mode_type="";
-								* Sensor mode type, For eg: yuv, Rgb, bayer, bayer_wdr_pwl
-								*
-								* pixel_phase="";
-								* Pixel phase for sensor mode, For eg: rggb, vyuy, rgb888
-								*
-								* readout_orientation = "0";
-								* Based on camera module orientation.
-								* Only change readout_orientation if you specifically
-								* Program a different readout order for this mode
-								*
-								* line_length = "";
-								* Pixel line length (width) for sensor mode.
-								* This is used to calibrate features in our camera stack.
-								*
-								* pix_clk_hz = "";
-								* Sensor pixel clock used for calculations like exposure and framerate
-								*
-								*
-								*
-								*
-								* inherent_gain = "";
-								* Gain obtained inherently from mode (ie. pixel binning)
-								*
-								* min_gain_val = ""; (floor to 6 decimal places)
-								* max_gain_val = ""; (floor to 6 decimal places)
-								* Gain limits for mode
-								* if use_decibel_gain = "true", please set the gain as decibel
-								*
-								* min_exp_time = ""; (ceil to integer)
-								* max_exp_time = ""; (ceil to integer)
-								* Exposure Time limits for mode (us)
-								*
-								*
-								* min_hdr_ratio = "";
-								* max_hdr_ratio = "";
-								* HDR Ratio limits for mode
-								*
-								* min_framerate = "";
-								* max_framerate = "";
-								* Framerate limits for mode (fps)
-								*
-								* embedded_metadata_height = "";
-								* Sensor embedded metadata height in units of rows.
-								* If sensor does not support embedded metadata value should be 0.
-								*/
-								mode0 {/*mode IMX390_MODE_1920X1080_CROP_30FPS*/
-									mclk_khz = "24000";
-									num_lanes = "2";
-									tegra_sinterface = "serial_a";
-									vc_id = "1";
-									discontinuous_clk = "no";
-									dpcm_enable = "false";
-									cil_settletime = "0";
-									dynamic_pixel_bit_depth = "12";
-									csi_pixel_bit_depth = "12";
-									mode_type = "bayer";
-									pixel_phase = "rggb";
-									active_w = "1920";
-									active_h = "1080";
-									readout_orientation = "0";
-									line_length = "2200";
-									inherent_gain = "1";
-									pix_clk_hz = "74250000";
-									serdes_pix_clk_hz = "200000000";
-									gain_factor = "10";
-									min_gain_val = "0"; /* dB */
-									max_gain_val = "300"; /* dB */
-									step_gain_val = "3"; /* 0.3 */
-									default_gain = "0";
-									min_hdr_ratio = "1";
-									max_hdr_ratio = "1";
-									framerate_factor = "1000000";
-									min_framerate = "30000000";
-									max_framerate = "30000000";
-									step_framerate = "1";
-									default_framerate = "30000000";
-									exposure_factor = "1000000";
-									min_exp_time = "59"; /*us, 2 lines*/
-									max_exp_time = "33333";
-									step_exp_time = "1";
-									default_exp_time = "33333";/* us */
-									embedded_metadata_height = "0";
-								};
-								ports {
-									#address-cells = <1>;
-									#size-cells = <0>;
-									port@0 {
-										reg = <0>;
-										imx390_imx390_out1: endpoint {
-											vc-id = <1>;
-											port-index = <0>;
-											bus-width = <2>;
-											remote-endpoint = <&imx390_csi_in1>;
-										};
-									};
-								};
-								gmsl-link {
-									src-csi-port = "b";
-									dst-csi-port = "a";
-									serdes-csi-link = "b";
-									csi-mode = "1x4";
-									st-vc = <0>;
-									vc-id = <1>;
-									num-lanes = <2>;
-									streams = "ued-u1", "raw12";
-								};
 							};
 						};
 					};
@@ -413,40 +278,6 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <2>;
-				max_lane_speed = <4000000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,
 				* The first part is the camera_board_id for the module; if the module is in a FFD
@@ -457,29 +288,14 @@
 				*/
 				modules {
 					module0 {
-						badge = "imx390_rear";
+						badge = "imx390_bottomleft_liimx390";
-						position = "rear";
+						position = "bottomleft";
-						orientation = "1";
+						orientation = "0";
 						drivernode0 {
 							/* Declare PCL support driver (classically known as guid)  */
 							pcl_id = "v4l2_sensor";
-							/* Driver v4l2 device name */
-							devname = "imx390 30-001b";
 							/* Declare the device-tree hierarchy to driver instance */
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9546@70/i2c@0/imx390_a@1b";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/tca9546@70/i2c@0/imx390_a@21";
-						};
-					};
-					module1 {
-						badge = "imx390_front";
-						position = "front";
-						orientation = "1";
-						drivernode0 {
-							/* Declare PCL support driver (classically known as guid)  */
-							pcl_id = "v4l2_sensor";
-							/* Driver v4l2 device name */
-							devname = "imx390 30-001c";
-							/* Declare the device-tree hierarchy to driver instance */
-							proc-device-tree = "/proc/device-tree/bus@0/i2c@3180000/tca9546@70/i2c@0/imx390_b@1c";
 						};
 					};
 				};

overlay/tegra234-camera-rbpcv2-imx219.dtsi

@@ -0,0 +1,727 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+#include <dt-bindings/clock/tegra234-clock.h>
+#include <dt-bindings/gpio/tegra234-gpio.h>
+
+/ {
+	fragment-camera@0 {
+		target-path = "/";
+		__overlay__ {
+			tegra-capture-vi  {
+				num-channels = <2>;
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					vi_port0: port@0 {
+						reg = <0>;
+						rbpcv2_imx219_vi_in0: endpoint {
+							port-index = <1>;
+							bus-width = <2>;
+							remote-endpoint = <&rbpcv2_imx219_csi_out0>;
+						};
+					};
+					vi_port1: port@1 {
+						reg = <1>;
+						rbpcv2_imx219_vi_in1: endpoint {
+							port-index = <2>;
+							bus-width = <2>;
+							remote-endpoint = <&rbpcv2_imx219_csi_out1>;
+						};
+					};
+				};
+			};
+
+			bus@0 {
+				host1x@13e00000 {
+					nvcsi@15a00000 {
+						num-channels = <2>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						csi_chan0: channel@0 {
+							reg = <0>;
+							ports {
+								#address-cells = <1>;
+								#size-cells = <0>;
+								csi_chan0_port0: port@0 {
+									reg = <0>;
+									rbpcv2_imx219_csi_in0: endpoint@0 {
+										port-index = <1>;
+										bus-width = <2>;
+										remote-endpoint = <&rbpcv2_imx219_out0>;
+									};
+								};
+								csi_chan0_port1: port@1 {
+									reg = <1>;
+									rbpcv2_imx219_csi_out0: endpoint@1 {
+										remote-endpoint = <&rbpcv2_imx219_vi_in0>;
+									};
+								};
+							};
+						};
+						csi_chan1: channel@1 {
+							reg = <1>;
+							ports {
+								#address-cells = <1>;
+								#size-cells = <0>;
+								csi_chan1_port0: port@0 {
+									reg = <0>;
+									rbpcv2_imx219_csi_in1: endpoint@2 {
+										port-index = <2>;
+										bus-width = <2>;
+										remote-endpoint = <&rbpcv2_imx219_out1>;
+									};
+								};
+								csi_chan1_port1: port@1 {
+									reg = <1>;
+									rbpcv2_imx219_csi_out1: endpoint@3 {
+										remote-endpoint = <&rbpcv2_imx219_vi_in1>;
+									};
+								};
+							};
+						};
+					};
+				};
+				cam_i2cmux {
+					i2c_0:i2c@0 {
+						imx219_cam0: rbpcv2_imx219_a@10 {
+							compatible = "sony,imx219";
+							/* I2C device address */
+							reg = <0x10>;
+							/* V4L2 device node location */
+							devnode = "video0";
+							/* Physical dimensions of sensor */
+							physical_w = "3.680";
+							physical_h = "2.760";
+							sensor_model = "imx219";
+							use_sensor_mode_id = "true";
+							/**
+							* ==== Modes ====
+							* A modeX node is required to support v4l2 driver
+							* implementation with NVIDIA camera software stack
+							*
+							* == Signal properties ==
+							*
+							* phy_mode = "";
+							* PHY mode used by the MIPI lanes for this device
+							*
+							* tegra_sinterface = "";
+							* CSI Serial interface connected to tegra
+							* Incase of virtual HW devices, use virtual
+							* For SW emulated devices, use host
+							*
+							* pix_clk_hz = "";
+							* Sensor pixel clock used for calculations like exposure and framerate
+							*
+							* readout_orientation = "0";
+							* Based on camera module orientation.
+							* Only change readout_orientation if you specifically
+							* Program a different readout order for this mode
+							*
+							* == Image format Properties ==
+							*
+							* active_w = "";
+							* Pixel active region width
+							*
+							* active_h = "";
+							* Pixel active region height
+							*
+							* pixel_t = "";
+							* The sensor readout pixel pattern
+							*
+							* line_length = "";
+							* Pixel line length (width) for sensor mode.
+							*
+							* == Source Control Settings ==
+							*
+							* Gain factor used to convert fixed point integer to float
+							* Gain range [min_gain/gain_factor, max_gain/gain_factor]
+							* Gain step [step_gain/gain_factor is the smallest step that can be configured]
+							* Default gain [Default gain to be initialized for the control.
+							*     use min_gain_val as default for optimal results]
+							* Framerate factor used to convert fixed point integer to float
+							* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
+							* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
+							* Default Framerate [Default framerate to be initialized for the control.
+							*     use max_framerate to get required performance]
+							* Exposure factor used to convert fixed point integer to float
+							* For convenience use 1 sec = 1000000us as conversion factor
+							* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
+							* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
+							* Default Exposure Time [Default exposure to be initialized for the control.
+							*     Set default exposure based on the default_framerate for optimal exposure settings]
+							*
+							* gain_factor = ""; (integer factor used for floating to fixed point conversion)
+							* min_gain_val = ""; (ceil to integer)
+							* max_gain_val = ""; (ceil to integer)
+							* step_gain_val = ""; (ceil to integer)
+							* default_gain = ""; (ceil to integer)
+							* Gain limits for mode
+							*
+							* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
+							* min_exp_time = ""; (ceil to integer)
+							* max_exp_time = ""; (ceil to integer)
+							* step_exp_time = ""; (ceil to integer)
+							* default_exp_time = ""; (ceil to integer)
+							* Exposure Time limits for mode (sec)
+							*
+							* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
+							* min_framerate = ""; (ceil to integer)
+							* max_framerate = ""; (ceil to integer)
+							* step_framerate = ""; (ceil to integer)
+							* default_framerate = ""; (ceil to integer)
+							* Framerate limits for mode (fps)
+							*
+							* embedded_metadata_height = "";
+							* Sensor embedded metadata height in units of rows.
+							* If sensor does not support embedded metadata value should be 0.
+							*/
+							mode0 { /* IMX219_MODE_3280x2464_21FPS */
+								mclk_khz = "24000";
+								num_lanes = "2";
+								tegra_sinterface = "serial_b";
+								lane_polarity = "6";
+								phy_mode = "DPHY";
+								discontinuous_clk = "yes";
+								dpcm_enable = "false";
+								cil_settletime = "0";
+								active_w = "3280";
+								active_h = "2464";
+								mode_type = "bayer";
+								pixel_phase = "rggb";
+								csi_pixel_bit_depth = "10";
+								readout_orientation = "90";
+								line_length = "3448";
+								inherent_gain = "1";
+								mclk_multiplier = "9.33";
+								pix_clk_hz = "182400000";
+								gain_factor = "16";
+								framerate_factor = "1000000";
+								exposure_factor = "1000000";
+								min_gain_val = "16"; /* 1.00x */
+								max_gain_val = "170"; /* 10.66x */
+								step_gain_val = "1";
+								default_gain = "16"; /* 1.00x */
+								min_hdr_ratio = "1";
+								max_hdr_ratio = "1";
+								min_framerate = "2000000"; /* 2.0 fps */
+								max_framerate = "21000000"; /* 21.0 fps */
+								step_framerate = "1";
+								default_framerate = "21000000"; /* 21.0 fps */
+								min_exp_time = "13"; /* us */
+								max_exp_time = "683709"; /* us */
+								step_exp_time = "1";
+								default_exp_time = "2495"; /* us */
+								embedded_metadata_height = "2";
+							};
+							mode1 { /* IMX219_MODE_3280x1848_28FPS */
+								mclk_khz = "24000";
+								num_lanes = "2";
+								tegra_sinterface = "serial_b";
+								lane_polarity = "6";
+								phy_mode = "DPHY";
+								discontinuous_clk = "yes";
+								dpcm_enable = "false";
+								cil_settletime = "0";
+								active_w = "3280";
+								active_h = "1848";
+								mode_type = "bayer";
+								pixel_phase = "rggb";
+								csi_pixel_bit_depth = "10";
+								readout_orientation = "90";
+								line_length = "3448";
+								inherent_gain = "1";
+								mclk_multiplier = "9.33";
+								pix_clk_hz = "182400000";
+								gain_factor = "16";
+								framerate_factor = "1000000";
+								exposure_factor = "1000000";
+								min_gain_val = "16"; /* 1.00x */
+								max_gain_val = "170"; /* 10.66x */
+								step_gain_val = "1";
+								default_gain = "16"; /* 1.00x */
+								min_hdr_ratio = "1";
+								max_hdr_ratio = "1";
+								min_framerate = "2000000"; /* 2.0 fps */
+								max_framerate = "28000000"; /* 28.0 fps */
+								step_framerate = "1";
+								default_framerate = "28000000"; /* 28.0 fps */
+								min_exp_time = "13"; /* us */
+								max_exp_time = "683709"; /* us */
+								step_exp_time = "1";
+								default_exp_time = "2495"; /* us */
+								embedded_metadata_height = "2";
+							};
+							mode2 { /* IMX219_MODE_1920x1080_30FPS */
+								mclk_khz = "24000";
+								num_lanes = "2";
+								tegra_sinterface = "serial_b";
+								lane_polarity = "6";
+								phy_mode = "DPHY";
+								discontinuous_clk = "yes";
+								dpcm_enable = "false";
+								cil_settletime = "0";
+								active_w = "1920";
+								active_h = "1080";
+								mode_type = "bayer";
+								pixel_phase = "rggb";
+								csi_pixel_bit_depth = "10";
+								readout_orientation = "90";
+								line_length = "3448";
+								inherent_gain = "1";
+								mclk_multiplier = "9.33";
+								pix_clk_hz = "182400000";
+								gain_factor = "16";
+								framerate_factor = "1000000";
+								exposure_factor = "1000000";
+								min_gain_val = "16"; /* 1.00x */
+								max_gain_val = "170"; /* 10.66x */
+								step_gain_val = "1";
+								default_gain = "16"; /* 1.00x */
+								min_hdr_ratio = "1";
+								max_hdr_ratio = "1";
+								min_framerate = "2000000"; /* 2.0 fps */
+								max_framerate = "30000000"; /* 30.0 fps */
+								step_framerate = "1";
+								default_framerate = "30000000"; /* 30.0 fps */
+								min_exp_time = "13"; /* us */
+								max_exp_time = "683709"; /* us */
+								step_exp_time = "1";
+								default_exp_time = "2495"; /* us */
+								embedded_metadata_height = "2";
+							};
+							mode3 { /* IMX219_MODE_1640x1232_30FPS */
+								mclk_khz = "24000";
+								num_lanes = "2";
+								tegra_sinterface = "serial_b";
+								lane_polarity = "6";
+								phy_mode = "DPHY";
+								discontinuous_clk = "yes";
+								dpcm_enable = "false";
+								cil_settletime = "0";
+								active_w = "1640";
+								active_h = "1232";
+								mode_type = "bayer";
+								pixel_phase = "rggb";
+								csi_pixel_bit_depth = "10";
+								readout_orientation = "90";
+								line_length = "3448";
+								inherent_gain = "1";
+								mclk_multiplier = "9.33";
+								pix_clk_hz = "182400000";
+								gain_factor = "16";
+								framerate_factor = "1000000";
+								exposure_factor = "1000000";
+								min_gain_val = "16"; /* 1.00x */
+								max_gain_val = "170"; /* 10.66x */
+								step_gain_val = "1";
+								default_gain = "16"; /* 1.00x */
+								min_hdr_ratio = "1";
+								max_hdr_ratio = "1";
+								min_framerate = "2000000"; /* 2.0 fps */
+								max_framerate = "30000000"; /* 60.0 fps */
+								step_framerate = "1";
+								default_framerate = "30000000"; /* 60.0 fps */
+								min_exp_time = "13"; /* us */
+								max_exp_time = "683709"; /* us */
+								step_exp_time = "1";
+								default_exp_time = "2495"; /* us */
+								embedded_metadata_height = "2";
+							};
+							mode4 { /* IMX219_MODE_1280x720_60FPS */
+								mclk_khz = "24000";
+								num_lanes = "2";
+								tegra_sinterface = "serial_b";
+								lane_polarity = "6";
+								phy_mode = "DPHY";
+								discontinuous_clk = "yes";
+								dpcm_enable = "false";
+								cil_settletime = "0";
+								active_w = "1280";
+								active_h = "720";
+								mode_type = "bayer";
+								pixel_phase = "rggb";
+								csi_pixel_bit_depth = "10";
+								readout_orientation = "90";
+								line_length = "3448";
+								inherent_gain = "1";
+								mclk_multiplier = "9.33";
+								pix_clk_hz = "182400000";
+								gain_factor = "16";
+								framerate_factor = "1000000";
+								exposure_factor = "1000000";
+								min_gain_val = "16"; /* 1.00x */
+								max_gain_val = "170"; /* 10.66x */
+								step_gain_val = "1";
+								default_gain = "16"; /* 1.00x */
+								min_hdr_ratio = "1";
+								max_hdr_ratio = "1";
+								min_framerate = "2000000"; /* 2.0 fps */
+								max_framerate = "60000000"; /* 60.0 fps */
+								step_framerate = "1";
+								default_framerate = "60000000"; /* 60.0 fps */
+								min_exp_time = "13"; /* us */
+								max_exp_time = "683709"; /* us */
+								step_exp_time = "1";
+								default_exp_time = "2495"; /* us */
+								embedded_metadata_height = "2";
+							};
+							ports {
+								#address-cells = <1>;
+								#size-cells = <0>;
+								port@0 {
+									reg = <0>;
+									rbpcv2_imx219_out0: endpoint {
+										port-index = <1>;
+										bus-width = <2>;
+										remote-endpoint = <&rbpcv2_imx219_csi_in0>;
+									};
+								};
+							};
+						};
+					};
+					i2c_1: i2c@1 {
+						imx219_cam1: rbpcv2_imx219_c@10 {
+							compatible = "sony,imx219";
+							/* I2C device address */
+							reg = <0x10>;
+							/* V4L2 device node location */
+							devnode = "video1";
+							/* Physical dimensions of sensor */
+							physical_w = "3.680";
+							physical_h = "2.760";
+							sensor_model = "imx219";
+							use_sensor_mode_id = "true";
+							/**
+							* ==== Modes ====
+							* A modeX node is required to support v4l2 driver
+							* implementation with NVIDIA camera software stack
+							*
+							* == Signal properties ==
+							*
+							* phy_mode = "";
+							* PHY mode used by the MIPI lanes for this device
+							*
+							* tegra_sinterface = "";
+							* CSI Serial interface connected to tegra
+							* Incase of virtual HW devices, use virtual
+							* For SW emulated devices, use host
+							*
+							* pix_clk_hz = "";
+							* Sensor pixel clock used for calculations like exposure and framerate
+							*
+							* readout_orientation = "0";
+							* Based on camera module orientation.
+							* Only change readout_orientation if you specifically
+							* Program a different readout order for this mode
+							*
+							* == Image format Properties ==
+							*
+							* active_w = "";
+							* Pixel active region width
+							*
+							* active_h = "";
+							* Pixel active region height
+							*
+							* pixel_t = "";
+							* The sensor readout pixel pattern
+							*
+							* line_length = "";
+							* Pixel line length (width) for sensor mode.
+							*
+							* == Source Control Settings ==
+							*
+							* Gain factor used to convert fixed point integer to float
+							* Gain range [min_gain/gain_factor, max_gain/gain_factor]
+							* Gain step [step_gain/gain_factor is the smallest step that can be configured]
+							* Default gain [Default gain to be initialized for the control.
+							*     use min_gain_val as default for optimal results]
+							* Framerate factor used to convert fixed point integer to float
+							* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
+							* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
+							* Default Framerate [Default framerate to be initialized for the control.
+							*     use max_framerate to get required performance]
+							* Exposure factor used to convert fixed point integer to float
+							* For convenience use 1 sec = 1000000us as conversion factor
+							* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
+							* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
+							* Default Exposure Time [Default exposure to be initialized for the control.
+							*     Set default exposure based on the default_framerate for optimal exposure settings]
+							*
+							* gain_factor = ""; (integer factor used for floating to fixed point conversion)
+							* min_gain_val = ""; (ceil to integer)
+							* max_gain_val = ""; (ceil to integer)
+							* step_gain_val = ""; (ceil to integer)
+							* default_gain = ""; (ceil to integer)
+							* Gain limits for mode
+							*
+							* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
+							* min_exp_time = ""; (ceil to integer)
+							* max_exp_time = ""; (ceil to integer)
+							* step_exp_time = ""; (ceil to integer)
+							* default_exp_time = ""; (ceil to integer)
+							* Exposure Time limits for mode (sec)
+							*
+							* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
+							* min_framerate = ""; (ceil to integer)
+							* max_framerate = ""; (ceil to integer)
+							* step_framerate = ""; (ceil to integer)
+							* default_framerate = ""; (ceil to integer)
+							* Framerate limits for mode (fps)
+							*
+							* embedded_metadata_height = "";
+							* Sensor embedded metadata height in units of rows.
+							* If sensor does not support embedded metadata value should be 0.
+							*/
+							mode0 { /* IMX219_MODE_3280x2464_21FPS */
+								mclk_khz = "24000";
+								num_lanes = "2";
+								tegra_sinterface = "serial_c";
+								phy_mode = "DPHY";
+								discontinuous_clk = "yes";
+								dpcm_enable = "false";
+								cil_settletime = "0";
+								active_w = "3280";
+								active_h = "2464";
+								mode_type = "bayer";
+								pixel_phase = "rggb";
+								csi_pixel_bit_depth = "10";
+								readout_orientation = "90";
+								line_length = "3448";
+								inherent_gain = "1";
+								mclk_multiplier = "9.33";
+								pix_clk_hz = "182400000";
+								gain_factor = "16";
+								framerate_factor = "1000000";
+								exposure_factor = "1000000";
+								min_gain_val = "16"; /* 1.00x */
+								max_gain_val = "170"; /* 10.66x */
+								step_gain_val = "1";
+								default_gain = "16"; /* 1.00x */
+								min_hdr_ratio = "1";
+								max_hdr_ratio = "1";
+								min_framerate = "2000000"; /* 2.0 fps */
+								max_framerate = "21000000"; /* 21.0 fps */
+								step_framerate = "1";
+								default_framerate = "21000000"; /* 21.0 fps */
+								min_exp_time = "13"; /* us */
+								max_exp_time = "683709"; /* us */
+								step_exp_time = "1";
+								default_exp_time = "2495"; /* us */
+								embedded_metadata_height = "2";
+							};
+							mode1 { /* IMX219_MODE_3280x1848_28FPS */
+								mclk_khz = "24000";
+								num_lanes = "2";
+								tegra_sinterface = "serial_c";
+								phy_mode = "DPHY";
+								discontinuous_clk = "yes";
+								dpcm_enable = "false";
+								cil_settletime = "0";
+								active_w = "3280";
+								active_h = "1848";
+								mode_type = "bayer";
+								pixel_phase = "rggb";
+								csi_pixel_bit_depth = "10";
+								readout_orientation = "90";
+								line_length = "3448";
+								inherent_gain = "1";
+								mclk_multiplier = "9.33";
+								pix_clk_hz = "182400000";
+								gain_factor = "16";
+								framerate_factor = "1000000";
+								exposure_factor = "1000000";
+								min_gain_val = "16"; /* 1.00x */
+								max_gain_val = "170"; /* 10.66x */
+								step_gain_val = "1";
+								default_gain = "16"; /* 1.00x */
+								min_hdr_ratio = "1";
+								max_hdr_ratio = "1";
+								min_framerate = "2000000"; /* 2.0 fps */
+								max_framerate = "28000000"; /* 28.0 fps */
+								step_framerate = "1";
+								default_framerate = "28000000"; /* 28.0 fps */
+								min_exp_time = "13"; /* us */
+								max_exp_time = "683709"; /* us */
+								step_exp_time = "1";
+								default_exp_time = "2495"; /* us */
+								embedded_metadata_height = "2";
+							};
+							mode2 { /* IMX219_MODE_1920x1080_30FPS */
+								mclk_khz = "24000";
+								num_lanes = "2";
+								tegra_sinterface = "serial_c";
+								phy_mode = "DPHY";
+								discontinuous_clk = "yes";
+								dpcm_enable = "false";
+								cil_settletime = "0";
+								active_w = "1920";
+								active_h = "1080";
+								mode_type = "bayer";
+								pixel_phase = "rggb";
+								csi_pixel_bit_depth = "10";
+								readout_orientation = "90";
+								line_length = "3448";
+								inherent_gain = "1";
+								mclk_multiplier = "9.33";
+								pix_clk_hz = "182400000";
+								gain_factor = "16";
+								framerate_factor = "1000000";
+								exposure_factor = "1000000";
+								min_gain_val = "16"; /* 1.00x */
+								max_gain_val = "170"; /* 10.66x */
+								step_gain_val = "1";
+								default_gain = "16"; /* 1.00x */
+								min_hdr_ratio = "1";
+								max_hdr_ratio = "1";
+								min_framerate = "2000000"; /* 2.0 fps */
+								max_framerate = "30000000"; /* 30.0 fps */
+								step_framerate = "1";
+								default_framerate = "30000000"; /* 30.0 fps */
+								min_exp_time = "13"; /* us */
+								max_exp_time = "683709"; /* us */
+								step_exp_time = "1";
+								default_exp_time = "2495"; /* us */
+								embedded_metadata_height = "2";
+							};
+							mode3 { /* IMX219_MODE_1640x1232_30FPS */
+								mclk_khz = "24000";
+								num_lanes = "2";
+								tegra_sinterface = "serial_c";
+								phy_mode = "DPHY";
+								discontinuous_clk = "yes";
+								dpcm_enable = "false";
+								cil_settletime = "0";
+								active_w = "1640";
+								active_h = "1232";
+								mode_type = "bayer";
+								pixel_phase = "rggb";
+								csi_pixel_bit_depth = "10";
+								readout_orientation = "90";
+								line_length = "3448";
+								inherent_gain = "1";
+								mclk_multiplier = "9.33";
+								pix_clk_hz = "182400000";
+								gain_factor = "16";
+								framerate_factor = "1000000";
+								exposure_factor = "1000000";
+								min_gain_val = "16"; /* 1.00x */
+								max_gain_val = "170"; /* 10.66x */
+								step_gain_val = "1";
+								default_gain = "16"; /* 1.00x */
+								min_hdr_ratio = "1";
+								max_hdr_ratio = "1";
+								min_framerate = "2000000"; /* 2.0 fps */
+								max_framerate = "30000000"; /* 60.0 fps */
+								step_framerate = "1";
+								default_framerate = "30000000"; /* 60.0 fps */
+								min_exp_time = "13"; /* us */
+								max_exp_time = "683709"; /* us */
+								step_exp_time = "1";
+								default_exp_time = "2495"; /* us */
+								embedded_metadata_height = "2";
+							};
+							mode4 { /* IMX219_MODE_1280x720_60FPS */
+								mclk_khz = "24000";
+								num_lanes = "2";
+								tegra_sinterface = "serial_c";
+								phy_mode = "DPHY";
+								discontinuous_clk = "yes";
+								dpcm_enable = "false";
+								cil_settletime = "0";
+								active_w = "1280";
+								active_h = "720";
+								mode_type = "bayer";
+								pixel_phase = "rggb";
+								csi_pixel_bit_depth = "10";
+								readout_orientation = "90";
+								line_length = "3448";
+								inherent_gain = "1";
+								mclk_multiplier = "9.33";
+								pix_clk_hz = "182400000";
+								gain_factor = "16";
+								framerate_factor = "1000000";
+								exposure_factor = "1000000";
+								min_gain_val = "16"; /* 1.00x */
+								max_gain_val = "170"; /* 10.66x */
+								step_gain_val = "1";
+								default_gain = "16"; /* 1.00x */
+								min_hdr_ratio = "1";
+								max_hdr_ratio = "1";
+								min_framerate = "2000000"; /* 2.0 fps */
+								max_framerate = "60000000"; /* 60.0 fps */
+								step_framerate = "1";
+								default_framerate = "60000000"; /* 60.0 fps */
+								min_exp_time = "13"; /* us */
+								max_exp_time = "683709"; /* us */
+								step_exp_time = "1";
+								default_exp_time = "2495"; /* us */
+								embedded_metadata_height = "2";
+							};
+							ports {
+								#address-cells = <1>;
+								#size-cells = <0>;
+								port@0 {
+									reg = <0>;
+									rbpcv2_imx219_out1: endpoint {
+										port-index = <2>;
+										bus-width = <2>;
+										remote-endpoint = <&rbpcv2_imx219_csi_in1>;
+									};
+								};
+							};
+						};
+					};
+				};
+				lens_imx219@RBPCV2 {
+					min_focus_distance = "0.0";
+					hyper_focal = "0.0";
+					focal_length = "3.04";
+					f_number = "2.0";
+					aperture = "0.0";
+				};
+			};
+
+			tcp: tegra-camera-platform {
+				compatible = "nvidia, tegra-camera-platform";
+
+				/**
+				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
+				 * The first part is the camera_board_id for the module; if the module is in a FFD
+				 * platform, then use the platform name for this part.
+				 * The second part contains the position of the module, ex. "rear" or "front".
+				 * The third part contains the last 6 characters of a part number which is found
+				 * in the module's specsheet from the vendor.
+				 */
+				modules {
+					cam_module0: module0 {
+						badge = "jakku_front_RBP194";
+						position = "front";
+						orientation = "1";
+						cam_module0_drivernode0: drivernode0 {
+							pcl_id = "v4l2_sensor";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/cam_i2cmux/i2c@0/rbpcv2_imx219_a@10";
+						};
+						cam_module0_drivernode1: drivernode1 {
+							pcl_id = "v4l2_lens";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/lens_imx219@RBPCV2";
+						};
+					};
+					cam_module1: module1 {
+						badge = "jakku_rear_RBP194";
+						position = "rear";
+						orientation = "1";
+						cam_module1_drivernode0: drivernode0 {
+							pcl_id = "v4l2_sensor";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/cam_i2cmux/i2c@1/rbpcv2_imx219_c@10";
+						};
+						cam_module1_drivernode1: drivernode1 {
+							pcl_id = "v4l2_lens";
+							sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/lens_imx219@RBPCV2/";
+						};
+					};
+				};
+			};
+		};
+	};
+};

overlay/tegra234-carveouts.dts

@@ -1,10 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 /dts-v1/;
 /plugin/;
 
 / {
+	overlay-name = "Tegra234 Carveouts Overlay";
+
 	fragment@0 {
 		target-path = "/";
 		__overlay__ {
@@ -16,6 +18,7 @@
 
 				vpr: vpr-carveout {
 					compatible = "nvidia,vpr-carveout";
+					no-map;
 					status = "okay";
 				};
 

overlay/tegra234-dcb-p3737-0000-p3701-0000.dtsi

@@ -1,540 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
-
-/ {
-	fragment-t234-dcb@0 {
-		target-path = "/";
-		__overlay__ {
-
-			display@13800000 {
-				nvidia,dcb-image = [
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-			};
-		};
-	};
-};

overlay/tegra234-dcb-p3767-0000-hdmi.dts

@@ -0,0 +1,557 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	fragment-t234-dcb@0 {
+		target-path = "/";
+		__overlay__ {
+			display@13800000 {
+				nvidia,dcb-image = [
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+					e0 e0 e0 e0 10 10 10 10 6e 2c c1 61 40 e0 e0 e0
+					e0 10 10 10 10 71 5f 0c c1 61 60 00 01 40 ff 40
+					00 00 00 00 40 65 61 80 fe bf 00 bf 3a 00 03 5b
+					14 1c 72 71 3a 07 01 38 6e 40 c1 61 60 fe ff ff
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+					0c c1 61 60 fe ff 00 ff 00 00 00 00 6e 30 c1 61
+					40 f0 ff ff ff 00 00 00 00 6e b0 c1 61 40 f0 ff
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+					00 80 00 6e 00 23 61 40 ff ff fc ff 00 00 02 00
+					74 05 00 6e 14 c0 61 40 ff ff ff f2 00 00 00 0d
+					74 05 00 6e 14 c0 61 40 ff ff bf ff 00 00 40 00
+					74 05 00 6e 14 c0 61 40 f7 ff ff ff 08 00 00 00
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+					61 40 ff ff ff 81 00 03 00 08 6e 00 23 61 40 ff
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+					07 01 00 00 01 ef 00 71 58 40 c0 61 40 10 00 00
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+					00 00 32 10 80 00 96 90 80 00 00 80 80 00 00 80
+					80 00 00 80 80 00 00 80 80 00 00 80 80 00 71 42
+					15 02 07 13 04 03 0a 04 28 23 28 23 01 04 04 06
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+					0f 04 2f 21 06 28 00 04 32 14 06 3c 00 06 14 00
+					02 19 0a 03 1e 14 04 2b 28 06 1e 00 03 25 0f 04
+					2f 21 06 28 00 04 32 14 06 3c 00 06 0f 00 02 16
+					09 03 1d 0e 04 27 12 06 17 00 03 21 09 04 27 0e
+					06 1f 00 04 27 09 06 27 00 06 62 1e 00 00 f2 1e
+					00 00 82 1f 00 00 12 20 00 00 a2 20 00 00 32 21
+					00 00 10 08 00 00 00 11 08 00 1e 00 00 00 00 01
+					05 05 00 40 00 00 00 00 00 30 00 14 00 00 00 00
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+					00 01 05 05 00 40 00 00 00 00 00 30 00 0c 00 00
+					00 00 01 05 05 00 40 00 00 00 00 00 30 00 0a 00
+					00 00 00 01 05 05 00 40 00 00 00 00 00 30 00 09
+					00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 00
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+					00 06 00 00 00 00 01 05 05 00 40 00 00 00 00 00
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+					05 05 00 00 00 00 00 00 00 00 00 14 00 00 00 00
+					00 05 05 00 00 00 00 00 00 00 00 00 10 00 00 00
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+					00 00 03 00 01 00 50 00 00 00 00 00 00 00 0a 00
+					00 00 00 00 05 05 00 00 00 00 00 00 00 00 00 09
+					00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 00
+					08 00 00 00 00 03 00 01 00 40 00 00 00 00 00 00
+					00 06 00 00 00 00 00 05 05 00 00 00 00 00 00 00
+					00 00 10 08 00 00 00 11 08 00 1e 00 00 00 00 00
+					05 05 00 00 00 00 00 00 00 00 00 14 00 00 00 00
+					00 05 05 00 00 00 00 00 00 00 00 00 10 00 00 00
+					00 03 00 01 00 50 00 00 00 00 00 00 00 0c 00 00
+					00 00 03 00 01 00 50 00 00 00 00 00 00 00 0a 00
+					00 00 00 00 05 05 00 00 00 00 00 00 00 00 00 09
+					00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 00
+					08 00 00 00 00 03 00 01 00 40 00 00 00 00 00 00
+					00 06 00 00 00 00 00 05 05 00 00 00 00 00 00 00
+					00 00 10 08 00 00 00 11 08 00 1e 00 00 00 00 00
+					05 05 00 00 00 00 00 00 00 00 00 14 00 00 00 00
+					00 05 05 00 00 00 00 00 00 00 00 00 10 00 00 00
+					00 03 00 01 00 50 00 00 00 00 00 00 00 0c 00 00
+					00 00 03 00 01 00 50 00 00 00 00 00 00 00 0a 00
+					00 00 00 00 05 05 00 00 00 00 00 00 00 00 00 09
+					00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 00
+					08 00 00 00 00 03 00 01 00 40 00 00 00 00 00 00
+					00 06 00 00 00 00 00 05 05 00 00 00 00 00 00 00
+					00 00 10 08 00 00 00 11 08 00 1e 00 00 00 00 00
+					05 05 00 00 00 00 00 00 00 00 00 14 00 00 00 00
+					00 05 05 00 00 00 00 00 00 00 00 00 10 00 00 00
+					00 03 00 01 00 50 00 00 00 00 00 00 00 0c 00 00
+					00 00 03 00 01 00 50 00 00 00 00 00 00 00 0a 00
+					00 00 00 00 05 05 00 00 00 00 00 00 00 00 00 09
+					00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 00
+					08 00 00 00 00 03 00 01 00 40 00 00 00 00 00 00
+					00 06 00 00 00 00 00 05 05 00 00 00 00 00 00 00
+					00 00 10 08 00 00 00 11 08 00 1e 00 00 00 00 00
+					05 05 00 00 00 00 00 00 00 00 00 14 00 00 00 00
+					00 05 05 00 00 00 00 00 00 00 00 00 10 00 00 00
+					00 03 00 01 00 50 00 00 00 00 00 00 00 0c 00 00
+					00 00 03 00 01 00 50 00 00 00 00 00 00 00 0a 00
+					00 00 00 00 05 05 00 00 00 00 00 00 00 00 00 09
+					00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 00
+					08 00 00 00 00 03 00 01 00 40 00 00 00 00 00 00
+					00 06 00 00 00 00 00 05 05 00 00 00 00 00 00 00
+					00 00 ];
+			};
+		};
+	};
+};

overlay/tegra234-jetson.dts

@@ -1,334 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
-
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/clock/tegra234-clock.h>
-#include <dt-bindings/gpio/tegra234-gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/memory/tegra234-mc.h>
-#include <dt-bindings/power/tegra234-powergate.h>
-#include <dt-bindings/reset/tegra234-reset.h>
-#include "tegra234-soc-display-overlay.dtsi"
-#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
-
-/ {
-	overlay-name = "Tegra234 Jetson Overlay";
-	compatible = "nvidia,tegra234";
-
-	fragment@0 {
-		target-path = "/bus@0/host1x@13e00000";
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			interrupt-parent = <&gic>;
-
-			ranges = <0x14800000 0x14800000 0x02000000>,
-				 <0x24700000 0x24700000 0x00080000>;
-
-			nvjpg@15380000 {
-				compatible = "nvidia,tegra234-nvjpg";
-				reg = <0x15380000 0x00040000>;
-				clocks = <&bpmp TEGRA234_CLK_NVJPG>;
-				clock-names = "nvjpg";
-				resets = <&bpmp TEGRA234_RESET_NVJPG>;
-				reset-names = "nvjpg";
-
-				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGA>;
-				interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPGSRD &emc>,
-						<&mc TEGRA234_MEMORY_CLIENT_NVJPGSWR &emc>;
-				interconnect-names = "dma-mem", "write";
-				iommus = <&smmu_niso1 TEGRA234_SID_NVJPG>;
-				dma-coherent;
-
-				nvidia,host1x-class = <0xc0>;
-			};
-
-			nvdec@15480000 {
-				compatible = "nvidia,tegra234-nvdec";
-				reg = <0x15480000 0x00040000>;
-				clocks = <&bpmp TEGRA234_CLK_NVDEC>,
-				         <&bpmp TEGRA234_CLK_FUSE>,
-				         <&bpmp TEGRA234_CLK_TSEC_PKA>;
-				clock-names = "nvdec", "fuse", "tsec_pka";
-				resets = <&bpmp TEGRA234_RESET_NVDEC>;
-				reset-names = "nvdec";
-				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
-				interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
-				                <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
-				interconnect-names = "dma-mem", "write";
-				iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
-				dma-coherent;
-
-				nvidia,memory-controller = <&mc>;
-				status = "okay";
-			};
-
-			nvenc@154c0000 {
-				compatible = "nvidia,tegra234-nvenc";
-				reg = <0x154c0000 0x00040000>;
-				clocks = <&bpmp TEGRA234_CLK_NVENC>;
-				clock-names = "nvenc";
-				resets = <&bpmp TEGRA234_RESET_NVENC>;
-				reset-names = "nvenc";
-
-				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVENC>;
-				interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVENCSRD &emc>,
-						<&mc TEGRA234_MEMORY_CLIENT_NVENCSWR &emc>;
-				interconnect-names = "dma-mem", "write";
-				iommus = <&smmu_niso0 TEGRA234_SID_NVENC>;
-				dma-coherent;
-			};
-
-			nvjpg@15540000 {
-				compatible = "nvidia,tegra234-nvjpg";
-				reg = <0x15540000 0x00040000>;
-				clocks = <&bpmp TEGRA234_CLK_NVJPG1>;
-				clock-names = "nvjpg";
-				resets = <&bpmp TEGRA234_RESET_NVJPG1>;
-				reset-names = "nvjpg";
-
-				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGB>;
-				interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPG1SRD &emc>,
-						<&mc TEGRA234_MEMORY_CLIENT_NVJPG1SWR &emc>;
-				interconnect-names = "dma-mem", "write";
-				iommus = <&smmu_niso0 TEGRA234_SID_NVJPG1>;
-				dma-coherent;
-
-				nvidia,host1x-class = <0x07>;
-			};
-
-			nvdla0: nvdla0@15880000 {
-				compatible = "nvidia,tegra234-nvdla";
-				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAA>;
-				reg = <0x15880000 0x00040000>;
-				interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
-
-				resets = <&bpmp TEGRA234_RESET_DLA0>;
-				clocks = <&bpmp TEGRA234_CLK_DLA0_CORE>,
-					 <&bpmp TEGRA234_CLK_DLA0_FALCON>;
-				clock-names = "nvdla0", "nvdla0_flcn";
-
-				interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA0RDA &emc>,
-						<&mc TEGRA234_MEMORY_CLIENT_DLA0FALRDB &emc>,
-						<&mc TEGRA234_MEMORY_CLIENT_DLA0WRA &emc>,
-						<&mc TEGRA234_MEMORY_CLIENT_DLA0FALWRB &emc>;
-				interconnect-names = "dma-mem", "read-1", "write", "write-1";
-				iommus = <&smmu_niso1 TEGRA234_SID_NVDLA0>;
-				dma-coherent;
-				status = "okay";
-			};
-
-			nvdla1: nvdla1@158c0000 {
-				compatible = "nvidia,tegra234-nvdla";
-				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAB>;
-				reg = <0x158c0000 0x00040000>;
-				interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
-
-				resets = <&bpmp TEGRA234_RESET_DLA1>;
-				clocks = <&bpmp TEGRA234_CLK_DLA1_CORE>,
-					 <&bpmp TEGRA234_CLK_DLA1_FALCON>;
-				clock-names = "nvdla1", "nvdla1_flcn";
-
-				interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA1RDA &emc>,
-						<&mc TEGRA234_MEMORY_CLIENT_DLA1FALRDB &emc>,
-						<&mc TEGRA234_MEMORY_CLIENT_DLA1WRA &emc>,
-						<&mc TEGRA234_MEMORY_CLIENT_DLA1FALWRB &emc>;
-				interconnect-names = "dma-mem", "read-1", "write", "write-1";
-				iommus = <&smmu_niso0 TEGRA234_SID_NVDLA1>;
-				dma-coherent;
-				status = "okay";
-			};
-
-			ofa@15a50000 {
-				compatible = "nvidia,tegra234-ofa";
-				reg = <0x15a50000 0x00040000>;
-				clocks = <&bpmp TEGRA234_CLK_OFA>;
-				clock-names = "ofa";
-				resets = <&bpmp TEGRA234_RESET_OFA>;
-				reset-names = "ofa";
-
-				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_OFA>;
-				interconnects = <&mc TEGRA234_MEMORY_CLIENT_OFAR &emc>,
-						<&mc TEGRA234_MEMORY_CLIENT_OFAW &emc>;
-				interconnect-names = "dma-mem", "write";
-				iommus = <&smmu_niso0 TEGRA234_SID_OFA>;
-				dma-coherent;
-			};
-
-			pva0: pva0@16000000 {
-				compatible = "nvidia,tegra234-pva";
-				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PVA>;
-				reg = <0x16000000 0x800000>,
-				      <0x24700000 0x080000>;
-				interrupts = <0 234 0x04>,
-					<0 432 0x04>,
-					<0 433 0x04>,
-					<0 434 0x04>,
-					<0 435 0x04>,
-					<0 436 0x04>,
-					<0 437 0x04>,
-					<0 438 0x04>,
-					<0 439 0x04>;
-				resets = <&bpmp TEGRA234_RESET_PVA0_ALL>;
-				clocks = <&bpmp TEGRA234_CLK_PVA0_CPU_AXI>,
-					 <&bpmp TEGRA234_CLK_NAFLL_PVA0_VPS>,
-					 <&bpmp TEGRA234_CLK_PVA0_VPS>;
-				clock-names = "axi", "vps0", "vps1";
-
-				iommus = <&smmu_niso1 TEGRA234_SID_PVA0>;
-				dma-coherent;
-				status = "okay";
-
-				pva0_ctx0n1: pva0_niso1_ctx0 {
-					compatible = "nvidia,pva-tegra186-iommu-context";
-					iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM0>;
-					dma-coherent;
-					status = "okay";
-				};
-
-				pva0_ctx1n1: pva0_niso1_ctx1 {
-					compatible = "nvidia,pva-tegra186-iommu-context";
-					iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM1>;
-					dma-coherent;
-					status = "okay";
-				};
-
-				pva0_ctx2n1: pva0_niso1_ctx2 {
-					compatible = "nvidia,pva-tegra186-iommu-context";
-					iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM2>;
-					dma-coherent;
-					status = "okay";
-				};
-
-				pva0_ctx3n1: pva0_niso1_ctx3 {
-					compatible = "nvidia,pva-tegra186-iommu-context";
-					iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM3>;
-					dma-coherent;
-					status = "okay";
-				};
-
-				pva0_ctx4n1: pva0_niso1_ctx4 {
-					compatible = "nvidia,pva-tegra186-iommu-context";
-					iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM4>;
-					dma-coherent;
-					status = "okay";
-				};
-
-				pva0_ctx5n1: pva0_niso1_ctx5 {
-					compatible = "nvidia,pva-tegra186-iommu-context";
-					iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM5>;
-					dma-coherent;
-					status = "okay";
-				};
-
-				pva0_ctx6n1: pva0_niso1_ctx6 {
-					compatible = "nvidia,pva-tegra186-iommu-context";
-					iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM6>;
-					dma-coherent;
-					status = "okay";
-				};
-
-				pva0_ctx7n1: pva0_niso1_ctx7 {
-					compatible = "nvidia,pva-tegra186-iommu-context";
-					iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM7>;
-					dma-coherent;
-					status = "okay";
-				};
-			};
-		};
-	};
-
-	fragment@1 {
-		target-path = "/bus@0";
-		__overlay__ {
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			gpu@17000000 {
-				compatible = "nvidia,ga10b";
-				reg = <0x17000000 0x01000000>,
-				      <0x18000000 0x01000000>,
-				      <0x03b41000 0x00001000>;
-				interrupt-parent = <&gic>;
-				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "stall0", "stall1", "stall2", "nonstall";
-				power-domains = <&bpmp TEGRA234_POWER_DOMAIN_GPU>;
-				clocks = <&bpmp TEGRA234_CLK_GPUSYS>,
-					 <&bpmp TEGRA234_CLK_GPC0CLK>,
-					 <&bpmp TEGRA234_CLK_GPC1CLK>;
-				clock-names = "sysclk", "gpc0clk", "gpc1clk";
-				resets = <&bpmp TEGRA234_RESET_GPU>;
-				dma-coherent;
-
-				nvidia,bpmp = <&bpmp>;
-
-				status = "okay";
-			};
-
-			tachometer@39c0000 {
-				compatible = "nvidia,pwm-tegra234-tachometer";
-				reg = <0x039c0000 0x10>;
-				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
-				#pwm-cells = <2>;
-				clocks = <&bpmp TEGRA234_CLK_TACH0>;
-				clock-names = "tach";
-				resets = <&bpmp TEGRA234_RESET_TACH0>;
-				reset-names = "tach";
-				pulse-per-rev = <2>;
-				capture-window-length = <2>;
-				upper-threshold = <0xfffff>;
-				lower-threshold = <0x0>;
-			};
-		};
-	};
-
-	fragment@2 {
-		target-path = "/";
-		__overlay__ {
-			reserved-memory {
-				#address-cells = <2>;
-				#size-cells = <2>;
-				ranges;
-
-				linux,cma { /* Needed for nvgpu comptags */
-					compatible = "shared-dma-pool";
-					reusable;
-					size = <0x0 0x10000000>; /* 256MB */
-					alignment = <0x0 0x10000>;
-					linux,cma-default;
-					status = "okay";
-				};
-			};
-
-			dce@d800000 {
-				status = "okay";
-			};
-
-			display@13800000 {
-				status = "okay";
-			};
-		};
-	};
-
-	fragment@3 {
-		target-path = "/bus@0";
-		board_config {
-			ids = "3737-0000-TS1","3737-0000-TS2","3737-0000-TS3","3737-0000-EB1","3737-0000-EB2","3737-0000-EB3","3737-0000-000","3737-0000-100","3737-0000-200";
-		};
-		__overlay__ {
-			i2c@c240000 {
-				ucsi_ccg@8 {
-					interrupt-parent = <&gpio_aon>;
-					interrupts = <TEGRA234_AON_GPIO(BB, 2) IRQ_TYPE_LEVEL_LOW>;
-				};
-			};
-		};
-	};
-};

overlay/tegra234-p3701-0000.dtsi

@@ -1,161 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
-
-#include "tegra234-p3737-0000-camera-imx274-dual.dtsi"
-/ {
-	fragment-t234-p3701-0000@0 {
-		target-path = "/";
-		__overlay__ {
-			bus@0 {
-				i2c@c240000 {
-					ina3221@40 {
-						compatible = "ti,ina3221";
-						reg = <0x40>;
-						#address-cells = <1>;
-						#size-cells = <0>;
-						#io-channel-cells = <1>;
-						channel@0 {
-							reg = <0x0>;
-							label = "VDD_GPU_SOC";
-							shunt-resistor-micro-ohms = <2000>;
-						};
-						channel@1 {
-							reg = <0x1>;
-							label = "VDD_CPU_CV";
-							shunt-resistor-micro-ohms = <2000>;
-						};
-						channel@2 {
-							reg = <0x2>;
-							label = "VIN_SYS_5V0";
-							shunt-resistor-micro-ohms = <2000>;
-							summation-bypass;
-						};
-					};
-
-					ina3221@41 {
-						compatible = "ti,ina3221";
-						reg = <0x41>;
-						#address-cells = <1>;
-						#size-cells = <0>;
-						#io-channel-cells = <1>;
-						channel@0 {
-							reg = <0x0>;
-							label = "NC";
-						};
-						channel@1 {
-							reg = <0x1>;
-							label = "VDDQ_VDD2_1V8AO";
-							shunt-resistor-micro-ohms = <2000>;
-						};
-						channel@2 {
-							reg = <0x2>;
-							label = "NC";
-						};
-					};
-				};
-
-				spi@3270000 {
-					flash@0 {
-						spi-max-frequency = <51000000>;
-						spi-tx-bus-width = <1>;
-						spi-rx-bus-width = <1>;
-					};
-				};
-			};
-
-			hdr40_vdd_3v3: regulator@3 {
-				compatible = "regulator-fixed";
-				reg = <3>;
-				regulator-name = "vdd-3v3-sys";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-			};
-
-			bpmp {
-				i2c {
-					vrs@3c {
-						compatible = "nvidia,vrs-pseq";
-						reg = <0x3c>;
-						interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-						interrupt-controller;
-						#interrupt-cells = <3>;
-						status = "okay";
-					};
-
-					tegra_tmp451: thermal-sensor@4c {
-						compatible = "ti,tmp451";
-						reg = <0x4c>;
-						vcc-supply = <&vdd_1v8_ao>;
-						#thermal-sensor-cells = <1>;
-						status = "okay";
-					};
-
-					vrs11_1@20 {
-						compatible = "nvidia,vrs11";
-						reg = <0x20>;
-						rail-name-loopA = "GPU";
-						rail-name-loopB = "CPU";
-					};
-
-					vrs11_2@22 {
-						compatible = "nvidia,vrs11";
-						reg = <0x22>;
-						rail-name-loopA = "SOC";
-						rail-name-loopB = "CV";
-					};
-				};
-			};
-
-			thermal-zones {
-				tboard-thermal {
-					polling-delay = <1000>;
-					polling-delay-passive = <1000>;
-					thermal-sensors = <&tegra_tmp451 0>;
-					status = "okay";
-				};
-
-				tdiode-thermal {
-					polling-delay = <1000>;
-					polling-delay-passive = <1000>;
-					thermal-sensors = <&tegra_tmp451 1>;
-					status = "okay";
-				};
-			};
-
-			eeprom-manager {
-				bus@0 {
-					i2c-bus = <&gen1_i2c>;
-					eeprom@0 {
-						slave-address = <0x50>;
-						label = "cvm";
-					};
-				};
-			};
-
-			reserved-memory {
-				linux,cma { /* Needed for nvgpu comptags */
-					compatible = "shared-dma-pool";
-					reusable;
-					size = <0x0 0x10000000>; /* 256MB */
-					alignment = <0x0 0x10000>;
-					linux,cma-default;
-					status = "okay";
-				};
-			};
-		};
-	};
-
-	fragment-t234-p3701-0000@1 {
-		target-path = "/";
-		board_config {
-			ids = "3701-0005-*","3701-0008-*";
-		};
-		__overlay__ {
-			reserved-memory {
-				linux,cma { /* Needed for nvgpu comptags */
-					size = <0x0 0x20000000>; /* 512MB */
-				};
-			};
-		};
-	};
-};

overlay/tegra234-p3701-0008.dtsi

@@ -1,160 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
-
-/ {
-	fragment-t234-p3701-0008@0 {
-		target-path = "/";
-		__overlay__ {
-			bus@0 {
-				i2c@c240000 {
-					ina3221@40 {
-						compatible = "ti,ina3221";
-						reg = <0x40>;
-						#address-cells = <1>;
-						#size-cells = <0>;
-						#io-channel-cells = <1>;
-						channel@0 {
-							reg = <0x0>;
-							label = "VDD_GPU_SOC";
-							shunt-resistor-micro-ohms = <2000>;
-						};
-						channel@1 {
-							reg = <0x1>;
-							label = "VDD_CPU_CV";
-							shunt-resistor-micro-ohms = <2000>;
-						};
-						channel@2 {
-							reg = <0x2>;
-							label = "VIN_SYS_5V0";
-							shunt-resistor-micro-ohms = <2000>;
-							summation-bypass;
-						};
-					};
-
-					ina3221@41 {
-						compatible = "ti,ina3221";
-						reg = <0x41>;
-						#address-cells = <1>;
-						#size-cells = <0>;
-						#io-channel-cells = <1>;
-						channel@0 {
-							reg = <0x0>;
-							label = "NC";
-						};
-						channel@1 {
-							reg = <0x1>;
-							label = "VDDQ_VDD2_1V8AO";
-							shunt-resistor-micro-ohms = <2000>;
-						};
-						channel@2 {
-							reg = <0x2>;
-							label = "NC";
-						};
-					};
-				};
-
-				i2c@c250000 {
-					ina3221@41 {
-						compatible = "ti,ina3221";
-						reg = <0x41>;
-						#address-cells = <1>;
-						#size-cells = <0>;
-						#io-channel-cells = <1>;
-						channel@0 {
-							reg = <0x0>;
-							label = "CVB_ATX_12V";
-							shunt-resistor-micro-ohms = <2000>;
-						};
-						channel@1 {
-							reg = <0x1>;
-							label = "CVB_ATX_3V3";
-							shunt-resistor-micro-ohms = <2000>;
-						};
-						channel@2 {
-							reg = <0x2>;
-							label = "CVB_ATX_5V";
-							shunt-resistor-micro-ohms = <2000>;
-						};
-					};
-
-					 ina219@44 {
-						compatible = "ti,ina219";
-						reg = <0x44>;
-						shunt-resistor = <2000>;
-						label = "CVB_ATX_12V_8P";
-					};
-				};
-
-				spi@3270000 {
-					flash@0 {
-						spi-max-frequency = <51000000>;
-						spi-tx-bus-width = <1>;
-						spi-rx-bus-width = <1>;
-					};
-				};
-			};
-
-			bpmp {
-				i2c {
-					vrs@3c {
-						compatible = "nvidia,vrs-pseq";
-						reg = <0x3c>;
-						interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
-						interrupt-controller;
-						#interrupt-cells = <3>;
-						status = "okay";
-					};
-
-					vrs11_1@20 {
-						compatible = "nvidia,vrs11";
-						reg = <0x20>;
-						rail-name-loopA = "GPU";
-						rail-name-loopB = "CPU";
-					};
-
-					vrs11_2@22 {
-						compatible = "nvidia,vrs11";
-						reg = <0x22>;
-						rail-name-loopA = "SOC";
-						rail-name-loopB = "CV";
-					};
-
-					tegra_tmp451: thermal-sensor@4c {
-						compatible = "ti,tmp451";
-						reg = <0x4c>;
-						vcc-supply = <&vdd_1v8_ao>;
-						#thermal-sensor-cells = <1>;
-						status = "okay";
-					};
-
-				};
-			};
-
-			eeprom-manager {
-				bus@0 {
-					i2c-bus = <&gen1_i2c>;
-					eeprom@0 {
-						slave-address = <0x50>;
-						label = "cvm";
-					};
-				};
-			};
-
-			thermal-zones {
-				tboard-thermal {
-					polling-delay = <1000>;
-					polling-delay-passive = <1000>;
-					thermal-sensors = <&tegra_tmp451 0>;
-					status = "okay";
-				};
-
-				tdiode-thermal {
-					polling-delay = <1000>;
-					polling-delay-passive = <1000>;
-					thermal-sensors = <&tegra_tmp451 1>;
-					status = "okay";
-				};
-			};
-		};
-	};
-};

overlay/tegra234-p3737-0000+p3701-0000-as-p3701-0004.dts

@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	overlay-name = "Tegra234 p3701-0000-as-p3701-0004 Emulation Overlay";
+
+	fragment-t234-p3701-0000-as-p3701-0004@0 {
+		target-path = "/";
+		board_config {
+			ids = "3701-0000-*", "3701-0005-*";
+		};
+		__overlay__ {
+			compatible = "nvidia,p3737-0000+p3701-0000-as-p3701-0004", "nvidia,tegra234";
+			model = "Jetson AGX Orin as JAO-40W";
+		};
+	};
+};

overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0000.dts

@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	overlay-name = "Tegra234 p3701-0000-as-p3767-0000 Emulation Overlay";
+
+	fragment-t234-p3701-0000-as-p3767-0000@0 {
+		target-path = "/";
+		board_config {
+			ids = "3701-0000-*", "3701-0005-*";
+		};
+		__overlay__ {
+			compatible = "nvidia,p3737-0000+p3701-0000-as-p3767-0000", "nvidia,tegra234";
+			model = "Jetson AGX Orin as NX-16GB";
+			opp-table-cluster0 {
+				opp-1984000000 { /* Max CPU freq for ONX */
+					opp-hz = /bits/ 64 <1984000000>;
+					opp-peak-kBps = <3200000>;
+				};
+			};
+			opp-table-cluster1 {
+				opp-1984000000 { /* Max CPU freq for ONX */
+					opp-hz = /bits/ 64 <1984000000>;
+					opp-peak-kBps = <3200000>;
+				};
+			};
+			opp-table-cluster2 {
+				opp-1984000000 { /* Max CPU freq for ONX */
+					opp-hz = /bits/ 64 <1984000000>;
+					opp-peak-kBps = <3200000>;
+				};
+			};
+		};
+	};
+};

overlay/tegra234-p3737-0000+p3701-0000-as-p3767-0001.dts

@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+
+/dts-v1/;
+/plugin/;
+
+/ {
+	overlay-name = "Tegra234 p3701-0000-as-p3767-0001 Emulation Overlay";
+
+	fragment-t234-p3701-0000-as-p3767-0001@0 {
+		target-path = "/";
+		board_config {
+			ids = "3701-0000-*", "3701-0005-*";
+		};
+		__overlay__ {
+			compatible = "nvidia,p3737-0000+p3701-0000-as-p3767-0001", "nvidia,tegra234";
+			model = "Jetson AGX Orin as NX-8GB";
+			bus@0 {
+				host1x@13e00000 {
+					nvdla1@158c0000 {
+						status = "disabled";
+					};
+				};
+			};
+			opp-table-cluster0 {
+				opp-1984000000 { /* Max CPU freq for ONX */
+					opp-hz = /bits/ 64 <1984000000>;
+					opp-peak-kBps = <3200000>;
+				};
+			};
+			opp-table-cluster1 {
+				opp-1984000000 { /* Max CPU freq for ONX */
+					opp-hz = /bits/ 64 <1984000000>;
+					opp-peak-kBps = <3200000>;
+				};
+			};
+			opp-table-cluster2 {
+				opp-1984000000 { /* Max CPU freq for ONX */
+					opp-hz = /bits/ 64 <1984000000>;
+					opp-peak-kBps = <3200000>;
+				};
+			};
+		};
+	};
+};